From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 76DE021123881 for ; Wed, 6 Jun 2018 05:37:06 -0700 (PDT) Received: by mail-wm0-x242.google.com with SMTP id v131-v6so11690526wma.1 for ; Wed, 06 Jun 2018 05:37:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=BUEzLBtRu5nLMbJ2Aru3DPpnGGMn5000aGMKvy/o4jA=; b=N5lRsMpg/TA29RFLxEoziFv63wd1Q+lN2RHl41cItZjCS3VQNp/qC/2yKhKxs7vMV3 Hp6qb+Qt6yvzBgzxsMo+bUmwjCAsq9rn6mZuN6JVbks9UBJOwrq1aJNFLTK/hSnyvCKF /ZSfSG/2lrppdBM+/6xWjKf+vTAIWvS15l+60= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=BUEzLBtRu5nLMbJ2Aru3DPpnGGMn5000aGMKvy/o4jA=; b=kN45/rSSSb0r9jMfzzYQ+MK+eZ7kxrqORdghy7dbM4wBJMppvKdnMZ8vdMAaVuyoex Ekof/vvZvAupZLXhJIp1luIMrUSIml38epc30hkQUVHq9c0pvICzLWQQ4r+xEFxaRo5e U069ZP5L23iEbFLr0imWlPNyWlLrb//FCWrPgKrhos92RB97ube20mimKgYLPbto6nHJ XSHh0vbb7yH4jV7xeawrNaHR3PYQFgbRk5Jag2/GhFrws39gPyERYg+pHTcM/qF80FuG mJEW+ojzam/ql67QBDGikt1sY92VQFeq2+3+lmo+qPivNrZ4Tkk9GURtiU3x0YnPd8Jt gnxw== X-Gm-Message-State: APt69E2kaCWhKE5WLFesOtEZOZdBLl8A4AL+959fLSi4f7F3wzgvgh59 TuG/09YPmmIdA5+YNCGOiXgtYdX4R90= X-Google-Smtp-Source: ADUXVKJPKL1n1BNZru2mP2KXwgRGWy+jNpKCEg+z59hxsAPv+FnFFTJ6NeF8Ugl49YdsPyuxmG5+1w== X-Received: by 2002:a1c:5e85:: with SMTP id s127-v6mr1769173wmb.123.1528288624116; Wed, 06 Jun 2018 05:37:04 -0700 (PDT) Received: from dogfood.home ([2a01:cb1d:112:6f00:e8af:f8ab:ef29:1cd5]) by smtp.gmail.com with ESMTPSA id g4-v6sm10266518wrq.32.2018.06.06.05.37.02 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 06 Jun 2018 05:37:03 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, Ard Biesheuvel Date: Wed, 6 Jun 2018 14:37:01 +0200 Message-Id: <20180606123701.4275-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.0 Subject: [PATCH] ArmPkg/ArmSmcPsciResetSystemLib: implement fallback for warm reboot X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 06 Jun 2018 12:37:06 -0000 Implement ResetSystemLib's EnterS3WithImmediateWake() routine using a jump back to the PEI entry point with interrupts and MMU+caches disabled. This is only possible at boot time, when we are sure that the current CPU is the only one up and running. Also, it depends on the platform whether the PEI code is preserved in memory (it may be copied to DRAM rather than execute in place), so also add a feature PCD to selectively enable this feature. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/ArmPkg.dec | 4 ++++ ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c | 21 ++++++++++++++++++-- ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf | 9 +++++++++ 3 files changed, 32 insertions(+), 2 deletions(-) diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index debe066b6f7b..3aa229fe2ec9 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -85,6 +85,10 @@ [PcdsFeatureFlag.common] # Define if the GICv3 controller should use the GICv2 legacy gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042 + # Whether to implement warm reboot for capsule update using a jump back to the + # PEI entry point with caches and interrupts disabled. + gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot|FALSE|BOOLEAN|0x0000001F + [PcdsFeatureFlag.ARM] # Whether to map normal memory as non-shareable. FALSE is the safe choice, but # TRUE may be appropriate to fix performance problems if you don't care about diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c index d6d26bce5009..cb75e32771c2 100644 --- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c +++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c @@ -15,10 +15,13 @@ #include +#include +#include #include #include #include -#include +#include +#include #include @@ -89,7 +92,21 @@ EnterS3WithImmediateWake ( VOID ) { - // Not implemented + VOID (*Reset)(VOID); + + if (FeaturePcdGet (PcdArmReenterPeiForCapsuleWarmReboot) && + !EfiAtRuntime ()) { + // + // At boot time, we are the only core running, so we can implement the + // immediate wake (which is used by capsule update) by disabling the MMU + // and interrupts, and jumping to the PEI entry point. + // + Reset = (VOID *)(UINTN)FixedPcdGet64 (PcdFvBaseAddress); + + gBS->RaiseTPL (TPL_HIGH_LEVEL); + ArmDisableMmu (); + Reset (); + } } /** diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf index 5a1ee976e5bc..19021cd1e8b6 100644 --- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf +++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf @@ -30,6 +30,15 @@ [Packages] MdePkg/MdePkg.dec [LibraryClasses] + ArmMmuLib ArmSmcLib BaseLib DebugLib + UefiBootServicesTableLib + UefiRuntimeLib + +[FeaturePcd] + gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvBaseAddress -- 2.17.0