From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::230; helo=mail-wr0-x230.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x230.google.com (mail-wr0-x230.google.com [IPv6:2a00:1450:400c:c0c::230]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id BA1AA21217973 for ; Tue, 12 Jun 2018 04:23:40 -0700 (PDT) Received: by mail-wr0-x230.google.com with SMTP id a12-v6so23682942wro.1 for ; Tue, 12 Jun 2018 04:23:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MymDKa3gGQke6glFvCyLm6c+eSZPG5i3Z0yqNFbX1mQ=; b=MIMT41tXqv5ZnmhFwkPLU4brhN3zljj3MNA0VRg1+mBaF4tqLe2RrZm0+fHelY2XwM xvA3I5xeT7Tx+elM0AZar2UTkVBJsKs9N8JZ6dmw8LGvxMoh0YhfuhLcvO2/MakaH7q9 G9h7sv9Xqqqjw8/24JRlAP3oWW6H11UL4Wd8U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=MymDKa3gGQke6glFvCyLm6c+eSZPG5i3Z0yqNFbX1mQ=; b=Q5vxPnR/k9A+UbeQp6CdbGeNSF5IVH8e6UfFz8jKNbRVkkGjJTi9M2jtZlppOIbsXo pHh6NPIA69bL5VRFCBAcK2qUlBpGVTfgUtxOE7KmMX1BffrmQKe9iPQ7OmvM6pwp5p2a yaW8Ji5jfa1Frd9MTteAx1jwHglx5geNDSrjX8x0WJxTSUWBnnCU48qKRWpVfpMoVgg8 Ot3fv09U2SSD+HeNwJ6VviDz1CEa0xAaZ9c6REOhn8/rRpFaWIwkN6kcR9zMQLi9pl7q +oON4cB6jfmqZSVTTLVix/zuiu6n+QTmO2pTAWE2m56iaWaQHhGpy/28ZTPh+cNucvQ6 kpjQ== X-Gm-Message-State: APt69E2PHHrVtQDnuFS5EUnxX96N1Evh0zExeLJyRptpvCYhvFyEKp0X ICo5bDeOXO+ipbQvaHFn8pIbCPKkpoU= X-Google-Smtp-Source: ADUXVKK9ANFuEcxA/+f4nbfN3nrCZSj3s4cdPszYMqRU+KB5Rn5qkguisMMrykg5Oo9nCoffIi2QZA== X-Received: by 2002:adf:c70e:: with SMTP id k14-v6mr2198126wrg.16.1528802618882; Tue, 12 Jun 2018 04:23:38 -0700 (PDT) Received: from dogfood.home ([2a01:cb1d:112:6f00:3c84:18ae:27f2:d03]) by smtp.gmail.com with ESMTPSA id o16-v6sm1177202wrp.8.2018.06.12.04.23.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Jun 2018 04:23:38 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, star.zeng@intel.com, jiewen.yao@intel.com, michael.d.kinney@intel.com, Ard Biesheuvel Date: Tue, 12 Jun 2018 13:23:29 +0200 Message-Id: <20180612112329.664-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180612112329.664-1-ard.biesheuvel@linaro.org> References: <20180612112329.664-1-ard.biesheuvel@linaro.org> Subject: [PATCH v3 4/4] ArmPkg/ArmSmcPsciResetSystemLib: implement fallback for warm reboot X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jun 2018 11:23:41 -0000 Implement ResetSystemLib's EnterS3WithImmediateWake() routine using a jump back to the PEI entry point with interrupts and MMU+caches disabled. This is only possible at boot time, when we are sure that the current CPU is the only one up and running. Also, it depends on the platform whether the PEI code is preserved in memory (it may be copied to DRAM rather than execute in place), so also add a feature PCD to selectively enable this feature. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- ArmPkg/ArmPkg.dec | 4 ++++ ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c | 21 ++++++++++++++++++-- ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf | 9 +++++++++ 3 files changed, 32 insertions(+), 2 deletions(-) diff --git a/ArmPkg/ArmPkg.dec b/ArmPkg/ArmPkg.dec index debe066b6f7b..3aa229fe2ec9 100644 --- a/ArmPkg/ArmPkg.dec +++ b/ArmPkg/ArmPkg.dec @@ -85,6 +85,10 @@ [PcdsFeatureFlag.common] # Define if the GICv3 controller should use the GICv2 legacy gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE|BOOLEAN|0x00000042 + # Whether to implement warm reboot for capsule update using a jump back to the + # PEI entry point with caches and interrupts disabled. + gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot|FALSE|BOOLEAN|0x0000001F + [PcdsFeatureFlag.ARM] # Whether to map normal memory as non-shareable. FALSE is the safe choice, but # TRUE may be appropriate to fix performance problems if you don't care about diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c index d6d26bce5009..10ceafd14d5d 100644 --- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c +++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.c @@ -15,10 +15,13 @@ #include +#include +#include #include #include #include -#include +#include +#include #include @@ -89,7 +92,21 @@ EnterS3WithImmediateWake ( VOID ) { - // Not implemented + VOID (*Reset)(VOID); + + if (FeaturePcdGet (PcdArmReenterPeiForCapsuleWarmReboot) && + !EfiAtRuntime ()) { + // + // At boot time, we are the only core running, so we can implement the + // immediate wake (which is used by capsule update) by disabling the MMU + // and interrupts, and jumping to the PEI entry point. + // + Reset = (VOID (*)(VOID))(UINTN)FixedPcdGet64 (PcdFvBaseAddress); + + gBS->RaiseTPL (TPL_HIGH_LEVEL); + ArmDisableMmu (); + Reset (); + } } /** diff --git a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf index 5a1ee976e5bc..19021cd1e8b6 100644 --- a/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf +++ b/ArmPkg/Library/ArmSmcPsciResetSystemLib/ArmSmcPsciResetSystemLib.inf @@ -30,6 +30,15 @@ [Packages] MdePkg/MdePkg.dec [LibraryClasses] + ArmMmuLib ArmSmcLib BaseLib DebugLib + UefiBootServicesTableLib + UefiRuntimeLib + +[FeaturePcd] + gArmTokenSpaceGuid.PcdArmReenterPeiForCapsuleWarmReboot + +[FixedPcd] + gArmTokenSpaceGuid.PcdFvBaseAddress -- 2.17.1