From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 989682127756A for ; Tue, 12 Jun 2018 07:24:27 -0700 (PDT) Received: by mail-wm0-x244.google.com with SMTP id p126-v6so21010904wmb.2 for ; Tue, 12 Jun 2018 07:24:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=7CCuY89me4Eu2ImjDuTN3w9PvDZ+3480mv4piw1Vk6E=; b=GHHYFf4Uvuwow4bRzU44QSSCXCpkiTojSxIWpujVhLOS/R2fjMIn5ewqyO8hC7CEzW /JAR7qu0LrRTxMyLcdr4GyinOTgTsQma+EIksbFiSwa1a8eS/an1PwQuacsouRaXHQcZ ChnQybzUhFp5Y0dzcqcWh/sK/gfr5xDjo7izY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=7CCuY89me4Eu2ImjDuTN3w9PvDZ+3480mv4piw1Vk6E=; b=cZGCSY8LilZj7pISJXftr6mkIw2ymXl+DL8lxaGbJC40nm5vCRxBuZ1BckUFzH0Yo/ mcTQ8YIWKYaIu+TukphVO1uqjzY9W8oDMylSieN3ZsXV4siLlUHAuYQ0xt7VvIvJT2aU nidnnPlLRkShtRahGNG0E+ydZAZ69Qwzk2n9ajyNRP7OR2lO+gusem+A0Ox+/L0ajl6k 3u11nqtuf5h8VAs4+aenSM2k2s7v9cOpo/y6UwRcSJKXJrh4W67jJ/XMW0secrbfBZD5 OCpq03f4E/R1ttxlifPrs7FWV9Vf3aYvdxeXmgxAw/60wQIPJz/vVKH0hGweBLuBk7xd l86w== X-Gm-Message-State: APt69E3QSahMGMFq3/c900bTLFQiS/uW8z31vg8IUlzw+EvsVFwrtDXq 94OvWcZ3RzH/gC6xZgeqh8qf4g== X-Google-Smtp-Source: ADUXVKJF13lIWgMkGo1PRm510u14RACGYFYTQvgN4J+PK/rey8J7hf09s/woSTCbMkhgNvbyjSbXvw== X-Received: by 2002:a7b:c01a:: with SMTP id c26-v6mr424192wmb.33.1528813465976; Tue, 12 Jun 2018 07:24:25 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id f2-v6sm434738wre.16.2018.06.12.07.24.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Jun 2018 07:24:13 -0700 (PDT) Date: Tue, 12 Jun 2018 15:23:49 +0100 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, jinghua@marvell.com, jsd@semihalf.com, jaz@semihalf.com Message-ID: <20180612142349.jjf26c73suspq6jc@bivouac.eciton.net> References: <1528812395-2716-1-git-send-email-mw@semihalf.com> <1528812395-2716-3-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1528812395-2716-3-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jun 2018 14:24:27 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline I have only bikeshedding-level comments on this set, inline below. (Applies to at lest 2-3.) On Tue, Jun 12, 2018 at 04:06:34PM +0200, Marcin Wojtas wrote: > Add new board description file Armada80x0McBin.dsc, > which uses common Armada7k8k.fdf file. By default > build capsule components. > Most of the interfaces are fully functional, except for: > - USB ports - it requires merging GPIO support and VBUS > power supply enabling > - SdMmc ports - they are kept enabled, as no issues were > observed on v1.3 board so far. However higher speed modes > (HS200) and full stability will be gained after Xenon > driver improvements merge. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > --- > Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 149 ++++++++++++++++++++ > 1 file changed, 149 insertions(+) > create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc > > diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc > new file mode 100644 > index 0000000..1a811d5 > --- /dev/null > +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc > @@ -0,0 +1,149 @@ > +#Copyright (C) 2017 Marvell International Ltd. > +# > +#Marvell BSD License Option > +# > +#If you received this File from Marvell, you may opt to use, redistribute and/or > +#modify this File under the following licensing terms. > +#Redistribution and use in source and binary forms, with or without modification, > +#are permitted provided that the following conditions are met: > +# > +# * Redistributions of source code must retain the above copyright notice, > +# this list of conditions and the following disclaimer. > +# > +# * Redistributions in binary form must reproduce the above copyright > +# notice, this list of conditions and the following disclaimer in the > +# documentation and/or other materials provided with the distribution. > +# > +# * Neither the name of Marvell nor the names of its contributors may be > +# used to endorse or promote products derived from this software without > +# specific prior written permission. > +# > +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND > +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED > +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE > +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR > +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES > +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; > +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS > +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > +# > +################################################################################ > +# > +# Defines Section - statements that will be processed to create a Makefile. > +# > +################################################################################ > +[Defines] > + PLATFORM_NAME = Armada80x0McBin > + PLATFORM_GUID = 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62 > + PLATFORM_VERSION = 0.1 > + DSC_SPECIFICATION = 0x00010019 Can be stepped to ...001A now. > + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH) > + SUPPORTED_ARCHITECTURES = AARCH64|ARM > + BUILD_TARGETS = DEBUG|RELEASE Question for Ard as much as anything else - should we start considering NOOPT to be something we want enabled in newly added platforms? / Leif > + SKUID_IDENTIFIER = DEFAULT > + FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf > + CAPSULE_ENABLE = TRUE > + > +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc > + > +################################################################################ > +# > +# Pcd Section - list of all EDK II PCD Entries defined by this Platform > +# > +################################################################################ > +[PcdsFixedAtBuild.common] > + #MPP > + gMarvellTokenSpaceGuid.PcdMppChipCount|3 > + > + # APN806-A0 MPP SET > + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE > + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 > + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 > + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 } > + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 } > + > + # CP110 MPP SET - master > + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE > + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 > + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 > + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } > + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } > + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } > + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2, 0x2, 0x2, 0xA } > + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE, 0xE, 0xE, 0xE } > + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } > + > + # CP110 MPP SET - slave > + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE > + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 > + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 > + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8, 0x8, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF } > + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } > + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } > + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } > + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } > + > + #SPI > + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680 > + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 > + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 > + > + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 > + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 > + > + #ComPhy > + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } > + # ComPhy0 > + # 0: PCIE0 5 Gbps > + # 1: PCIE0 5 Gbps > + # 2: PCIE0 5 Gbps > + # 3: PCIE0 5 Gbps > + # 4: SFI 10.31 Gbps > + # 5: SATA1 5 Gbps > + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)} > + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } > + # ComPhy1 > + # 0: SGMII1 1.25 Gbps > + # 1: SATA0 5 Gbps > + # 2: USB3_HOST0 5 Gbps > + # 3: SATA1 5 Gbps > + # 4: SFI 10.31 Gbps > + # 5: SGMII2 3.125 Gbps > + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) } > + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) } > + > + #UtmiPhy > + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 } > + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } > + > + #MDIO > + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } > + > + #PHY > + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 } > + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 } > + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 } > + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE > + > + #NET > + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 } > + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 } > + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) } > + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) } > + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF } > + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 } > + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 } > + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } > + > + #PciEmulation > + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 } > + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } > + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } > + > + #RTC > + gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 } > -- > 2.7.4 >