Re: [platforms PATCH 15/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with ComPhy information

[Leif Lindholm <leif.lindholm@linaro.org>]

On Fri, Jun 08, 2018 at 05:34:13PM +0200, Marcin Wojtas wrote:
> This patch introduces new library callback (ArmadaSoCDescComPhyGet ()),
> which dynamically allocates and fills MV_SOC_COMPHY_DESC structure with
> the SoC description of ComPhy SerDes controllers.
> 
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> Reviewed-by: Hua Jing <jinghua@marvell.com>
> ---
>  Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 40 ++++++++++++++++++++
>  Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h                             | 20 ++++++++++
>  2 files changed, 60 insertions(+)
> 
> diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> index de57b47..ba44a0c 100644
> --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c
> @@ -32,6 +32,46 @@
>  #define MV_SOC_CP_BASE(Cp)               (0xF2000000 + (Cp) * 0x2000000)
>  
>  //
> +// Platform description of ComPhy controllers
> +//
> +#define MV_SOC_COMPHY_BASE(Cp)           (MV_SOC_CP_BASE ((Cp)) + 0x441000)
> +#define MV_SOC_HPIPE3_BASE(Cp)           (MV_SOC_CP_BASE ((Cp)) + 0x120000)
> +#define MV_SOC_COMPHY_LANE_COUNT         6
> +#define MV_SOC_COMPHY_MUX_BITS           4
> +
> +EFI_STATUS
> +EFIAPI
> +ArmadaSoCDescComPhyGet (
> +  IN OUT MV_SOC_COMPHY_DESC  **ComPhyDesc,
> +  IN OUT UINT8                *DescCount

Make it UINTN please.

> +  )
> +{
> +  MV_SOC_COMPHY_DESC *Desc;
> +  UINT8 CpCount = FixedPcdGet8 (PcdMaxCpCount);
> +  UINT8 CpIndex;

UINTN x2.

/
    Leif

> +
> +  Desc = AllocateZeroPool (CpCount * sizeof (MV_SOC_COMPHY_DESC));
> +  if (Desc == NULL) {
> +    DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__));
> +    return EFI_OUT_OF_RESOURCES;
> +  }
> +
> +  for (CpIndex = 0; CpIndex < CpCount; CpIndex++) {
> +    Desc[CpIndex].ComPhyBaseAddress = MV_SOC_COMPHY_BASE (CpIndex);
> +    Desc[CpIndex].ComPhyHpipe3BaseAddress = MV_SOC_HPIPE3_BASE (CpIndex);
> +    Desc[CpIndex].ComPhyLaneCount = MV_SOC_COMPHY_LANE_COUNT;
> +    Desc[CpIndex].ComPhyMuxBitCount = MV_SOC_COMPHY_MUX_BITS;
> +    Desc[CpIndex].ComPhyChipType = MvComPhyTypeCp110;
> +    Desc[CpIndex].ComPhyId = CpIndex;
> +  }
> +
> +  *ComPhyDesc = Desc;
> +  *DescCount = CpCount;
> +
> +  return EFI_SUCCESS;
> +}
> +
> +//
>  // Platform description of NonDiscoverableDevices
>  //
>  
> diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> index 438f838..791d58b 100644
> --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h
> @@ -14,9 +14,29 @@
>  #ifndef __ARMADA_SOC_DESC_LIB_H__
>  #define __ARMADA_SOC_DESC_LIB_H__
>  
> +#include <Library/MvComPhyLib.h>
>  #include <Library/NonDiscoverableDeviceRegistrationLib.h>
>  
>  //
> +// ComPhy SoC description
> +//
> +typedef struct {
> +  UINTN ComPhyId;
> +  UINTN ComPhyBaseAddress;
> +  UINTN ComPhyHpipe3BaseAddress;
> +  UINTN ComPhyLaneCount;
> +  UINTN ComPhyMuxBitCount;
> +  MV_COMPHY_CHIP_TYPE ComPhyChipType;
> +} MV_SOC_COMPHY_DESC;
> +
> +EFI_STATUS
> +EFIAPI
> +ArmadaSoCDescComPhyGet (
> +  IN OUT MV_SOC_COMPHY_DESC  **ComPhyDesc,
> +  IN OUT UINT8                *DescCount
> +  );
> +
> +//
>  // NonDiscoverable devices SoC description
>  //
>  // AHCI
> -- 
> 2.7.4
>