From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 67509213030BB for ; Tue, 12 Jun 2018 13:51:46 -0700 (PDT) Received: by mail-wr0-x241.google.com with SMTP id e18-v6so415204wrs.5 for ; Tue, 12 Jun 2018 13:51:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=pTuV7qlbraXZq83DAlGoiAd+e/gLj+b09Ut0P7rUf1k=; b=AzzJ075QtyCYZVtk14ZdeHLV3BsjPXMRjGpJgS/OE/JU8ypzHkOASo/2KYwFbPObjS Tb7w22je/cTEEVGL8aoDZtTILo5tGYRvCm29JbuBG9ih9doEvbaRZzjdtRto4h62Aayq 8DCMoR54ny88KTz3RIiA04GQUlU6h+YxFR9s8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=pTuV7qlbraXZq83DAlGoiAd+e/gLj+b09Ut0P7rUf1k=; b=ullvaRdqij8/jC5T7Lj8dZT79b5EXjE/K4j3omo3/H9O80k3LiugY+/9+fKGIg/usG o+oI5QdsageRgvtbjhUutjIZN/s7sFbQ3pVocSK7HN7nO2kp0B3AQzvsthwmis5q/UhU u0U6n3ZTBEGHeNlidWD+kHHReZPmo5bkq7VKCIA0Rz45SxTX6KVC+R+zPE7UJWCtfmag zrfrKpP+MobjYuu4NEdMYFlmoYhwbhj3fikkjw4Zyu2EKVIZZ1CzjFy4PTcsINE8RDWG fJMK41F2BT/s4+RunODIhixajNQ7IScTMry1ASerQWglmEDFccIMJLs1HeV/Ke+9QM2F 3njQ== X-Gm-Message-State: APt69E3/ibmStaKpq81SX79OHTTQexXFltbCBXI9W0hUeSaw0sbtvED5 3kE8GqRhXzABOBezYsjThFqKmQ== X-Google-Smtp-Source: ADUXVKIZl0ibH3FqE7C4AZUYzE6QvVrNAimXA3mZ2JLgTossN1UeJKACkXmfPONF7xF90cl5/GMyMQ== X-Received: by 2002:adf:9025:: with SMTP id h34-v6mr1931876wrh.123.1528836704489; Tue, 12 Jun 2018 13:51:44 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id n71-v6sm2223483wmi.14.2018.06.12.13.51.42 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Jun 2018 13:51:43 -0700 (PDT) Date: Tue, 12 Jun 2018 21:51:41 +0100 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, jinghua@marvell.com, jsd@semihalf.com, jaz@semihalf.com Message-ID: <20180612205141.sgwnmujxjfp5sjku@bivouac.eciton.net> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> <1528472063-1660-16-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1528472063-1660-16-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms PATCH 15/25] Marvell/Armada7k8k: Extend ArmadaSoCDescLib with ComPhy information X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jun 2018 20:51:46 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Jun 08, 2018 at 05:34:13PM +0200, Marcin Wojtas wrote: > This patch introduces new library callback (ArmadaSoCDescComPhyGet ()), > which dynamically allocates and fills MV_SOC_COMPHY_DESC structure with > the SoC description of ComPhy SerDes controllers. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > Reviewed-by: Hua Jing > --- > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 40 ++++++++++++++++++++ > Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 20 ++++++++++ > 2 files changed, 60 insertions(+) > > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c > index de57b47..ba44a0c 100644 > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c > @@ -32,6 +32,46 @@ > #define MV_SOC_CP_BASE(Cp) (0xF2000000 + (Cp) * 0x2000000) > > // > +// Platform description of ComPhy controllers > +// > +#define MV_SOC_COMPHY_BASE(Cp) (MV_SOC_CP_BASE ((Cp)) + 0x441000) > +#define MV_SOC_HPIPE3_BASE(Cp) (MV_SOC_CP_BASE ((Cp)) + 0x120000) > +#define MV_SOC_COMPHY_LANE_COUNT 6 > +#define MV_SOC_COMPHY_MUX_BITS 4 > + > +EFI_STATUS > +EFIAPI > +ArmadaSoCDescComPhyGet ( > + IN OUT MV_SOC_COMPHY_DESC **ComPhyDesc, > + IN OUT UINT8 *DescCount Make it UINTN please. > + ) > +{ > + MV_SOC_COMPHY_DESC *Desc; > + UINT8 CpCount = FixedPcdGet8 (PcdMaxCpCount); > + UINT8 CpIndex; UINTN x2. / Leif > + > + Desc = AllocateZeroPool (CpCount * sizeof (MV_SOC_COMPHY_DESC)); > + if (Desc == NULL) { > + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); > + return EFI_OUT_OF_RESOURCES; > + } > + > + for (CpIndex = 0; CpIndex < CpCount; CpIndex++) { > + Desc[CpIndex].ComPhyBaseAddress = MV_SOC_COMPHY_BASE (CpIndex); > + Desc[CpIndex].ComPhyHpipe3BaseAddress = MV_SOC_HPIPE3_BASE (CpIndex); > + Desc[CpIndex].ComPhyLaneCount = MV_SOC_COMPHY_LANE_COUNT; > + Desc[CpIndex].ComPhyMuxBitCount = MV_SOC_COMPHY_MUX_BITS; > + Desc[CpIndex].ComPhyChipType = MvComPhyTypeCp110; > + Desc[CpIndex].ComPhyId = CpIndex; > + } > + > + *ComPhyDesc = Desc; > + *DescCount = CpCount; > + > + return EFI_SUCCESS; > +} > + > +// > // Platform description of NonDiscoverableDevices > // > > diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h > index 438f838..791d58b 100644 > --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h > +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h > @@ -14,9 +14,29 @@ > #ifndef __ARMADA_SOC_DESC_LIB_H__ > #define __ARMADA_SOC_DESC_LIB_H__ > > +#include > #include > > // > +// ComPhy SoC description > +// > +typedef struct { > + UINTN ComPhyId; > + UINTN ComPhyBaseAddress; > + UINTN ComPhyHpipe3BaseAddress; > + UINTN ComPhyLaneCount; > + UINTN ComPhyMuxBitCount; > + MV_COMPHY_CHIP_TYPE ComPhyChipType; > +} MV_SOC_COMPHY_DESC; > + > +EFI_STATUS > +EFIAPI > +ArmadaSoCDescComPhyGet ( > + IN OUT MV_SOC_COMPHY_DESC **ComPhyDesc, > + IN OUT UINT8 *DescCount > + ); > + > +// > // NonDiscoverable devices SoC description > // > // AHCI > -- > 2.7.4 >