From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5800921276B89 for ; Tue, 12 Jun 2018 14:12:42 -0700 (PDT) Received: by mail-wm0-x242.google.com with SMTP id 69-v6so1374346wmf.3 for ; Tue, 12 Jun 2018 14:12:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=neHuqb1Jimpo9GrojYsyrMGm0xxORP3owQaqyzgT3QI=; b=Ofafge5R8mIrK0AK/7ceDPYDIyDBKMbx+11XRAvukolLlwavlJIFLvjPW3Oi5NEl+G PCWuiSV/pFGNUt4NepKFIMrPfZWMzA7YdJkbXdHZ61WGu88dQQIHIGXjXDUALiwb26SV 7ZJF5T9NWrI7Y9t+xUVfOTvpgGcRRMdzwt+Us= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=neHuqb1Jimpo9GrojYsyrMGm0xxORP3owQaqyzgT3QI=; b=fgLRmI6WTCoQ30w7V7v2VafcXTkVexb6E+xSwg1OCd8LIcK4DRt7zS/6k5Mq8HM9Oq w8+wnkhbN1G9/FSe7wiXCJna56zfc643Lpijxa+ienfAZAvZ+mME8lk27AKNuNiR0ein NJSh3adxWqrDACV57p51Q85S9UtMWCToVEwMbQwCW9TcbxYDL4U7MQoiKIGRLm/lAvCJ L/cgeGz+aClTHbrZPStagdxZIZylgbp41H9UCS51a8NsPxtucVvSZJa7wS+ub/yNODM6 0mnXdBBNJWgRACVdJAwCmwbM0qicVhzUfd073bCsuhx4fwXmy75hNUJzqKY346168ZSF /HkQ== X-Gm-Message-State: APt69E0iKL4/xDAcpP3cNZ2SqqWShXijDKH6ZsO3vZ9rjAzas8AkDt/x X7M+enwMEpWL3V4ig4iqezgbxg== X-Google-Smtp-Source: ADUXVKI8SgSu7maYimH+KxWt1tUEZd+trdRdBmyiHGj/xthd1xiJHlAm3LZNVU1AZvtz2iU4xj8VWQ== X-Received: by 2002:a1c:9c0b:: with SMTP id f11-v6mr1589624wme.148.1528837960813; Tue, 12 Jun 2018 14:12:40 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id n17-v6sm1823659wmd.14.2018.06.12.14.12.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Jun 2018 14:12:39 -0700 (PDT) Date: Tue, 12 Jun 2018 22:12:38 +0100 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, jinghua@marvell.com, jsd@semihalf.com, jaz@semihalf.com Message-ID: <20180612211238.en72vqgp5cbbfdda@bivouac.eciton.net> References: <1528472063-1660-1-git-send-email-mw@semihalf.com> <1528472063-1660-18-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1528472063-1660-18-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms PATCH 17/25] Marvell/Library: ComPhyLib: Switch library to use MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jun 2018 21:12:42 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Jun 08, 2018 at 05:34:15PM +0200, Marcin Wojtas wrote: > MvComPhyLib library used to get Armada7k8k SerDes multiplexing > controller description from hardcoded values stored in the header > file MvHwDescLib.h. As a result it is very hard to support other > Armada SoC families with this library. > > This patch updates the library, so that it can obtain the > description from newly introduced MARVELL_BOARD_DESC protocol, > and removes the dependency on the hardcoded structures. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > Reviewed-by: Hua Jing > --- > Silicon/Marvell/Include/Library/MvHwDescLib.h | 39 ----------- > Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c | 74 ++++++++++++-------- > 2 files changed, 45 insertions(+), 68 deletions(-) > > diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvell/Include/Library/MvHwDescLib.h > index 9f383f4..423ca17 100644 > --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h > +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h > @@ -35,8 +35,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > #ifndef __MVHWDESCLIB_H__ > #define __MVHWDESCLIB_H__ > > -#include > - > // > // Helper macros > // > @@ -45,20 +43,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > #define MVHW_DEV_ENABLED(type, index) (type ## DeviceTable[index]) > > // > -// CommonPhy devices description template definition > -// > -#define MVHW_MAX_COMPHY_DEVS 4 > - > -typedef struct { > - UINT8 ComPhyDevCount; > - UINTN ComPhyBaseAddresses[MVHW_MAX_COMPHY_DEVS]; > - UINTN ComPhyHpipe3BaseAddresses[MVHW_MAX_COMPHY_DEVS]; > - UINTN ComPhyLaneCount[MVHW_MAX_COMPHY_DEVS]; > - UINTN ComPhyMuxBitCount[MVHW_MAX_COMPHY_DEVS]; > - MV_COMPHY_CHIP_TYPE ComPhyChipType[MVHW_MAX_COMPHY_DEVS]; > -} MVHW_COMPHY_DESC; > - > -// > // I2C devices description template definition > // > #define MVHW_MAX_I2C_DEVS 4 > @@ -79,29 +63,6 @@ typedef struct { > } MVHW_MDIO_DESC; > > // > -// Platform description of CommonPhy devices > -// > -#define MVHW_CP0_COMPHY_BASE 0xF2441000 > -#define MVHW_CP0_HPIPE3_BASE 0xF2120000 > -#define MVHW_CP0_COMPHY_LANES 6 > -#define MVHW_CP0_COMPHY_MUX_BITS 4 > -#define MVHW_CP1_COMPHY_BASE 0xF4441000 > -#define MVHW_CP1_HPIPE3_BASE 0xF4120000 > -#define MVHW_CP1_COMPHY_LANES 6 > -#define MVHW_CP1_COMPHY_MUX_BITS 4 > - > -#define DECLARE_A7K8K_COMPHY_TEMPLATE \ > -STATIC \ > -MVHW_COMPHY_DESC mA7k8kComPhyDescTemplate = {\ > - 2,\ > - { MVHW_CP0_COMPHY_BASE, MVHW_CP1_COMPHY_BASE },\ > - { MVHW_CP0_HPIPE3_BASE, MVHW_CP1_HPIPE3_BASE },\ > - { MVHW_CP0_COMPHY_LANES, MVHW_CP1_COMPHY_LANES },\ > - { MVHW_CP0_COMPHY_MUX_BITS, MVHW_CP1_COMPHY_MUX_BITS },\ > - { MvComPhyTypeCp110, MvComPhyTypeCp110 }\ > -} > - > -// > // Platform description of I2C devices > // > #define MVHW_CP0_I2C0_BASE 0xF2701000 > diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c > index b03bc35..8555c4c 100644 > --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c > +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.c > @@ -34,9 +34,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > > #include "ComPhyLib.h" > #include > -#include > - > -DECLARE_A7K8K_COMPHY_TEMPLATE; > > CHAR16 * TypeStringTable [] = {L"unconnected", L"PCIE0", L"PCIE1", L"PCIE2", > L"PCIE3", L"SATA0", L"SATA1", L"SATA2", L"SATA3", > @@ -182,22 +179,20 @@ VOID > InitComPhyConfig ( > IN OUT CHIP_COMPHY_CONFIG *ChipConfig, > IN OUT PCD_LANE_MAP *LaneData, > - IN UINT8 Id > + IN MV_BOARD_COMPHY_DESC *Desc > ) > { > - MVHW_COMPHY_DESC *Desc = &mA7k8kComPhyDescTemplate; > - > - ChipConfig->ChipType = Desc->ComPhyChipType[Id]; > - ChipConfig->ComPhyBaseAddr = Desc->ComPhyBaseAddresses[Id]; > - ChipConfig->Hpipe3BaseAddr = Desc->ComPhyHpipe3BaseAddresses[Id]; > - ChipConfig->LanesCount = Desc->ComPhyLaneCount[Id]; > - ChipConfig->MuxBitCount = Desc->ComPhyMuxBitCount[Id]; > - ChipConfig->ChipId = Id; > + ChipConfig->ChipType = Desc->SoC->ComPhyChipType; > + ChipConfig->ComPhyBaseAddr = Desc->SoC->ComPhyBaseAddress; > + ChipConfig->Hpipe3BaseAddr = Desc->SoC->ComPhyHpipe3BaseAddress; > + ChipConfig->LanesCount = Desc->SoC->ComPhyLaneCount; > + ChipConfig->MuxBitCount = Desc->SoC->ComPhyMuxBitCount; > + ChipConfig->ChipId = Desc->SoC->ComPhyId; > > /* > * Below macro contains variable name concatenation (used to form PCD's name). > */ > - switch (Id) { > + switch (ChipConfig->ChipId) { > case 0: > GetComPhyPcd (LaneData, 0); > break; > @@ -219,32 +214,49 @@ MvComPhyInit ( > ) > { > EFI_STATUS Status; > - CHIP_COMPHY_CONFIG ChipConfig[MVHW_MAX_COMPHY_DEVS], *PtrChipCfg; > - PCD_LANE_MAP LaneData[MVHW_MAX_COMPHY_DEVS]; > + CHIP_COMPHY_CONFIG *ChipConfig, *PtrChipCfg; > + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; > + MV_BOARD_COMPHY_DESC *ComPhyBoardDesc; > + PCD_LANE_MAP *LaneData; > UINT32 Lane, MaxComphyCount; > - UINT8 *ComPhyDeviceTable, Index; > + UINT8 Index; UINTN. / Leif > > /* Obtain table with enabled ComPhy devices */ > - ComPhyDeviceTable = (UINT8 *)PcdGetPtr (PcdComPhyDevices); > - if (ComPhyDeviceTable == NULL) { > - DEBUG ((DEBUG_ERROR, "Missing PcdComPhyDevices\n")); > - return EFI_INVALID_PARAMETER; > + Status = gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, > + NULL, > + (VOID **)&BoardDescProtocol); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + Status = BoardDescProtocol->BoardDescComPhyGet (BoardDescProtocol, > + &ComPhyBoardDesc); > + if (EFI_ERROR (Status)) { > + return Status; > } > > - if (PcdGetSize (PcdComPhyDevices) > MVHW_MAX_COMPHY_DEVS) { > - DEBUG ((DEBUG_ERROR, "Wrong PcdComPhyDevices format\n")); > - return EFI_INVALID_PARAMETER; > + ChipConfig = AllocateZeroPool (ComPhyBoardDesc->ComPhyDevCount * > + sizeof (CHIP_COMPHY_CONFIG)); > + if (ChipConfig == NULL) { > + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); > + BoardDescProtocol->BoardDescFree (ComPhyBoardDesc); > + return EFI_OUT_OF_RESOURCES; > + } > + > + LaneData = AllocateZeroPool (ComPhyBoardDesc->ComPhyDevCount * > + sizeof (PCD_LANE_MAP)); > + if (ChipConfig == NULL) { > + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); > + BoardDescProtocol->BoardDescFree (ComPhyBoardDesc); > + FreePool (ChipConfig); > + return EFI_OUT_OF_RESOURCES; > } > > /* Initialize enabled chips */ > - for (Index = 0; Index < PcdGetSize (PcdComPhyDevices); Index++) { > - if (!MVHW_DEV_ENABLED (ComPhy, Index)) { > - DEBUG ((DEBUG_ERROR, "Skip ComPhy chip %d\n", Index)); > - continue; > - } > + for (Index = 0; Index < ComPhyBoardDesc->ComPhyDevCount; Index++) { > > PtrChipCfg = &ChipConfig[Index]; > - InitComPhyConfig(PtrChipCfg, LaneData, Index); > + InitComPhyConfig (PtrChipCfg, LaneData, &ComPhyBoardDesc[Index]); > > /* Get the count of the SerDes of the specific chip */ > MaxComphyCount = PtrChipCfg->LanesCount; > @@ -275,5 +287,9 @@ MvComPhyInit ( > PtrChipCfg->Init (PtrChipCfg); > } > > + BoardDescProtocol->BoardDescFree (ComPhyBoardDesc); > + FreePool (ChipConfig); > + FreePool (LaneData); > + > return EFI_SUCCESS; > } > -- > 2.7.4 >