From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AB19921306CC6 for ; Tue, 12 Jun 2018 15:59:24 -0700 (PDT) Received: by mail-wm0-x242.google.com with SMTP id l15-v6so16506865wmc.1 for ; Tue, 12 Jun 2018 15:59:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=2FsSSes/64MNr60WzCKMph5iIsX+IUhVSj9lO1eGB/A=; b=OU57TYq5qIT5tgcEeiBSzSw75R+Q+l3D28+bN+1RlrnAFdqzFQuyezWWj/YRTn4nUq j7I4sSsoa5jOfdxGnB6ZwDFXBnNXBQ090bu3sggjVknxQ9DsG9mbN5iky+U1yem0CH4A FRMyc1VmKCCOPx6zFc1SYl+LXlinxHZh5hW7w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=2FsSSes/64MNr60WzCKMph5iIsX+IUhVSj9lO1eGB/A=; b=eyJThH2USU32Md2ulpACfO+dQjqpCeDAxM6gs1RqPdwp5CF3MB+ldj6aZh/jztLrL0 KTk8hIBQ89b5MBwCvussC+FgG48HUv9OVTeHstidOiT1G2PvBOJd3wJBGGYtFD/dJ0tC wqtwltsP5CYhbi9paG4LjbhARHS3ae32Kz4R4A3z+nJDyRJ89/BfZohpG+Qcfu2ooqli 18vieL6bf7dvZ1BUQlohRhcovRtpkuHdeBX3IPq5Rl62RYw/e/kEV34XE0hsbUTZivfM hxDRtrEYio/X/kE5dtdSiz6QK8S5X95KPGpRB7gqjeFu90lZFMCleJy2eTbtPMyJmdWH DwHQ== X-Gm-Message-State: APt69E2AMFTkS09rDFJQkdckTlbaJ8c9htb7W4rEDoqQ1z+LFVDZ3bd7 YN4Dv7v/fBbYip/IdPS7me+ilA== X-Google-Smtp-Source: ADUXVKLwPC2Qj5YHPBxoK7eclB+6GVR6W6RfR8uJrw185BQyP8uAhtgeybZZmr+YUJuuJzm2wspIbw== X-Received: by 2002:a1c:8410:: with SMTP id g16-v6mr1838883wmd.26.1528844363031; Tue, 12 Jun 2018 15:59:23 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id u89-v6sm2092559wma.4.2018.06.12.15.59.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Jun 2018 15:59:21 -0700 (PDT) Date: Tue, 12 Jun 2018 23:59:19 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org Message-ID: <20180612225919.kroissnk2tusdw76@bivouac.eciton.net> References: <20180607150818.14393-1-ard.biesheuvel@linaro.org> <20180607150818.14393-3-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180607150818.14393-3-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 2/2] Silicon/NorFlashSynQuacerLib: describe entire firmware region as FV X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jun 2018 22:59:25 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Jun 07, 2018 at 05:08:18PM +0200, Ard Biesheuvel wrote: > In order to allow for more flexibility when updating parts of the > firmware via capsule update, expand the description of the code FV > to cover the entire 4 MB region at the base of the NOR flash. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c > index 816d8ba33f8c..357082c3d903 100644 > --- a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c > +++ b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c > @@ -23,8 +23,9 @@ STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = { > { > // UEFI code region > SYNQUACER_SPI_NOR_BASE, // device base > - FixedPcdGet64 (PcdFdBaseAddress), // region base > - FixedPcdGet32 (PcdFdSize), // region size > + SYNQUACER_SPI_NOR_BASE, // region base > + FixedPcdGet32 (PcdFlashNvStorageVariableBase) - > + SYNQUACER_SPI_NOR_BASE, // region size Could you define the size as a macro in Platform/MemoryMap.h? / Leif > SIZE_64KB, // block size > { > 0x19c118b0, 0xc423, 0x42be, { 0xb8, 0x0f, 0x70, 0x6f, 0x1f, 0xcb, 0x59, 0x9a } > -- > 2.17.0 >