From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E9BA7212733E4 for ; Wed, 13 Jun 2018 09:28:33 -0700 (PDT) Received: by mail-wm0-x244.google.com with SMTP id n5-v6so6547417wmc.5 for ; Wed, 13 Jun 2018 09:28:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=oSC3QiYXuo7vF2NE8qh7dnb1L7wt+1/sR2zveKZmqmE=; b=Otqr7Wk7REka1PD/VX/XezYNtGYONKTIL+GQmVPRVWE12hReDB9xVcOByflVsfVwrb ATGrOMmAuUJ2eyBlHPabStyOLwIiAmc6ob2xaLcSguMA2as802+z42tr4nqTKC6PYaMw jCOYMwiTZ5sAi3VOtqUuOcBHxrmsMfKVP8OsE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=oSC3QiYXuo7vF2NE8qh7dnb1L7wt+1/sR2zveKZmqmE=; b=XDgzaHoX+wMFunPDD+B38psMjd8GmmDJoq/36/Ez6sMqE9eK+1ee2aRob4sthYd1Kh O5345IzrnsXbDJpjxR5wBm4nJi+Y5qrn2lF+esxt+mNG0okIZJ7f+5/I8TPUyCS+Tu0w e/uN5lJcudi/wlIpZBqtSHfCzhA1MwmG+dWkP+DAbuwKbzOIu4CvCbKf3GPAzqbiwBRa gBVq88F9BvphnjQ1bF03gFVDVId+xF2qBHTfMwY1bKaPLbeGjyl3/g0mtOBdDk9RHNx2 teQiLiaMR9AKQAanvKK+QaJgNWI1uQGcF4VA1SS2LJzau2p7W5ANjykmDLTF6qf7cHxr lYag== X-Gm-Message-State: APt69E0pJEq5qahXbOSpbWURHBv4AJoj8oPbaPnnHw4Hn+o9Q+C2UlR6 fm1A13qchCmo0gnDGCK3rJli/d+QiRk= X-Google-Smtp-Source: ADUXVKIRYrpZ6znJKJ+ZF55vDTiOiQKqLaSQGWhFwIuw26Q/LdIIgngRvQlx+Bh+V75tRXDXuA77xw== X-Received: by 2002:a1c:903:: with SMTP id 3-v6mr4087677wmj.130.1528907312289; Wed, 13 Jun 2018 09:28:32 -0700 (PDT) Received: from dogfood.home ([2a01:cb1d:112:6f00:6dfc:b76c:4240:35ff]) by smtp.gmail.com with ESMTPSA id s191-v6sm6234782wmd.27.2018.06.13.09.28.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Jun 2018 09:28:31 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, Ard Biesheuvel Date: Wed, 13 Jun 2018 18:28:26 +0200 Message-Id: <20180613162826.19986-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180613162826.19986-1-ard.biesheuvel@linaro.org> References: <20180613162826.19986-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms v2 2/2] Silicon/NorFlashSynQuacerLib: describe entire firmware region as FV X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 13 Jun 2018 16:28:34 -0000 In order to allow for more flexibility when updating parts of the firmware via capsule update, expand the description of the code FV to cover the entire 4 MB region at the base of the NOR flash. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c index 816d8ba33f8c..d44fe3e4e94c 100644 --- a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c +++ b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c @@ -19,12 +19,20 @@ #include +#define FW_CODE_REGION_BASE SYNQUACER_SPI_NOR_BASE +#define FW_CODE_REGION_SIZE (FW_ENV_REGION_BASE - FW_CODE_REGION_BASE) + +#define FW_ENV_REGION_BASE FixedPcdGet32 (PcdFlashNvStorageVariableBase) +#define FW_ENV_REGION_SIZE (FixedPcdGet32 (PcdFlashNvStorageVariableSize) + \ + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + \ + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)) + STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = { { // UEFI code region SYNQUACER_SPI_NOR_BASE, // device base - FixedPcdGet64 (PcdFdBaseAddress), // region base - FixedPcdGet32 (PcdFdSize), // region size + FW_CODE_REGION_BASE, // region base + FW_CODE_REGION_SIZE, // region size SIZE_64KB, // block size { 0x19c118b0, 0xc423, 0x42be, { 0xb8, 0x0f, 0x70, 0x6f, 0x1f, 0xcb, 0x59, 0x9a } @@ -33,10 +41,8 @@ STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = { { // Environment variable region SYNQUACER_SPI_NOR_BASE, // device base - FixedPcdGet32 (PcdFlashNvStorageVariableBase), // region base - FixedPcdGet32 (PcdFlashNvStorageVariableSize) + - FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + - FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize), // region size + FW_ENV_REGION_BASE, // region base + FW_ENV_REGION_SIZE, // region size SIZE_64KB, // block size { 0x3105bd7a, 0x82c3, 0x486f, { 0xb1, 0x03, 0x1e, 0x09, 0x54, 0xec, 0x85, 0x75 } -- 2.17.1