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[2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id y8-v6sm18667086wrq.35.2018.06.18.09.09.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jun 2018 09:09:54 -0700 (PDT) Date: Mon, 18 Jun 2018 17:09:52 +0100 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, jinghua@marvell.com, jsd@semihalf.com, jaz@semihalf.com Message-ID: <20180618160952.kloaydbqe6fbylge@bivouac.eciton.net> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> <1529266325-18371-13-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1529266325-18371-13-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH v2 12/25] Marvell/Drivers: MvBoardDesc: Extend protocol with AHCI/SDMMC/XHCI X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jun 2018 16:09:57 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sun, Jun 17, 2018 at 10:11:52PM +0200, Marcin Wojtas wrote: > Introduce new callback that can provide information > about NonDiscoverableDevices to the relevant drivers and libraries. > > Extend ArmadaBoardDescLib with new structures (MV_BOARD_AHCI_DESC/ > MV_BOARD_SDMMC_DESC/MV_BOARD_XHCI_DESC) for holding board specific > data. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm > --- > Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf | 2 + > Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h | 28 +++ > Silicon/Marvell/Include/Protocol/BoardDesc.h | 24 +++ > Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c | 192 ++++++++++++++++++++ > 4 files changed, 246 insertions(+) > > diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf > index 6f57f06..cc0d9d4 100644 > --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf > +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.inf > @@ -57,6 +57,8 @@ > gMarvellBoardDescProtocolGuid > > [Pcd] > + gMarvellTokenSpaceGuid.PcdPciEAhci > + gMarvellTokenSpaceGuid.PcdPciESdhci > gMarvellTokenSpaceGuid.PcdPciEXhci > gMarvellTokenSpaceGuid.PcdPp2Controllers > gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled > diff --git a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h > index ab94877..7e4fa4d 100644 > --- a/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h > +++ b/Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h > @@ -17,6 +17,34 @@ > #include > > // > +// NonDiscoverableDevices per-board description > +// > + > +// > +// AHCI devices per-board description > +// > +typedef struct { > + MV_SOC_AHCI_DESC *SoC; > + UINTN AhciDevCount; > +} MV_BOARD_AHCI_DESC; > + > +// > +// SDMMC devices per-board description > +// > +typedef struct { > + MV_SOC_SDMMC_DESC *SoC; > + UINTN SdMmcDevCount; > +} MV_BOARD_SDMMC_DESC; > + > +// > +// XHCI devices per-board description > +// > +typedef struct { > + MV_SOC_XHCI_DESC *SoC; > + UINTN XhciDevCount; > +} MV_BOARD_XHCI_DESC; > + > +// > // PP2 NIC devices per-board description > // > typedef struct { > diff --git a/Silicon/Marvell/Include/Protocol/BoardDesc.h b/Silicon/Marvell/Include/Protocol/BoardDesc.h > index 114a0ec..edf9491 100644 > --- a/Silicon/Marvell/Include/Protocol/BoardDesc.h > +++ b/Silicon/Marvell/Include/Protocol/BoardDesc.h > @@ -43,6 +43,27 @@ typedef struct _MARVELL_BOARD_DESC_PROTOCOL MARVELL_BOARD_DESC_PROTOCOL; > > typedef > EFI_STATUS > +(EFIAPI *MV_BOARD_DESC_AHCI_GET) ( > + IN MARVELL_BOARD_DESC_PROTOCOL *This, > + IN OUT MV_BOARD_AHCI_DESC **AhciDesc > + ); > + > +typedef > +EFI_STATUS > +(EFIAPI *MV_BOARD_DESC_SDMMC_GET) ( > + IN MARVELL_BOARD_DESC_PROTOCOL *This, > + IN OUT MV_BOARD_SDMMC_DESC **SdMmcDesc > + ); > + > +typedef > +EFI_STATUS > +(EFIAPI *MV_BOARD_DESC_XHCI_GET) ( > + IN MARVELL_BOARD_DESC_PROTOCOL *This, > + IN OUT MV_BOARD_XHCI_DESC **XhciDesc > + ); > + > +typedef > +EFI_STATUS > (EFIAPI *MV_BOARD_DESC_PP2_GET) ( > IN MARVELL_BOARD_DESC_PROTOCOL *This, > IN OUT MV_BOARD_PP2_DESC **Pp2Desc > @@ -62,8 +83,11 @@ VOID > ); > > struct _MARVELL_BOARD_DESC_PROTOCOL { > + MV_BOARD_DESC_AHCI_GET BoardDescAhciGet; > MV_BOARD_DESC_PP2_GET BoardDescPp2Get; > + MV_BOARD_DESC_SDMMC_GET BoardDescSdMmcGet; > MV_BOARD_DESC_UTMI_GET BoardDescUtmiGet; > + MV_BOARD_DESC_XHCI_GET BoardDescXhciGet; > MV_BOARD_DESC_FREE BoardDescFree; > }; > > diff --git a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c > index 7c0bc39..3439017 100644 > --- a/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c > +++ b/Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c > @@ -37,6 +37,195 @@ MV_BOARD_DESC *mBoardDescInstance; > > STATIC > EFI_STATUS > +MvBoardDescAhciGet ( > + IN MARVELL_BOARD_DESC_PROTOCOL *This, > + IN OUT MV_BOARD_AHCI_DESC **AhciDesc > + ) > +{ > + UINT8 *AhciDeviceEnabled; > + UINTN AhciCount, AhciDeviceTableSize, AhciIndex, Index; > + MV_BOARD_AHCI_DESC *BoardDesc; > + MV_SOC_AHCI_DESC *SoCDesc; > + EFI_STATUS Status; > + > + /* Get SoC data about all available AHCI controllers */ > + Status = ArmadaSoCDescAhciGet (&SoCDesc, &AhciCount); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + /* > + * Obtain table with enabled AHCI controllers > + * which is represented as an array of UINT8 values > + * (0x0 - disabled, 0x1 enabled). > + */ > + AhciDeviceEnabled = PcdGetPtr (PcdPciEAhci); > + if (AhciDeviceEnabled == NULL) { > + /* No AHCI on the platform */ > + return EFI_SUCCESS; > + } > + > + AhciDeviceTableSize = PcdGetSize (PcdPciEAhci); > + > + /* Check if PCD with AHCI controllers is correctly defined */ > + if (AhciDeviceTableSize > AhciCount) { > + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciEAhci format\n", __FUNCTION__)); > + return EFI_INVALID_PARAMETER; > + } > + > + /* Allocate and fill board description */ > + BoardDesc = AllocateZeroPool (AhciDeviceTableSize * sizeof (MV_BOARD_AHCI_DESC)); > + if (BoardDesc == NULL) { > + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); > + return EFI_OUT_OF_RESOURCES; > + } > + > + AhciIndex = 0; > + for (Index = 0; Index < AhciDeviceTableSize; Index++) { > + if (!AhciDeviceEnabled[Index]) { > + DEBUG ((DEBUG_INFO, "%a: Skip Ahci controller %d\n", __FUNCTION__, Index)); > + continue; > + } > + > + BoardDesc[AhciIndex].SoC = &SoCDesc[Index]; > + AhciIndex++; > + } > + > + BoardDesc->AhciDevCount = AhciIndex; > + > + *AhciDesc = BoardDesc; > + > + return EFI_SUCCESS; > +} > + > +STATIC > +EFI_STATUS > +MvBoardDescSdMmcGet ( > + IN MARVELL_BOARD_DESC_PROTOCOL *This, > + IN OUT MV_BOARD_SDMMC_DESC **SdMmcDesc > + ) > +{ > + UINT8 *SdMmcDeviceEnabled; > + UINTN SdMmcCount, SdMmcDeviceTableSize, SdMmcIndex, Index; > + MV_BOARD_SDMMC_DESC *BoardDesc; > + MV_SOC_SDMMC_DESC *SoCDesc; > + EFI_STATUS Status; > + > + /* Get SoC data about all available SDMMC controllers */ > + Status = ArmadaSoCDescSdMmcGet (&SoCDesc, &SdMmcCount); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + /* > + * Obtain table with enabled SDMMC controllers > + * which is represented as an array of UINT8 values > + * (0x0 - disabled, 0x1 enabled). > + */ > + SdMmcDeviceEnabled = PcdGetPtr (PcdPciESdhci); > + if (SdMmcDeviceEnabled == NULL) { > + /* No SDMMC on platform */ > + return EFI_SUCCESS; > + } > + > + SdMmcDeviceTableSize = PcdGetSize (PcdPciESdhci); > + > + /* Check if PCD with SDMMC controllers is correctly defined */ > + if (SdMmcDeviceTableSize > SdMmcCount) { > + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciESdhci format\n", __FUNCTION__)); > + return EFI_INVALID_PARAMETER; > + } > + > + /* Allocate and fill board description */ > + BoardDesc = AllocateZeroPool (SdMmcDeviceTableSize * sizeof (MV_BOARD_SDMMC_DESC)); > + if (BoardDesc == NULL) { > + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); > + return EFI_OUT_OF_RESOURCES; > + } > + > + SdMmcIndex = 0; > + for (Index = 0; Index < SdMmcDeviceTableSize; Index++) { > + if (!SdMmcDeviceEnabled[Index]) { > + DEBUG ((DEBUG_INFO, "%a: Skip SdMmc controller %d\n", __FUNCTION__, Index)); > + continue; > + } > + > + BoardDesc[SdMmcIndex].SoC = &SoCDesc[Index]; > + SdMmcIndex++; > + } > + > + BoardDesc->SdMmcDevCount = SdMmcIndex; > + > + *SdMmcDesc = BoardDesc; > + > + return EFI_SUCCESS; > +} > + > +STATIC > +EFI_STATUS > +MvBoardDescXhciGet ( > + IN MARVELL_BOARD_DESC_PROTOCOL *This, > + IN OUT MV_BOARD_XHCI_DESC **XhciDesc > + ) > +{ > + UINT8 *XhciDeviceEnabled; > + UINTN XhciCount, XhciDeviceTableSize, XhciIndex, Index; > + MV_BOARD_XHCI_DESC *BoardDesc; > + MV_SOC_XHCI_DESC *SoCDesc; > + EFI_STATUS Status; > + > + /* Get SoC data about all available XHCI controllers */ > + Status = ArmadaSoCDescXhciGet (&SoCDesc, &XhciCount); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + /* > + * Obtain table with enabled XHCI controllers > + * which is represented as an array of UINT8 values > + * (0x0 - disabled, 0x1 enabled). > + */ > + XhciDeviceEnabled = PcdGetPtr (PcdPciEXhci); > + if (XhciDeviceEnabled == NULL) { > + /* No XHCI on platform */ > + return EFI_SUCCESS; > + } > + > + XhciDeviceTableSize = PcdGetSize (PcdPciEXhci); > + > + /* Check if PCD with XHCI controllers is correctly defined */ > + if (XhciDeviceTableSize > XhciCount) { > + DEBUG ((DEBUG_ERROR, "%a: Wrong PcdPciEXhci format\n", __FUNCTION__)); > + return EFI_INVALID_PARAMETER; > + } > + > + /* Allocate and fill board description */ > + BoardDesc = AllocateZeroPool (XhciDeviceTableSize * sizeof (MV_BOARD_XHCI_DESC)); > + if (BoardDesc == NULL) { > + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); > + return EFI_OUT_OF_RESOURCES; > + } > + > + XhciIndex = 0; > + for (Index = 0; Index < XhciDeviceTableSize; Index++) { > + if (!XhciDeviceEnabled[Index]) { > + DEBUG ((DEBUG_INFO, "%a: Skip Xhci controller %d\n", __FUNCTION__, Index)); > + continue; > + } > + > + BoardDesc[XhciIndex].SoC = &SoCDesc[Index]; > + XhciIndex++; > + } > + > + BoardDesc->XhciDevCount = XhciIndex; > + > + *XhciDesc = BoardDesc; > + > + return EFI_SUCCESS; > +} > + > +STATIC > +EFI_STATUS > MvBoardDescPp2Get ( > IN MARVELL_BOARD_DESC_PROTOCOL *This, > IN OUT MV_BOARD_PP2_DESC **Pp2Desc > @@ -202,8 +391,11 @@ MvBoardDescInitProtocol ( > IN MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol > ) > { > + BoardDescProtocol->BoardDescAhciGet = MvBoardDescAhciGet; > BoardDescProtocol->BoardDescPp2Get = MvBoardDescPp2Get; > + BoardDescProtocol->BoardDescSdMmcGet = MvBoardDescSdMmcGet; > BoardDescProtocol->BoardDescUtmiGet = MvBoardDescUtmiGet; > + BoardDescProtocol->BoardDescXhciGet = MvBoardDescXhciGet; > BoardDescProtocol->BoardDescFree = MvBoardDescFree; > > return EFI_SUCCESS; > -- > 2.7.4 >