From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AE31D210ED787 for ; Mon, 18 Jun 2018 09:15:17 -0700 (PDT) Received: by mail-wm0-x241.google.com with SMTP id x6-v6so15025476wmc.3 for ; Mon, 18 Jun 2018 09:15:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=WZMpG18kExu11APaNiNtTSfkOBqQzXzQBqvonw3Md7U=; b=f9V7sVycWq28yo/HdiTM15C3PQf0sB/abfV1OOGyAw0/lPjDerduzPT3zuIFdqcmcj 5qSBaUbhnZyIINJ4WuVGBlGTI9IcJ+sodRpp1eXTpswWbqSUQelnr91hkKXp3GUf5H+S bdORzEmHzbahbeV1mQhm46DWxfs35iRpMjvng= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=WZMpG18kExu11APaNiNtTSfkOBqQzXzQBqvonw3Md7U=; b=PRZ+fOimoup2ATeD3wlrj6YuoBeL1C4iImpL//K2JBfCuFOjPJwYAm7O5zAv4AsSCj 8PE4UePaeHsze7i0AIndcsIQoqYwZxge+4eEzlP8VUApDo7BetJh8AWo78su5ESi788m Ge/8x9+PPNHxDRRnABw6EtrHY24Az8LnPEy+UxDYZ8zieQAEBLmHDzHjXLLr2nxLDmbc 4kdyLC7sG2y5O8XrdYGY3vMQNRg7Q9gBDWPDcOeTiqwqLvlRF5nMgSCyW6LvBs4IN+QB rnrxJi7/bWwnTh5YIYg2YL9SzYs0BmjLvvw4LKxziNVAX9Q1WwR1S9Zjy8RgvPuddEym VjgA== X-Gm-Message-State: APt69E3Q9u0JnOenNTclIBYPMbWKWaBW7tPukNmBWgOP2/eGHSK8RA8Y iatSYPd4d6toNzh5pP60I0Igsw== X-Google-Smtp-Source: ADUXVKIgNAg8l4ULRS/nx4TqgCFccwOHeP1yb9mKN+qW1oJ72zN2FlO6Eq9C8rmgfItdZqO8nFzo9A== X-Received: by 2002:a1c:454f:: with SMTP id s76-v6mr8810605wma.16.1529338516073; Mon, 18 Jun 2018 09:15:16 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id r5-v6sm12445627wrp.59.2018.06.18.09.15.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Jun 2018 09:15:14 -0700 (PDT) Date: Mon, 18 Jun 2018 17:15:13 +0100 From: Leif Lindholm To: Marcin Wojtas Cc: edk2-devel@lists.01.org, ard.biesheuvel@linaro.org, nadavh@marvell.com, jinghua@marvell.com, jsd@semihalf.com, jaz@semihalf.com Message-ID: <20180618161513.gh43ndscpy3xtatk@bivouac.eciton.net> References: <1529266325-18371-1-git-send-email-mw@semihalf.com> <1529266325-18371-15-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: <1529266325-18371-15-git-send-email-mw@semihalf.com> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [platforms: PATCH v2 14/25] Marvell/Library: ComPhyLib: Get AHCI data with MARVELL_BOARD_DESC X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Jun 2018 16:15:18 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Sun, Jun 17, 2018 at 10:11:54PM +0200, Marcin Wojtas wrote: > ComPhy Library used to get Armada7k8k AHCI/SDMMC/XHCI controller > description from hardcoded values stored in the header file > MvHwDescLib.h. As a result it is very hard to support other > Armada SoC families with this library. > > This patch updates the driver to get AHCI controller > description from newly introduced MARVELL_BOARD_DESC protocol, > and removes the dependency on the hardcoded structures. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas Reviewed-by: Leif Lindholm > --- > Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 1 - > Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf | 6 +- > Silicon/Marvell/Include/Library/MvHwDescLib.h | 60 -------------------- > Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h | 4 ++ > Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 50 ++++++++-------- > 5 files changed, 35 insertions(+), 86 deletions(-) > > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf > index f2c173c..e888566 100644 > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf > @@ -47,7 +47,6 @@ > > [LibraryClasses] > ArmLib > - ComPhyLib > DebugLib > MemoryAllocationLib > MppLib > diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf > index ce0af54..f36c701 100644 > --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf > +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf > @@ -52,12 +52,16 @@ > PcdLib > SampleAtResetLib > IoLib > + UefiBootServicesTableLib > > [Sources.common] > ComPhyLib.c > ComPhyCp110.c > ComPhyMux.c > > +[Protocols] > + gMarvellBoardDescProtocolGuid ## CONSUMES > + > [FixedPcd] > gMarvellTokenSpaceGuid.PcdComPhyDevices > > @@ -80,5 +84,3 @@ > gMarvellTokenSpaceGuid.PcdChip3ComPhyTypes > gMarvellTokenSpaceGuid.PcdChip3ComPhySpeeds > gMarvellTokenSpaceGuid.PcdChip3ComPhyInvFlags > - > - gMarvellTokenSpaceGuid.PcdPciEAhci > diff --git a/Silicon/Marvell/Include/Library/MvHwDescLib.h b/Silicon/Marvell/Include/Library/MvHwDescLib.h > index 5fd514c..9f383f4 100644 > --- a/Silicon/Marvell/Include/Library/MvHwDescLib.h > +++ b/Silicon/Marvell/Include/Library/MvHwDescLib.h > @@ -36,7 +36,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > #define __MVHWDESCLIB_H__ > > #include > -#include > > // > // Helper macros > @@ -80,31 +79,6 @@ typedef struct { > } MVHW_MDIO_DESC; > > // > -// NonDiscoverable devices description template definition > -// > -#define MVHW_MAX_XHCI_DEVS 4 > -#define MVHW_MAX_AHCI_DEVS 4 > -#define MVHW_MAX_SDHCI_DEVS 4 > - > -typedef struct { > - // XHCI > - UINT8 XhciDevCount; > - UINTN XhciBaseAddresses[MVHW_MAX_XHCI_DEVS]; > - UINTN XhciMemSize[MVHW_MAX_XHCI_DEVS]; > - NON_DISCOVERABLE_DEVICE_DMA_TYPE XhciDmaType[MVHW_MAX_XHCI_DEVS]; > - // AHCI > - UINT8 AhciDevCount; > - UINTN AhciBaseAddresses[MVHW_MAX_AHCI_DEVS]; > - UINTN AhciMemSize[MVHW_MAX_AHCI_DEVS]; > - NON_DISCOVERABLE_DEVICE_DMA_TYPE AhciDmaType[MVHW_MAX_AHCI_DEVS]; > - // SDHCI > - UINT8 SdhciDevCount; > - UINTN SdhciBaseAddresses[MVHW_MAX_SDHCI_DEVS]; > - UINTN SdhciMemSize[MVHW_MAX_SDHCI_DEVS]; > - NON_DISCOVERABLE_DEVICE_DMA_TYPE SdhciDmaType[MVHW_MAX_SDHCI_DEVS]; > -} MVHW_NONDISCOVERABLE_DESC; > - > -// > // Platform description of CommonPhy devices > // > #define MVHW_CP0_COMPHY_BASE 0xF2441000 > @@ -155,38 +129,4 @@ MVHW_MDIO_DESC mA7k8kMdioDescTemplate = {\ > { MVHW_CP0_MDIO_BASE, MVHW_CP1_MDIO_BASE }\ > } > > -// > -// Platform description of NonDiscoverable devices > -// > -#define MVHW_CP0_XHCI0_BASE 0xF2500000 > -#define MVHW_CP0_XHCI1_BASE 0xF2510000 > -#define MVHW_CP1_XHCI0_BASE 0xF4500000 > -#define MVHW_CP1_XHCI1_BASE 0xF4510000 > - > -#define MVHW_CP0_AHCI0_BASE 0xF2540000 > -#define MVHW_CP0_AHCI0_ID 0 > -#define MVHW_CP1_AHCI0_BASE 0xF4540000 > -#define MVHW_CP1_AHCI0_ID 1 > - > -#define MVHW_AP0_SDHCI0_BASE 0xF06E0000 > -#define MVHW_CP0_SDHCI0_BASE 0xF2780000 > - > -#define DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE \ > -STATIC \ > -MVHW_NONDISCOVERABLE_DESC mA7k8kNonDiscoverableDescTemplate = {\ > - 4, /* XHCI */\ > - { MVHW_CP0_XHCI0_BASE, MVHW_CP0_XHCI1_BASE, MVHW_CP1_XHCI0_BASE, MVHW_CP1_XHCI1_BASE },\ > - { SIZE_16KB, SIZE_16KB, SIZE_16KB, SIZE_16KB },\ > - { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCoherent,\ > - NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCoherent },\ > - 2, /* AHCI */\ > - { MVHW_CP0_AHCI0_BASE, MVHW_CP1_AHCI0_BASE },\ > - { SIZE_8KB, SIZE_8KB },\ > - { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCoherent },\ > - 2, /* SDHCI */\ > - { MVHW_AP0_SDHCI0_BASE, MVHW_CP0_SDHCI0_BASE },\ > - { SIZE_1KB, SIZE_1KB },\ > - { NonDiscoverableDeviceDmaTypeCoherent, NonDiscoverableDeviceDmaTypeCoherent }\ > -} > - > #endif /* __MVHWDESCLIB_H__ */ > diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h > index c675d74..090116d 100644 > --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h > +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyLib.h > @@ -35,6 +35,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > #ifndef __COMPHY_H__ > #define __COMPHY_H__ > > +#include > #include > #include > #include > @@ -43,6 +44,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > #include > #include > #include > +#include > + > +#include > > #define MAX_LANE_OPTIONS 10 > > diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c > index 09994ca..5e0ebf6 100755 > --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c > +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c > @@ -33,7 +33,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > *******************************************************************************/ > > #include "ComPhyLib.h" > -#include > #include > > #define SD_LANE_ADDR_WIDTH 0x1000 > @@ -46,8 +45,6 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > #define CP110_PCIE_REF_CLK_TYPE0 0 > #define CP110_PCIE_REF_CLK_TYPE12 1 > > -DECLARE_A7K8K_NONDISCOVERABLE_TEMPLATE; > - > /* > * For CP-110 we have 2 Selector registers "PHY Selectors" > * and " PIPE Selectors". > @@ -1138,36 +1135,23 @@ ComPhySataCheckPll ( > STATIC > UINTN > ComPhySataPowerUp ( > + IN UINTN ChipId, > IN UINT32 Lane, > IN EFI_PHYSICAL_ADDRESS HpipeBase, > IN EFI_PHYSICAL_ADDRESS ComPhyBase, > - IN UINT8 SataHostId > + IN MV_BOARD_AHCI_DESC *Desc > ) > { > EFI_STATUS Status; > - UINT8 *SataDeviceTable; > - MVHW_NONDISCOVERABLE_DESC *Desc = &mA7k8kNonDiscoverableDescTemplate; > EFI_PHYSICAL_ADDRESS HpipeAddr = HPIPE_ADDR(HpipeBase, Lane); > EFI_PHYSICAL_ADDRESS SdIpAddr = SD_ADDR(HpipeBase, Lane); > EFI_PHYSICAL_ADDRESS ComPhyAddr = COMPHY_ADDR(ComPhyBase, Lane); > > - SataDeviceTable = (UINT8 *) PcdGetPtr (PcdPciEAhci); > - > - if (SataDeviceTable == NULL || SataHostId >= PcdGetSize (PcdPciEAhci)) { > - DEBUG ((DEBUG_ERROR, "ComPhySata: Sata host %d is undefined\n", SataHostId)); > - return EFI_INVALID_PARAMETER; > - } > - > - if (!MVHW_DEV_ENABLED (Sata, SataHostId)) { > - DEBUG ((DEBUG_ERROR, "ComPhySata: Sata host %d is disabled\n", SataHostId)); > - return EFI_INVALID_PARAMETER; > - } > - > DEBUG ((DEBUG_INFO, "ComPhySata: Initialize SATA PHYs\n")); > > DEBUG((DEBUG_INFO, "ComPhySataPowerUp: stage: MAC configuration - power down ComPhy\n")); > > - ComPhySataMacPowerDown (Desc->AhciBaseAddresses[SataHostId]); > + ComPhySataMacPowerDown (Desc[ChipId].SoC->AhciBaseAddress); > > DEBUG((DEBUG_INFO, "ComPhy: stage: RFU configurations - hard reset ComPhy\n")); > > @@ -1183,7 +1167,7 @@ ComPhySataPowerUp ( > > DEBUG((DEBUG_INFO, "ComPhy: stage: ComPhy power up\n")); > > - ComPhySataPhyPowerUp (Desc->AhciBaseAddresses[SataHostId]); > + ComPhySataPhyPowerUp (Desc[ChipId].SoC->AhciBaseAddress); > > DEBUG((DEBUG_INFO, "ComPhy: stage: Check PLL\n")); > > @@ -1884,6 +1868,8 @@ ComPhyCp110Init ( > EFI_STATUS Status; > COMPHY_MAP *PtrComPhyMap, *SerdesMap; > EFI_PHYSICAL_ADDRESS ComPhyBaseAddr, HpipeBaseAddr; > + MARVELL_BOARD_DESC_PROTOCOL *BoardDescProtocol; > + MV_BOARD_AHCI_DESC *AhciBoardDesc; > UINT32 ComPhyMaxCount, Lane; > UINT32 PcieWidth = 0; > UINT8 ChipId; > @@ -1927,11 +1913,29 @@ ComPhyCp110Init ( > break; > case COMPHY_TYPE_SATA0: > case COMPHY_TYPE_SATA1: > - Status = ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, MVHW_CP0_AHCI0_ID); > - break; > case COMPHY_TYPE_SATA2: > case COMPHY_TYPE_SATA3: > - Status = ComPhySataPowerUp (Lane, HpipeBaseAddr, ComPhyBaseAddr, MVHW_CP1_AHCI0_ID); > + /* Obtain AHCI board description */ > + Status = gBS->LocateProtocol (&gMarvellBoardDescProtocolGuid, > + NULL, > + (VOID **)&BoardDescProtocol); > + if (EFI_ERROR (Status)) { > + break; > + } > + > + Status = BoardDescProtocol->BoardDescAhciGet (BoardDescProtocol, > + &AhciBoardDesc); > + if (EFI_ERROR (Status)) { > + break; > + } > + > + Status = ComPhySataPowerUp (ChipId, > + Lane, > + HpipeBaseAddr, > + ComPhyBaseAddr, > + AhciBoardDesc); > + > + BoardDescProtocol->BoardDescFree (AhciBoardDesc); > break; > case COMPHY_TYPE_USB3_HOST0: > case COMPHY_TYPE_USB3_HOST1: > -- > 2.7.4 >