From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3082A211C8302 for ; Thu, 21 Jun 2018 01:13:23 -0700 (PDT) Received: by mail-wr0-x242.google.com with SMTP id k16-v6so2163616wro.0 for ; Thu, 21 Jun 2018 01:13:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xQ8MhwOxfAim2qnrZ0l4y2It3bLdPmUEOfX6l3rj+lk=; b=A2EMMckZgJnDBSSpi1sT0tN8k+Tt5sPpUqv3RPRwqbL+E3rnGfvoqb4+yEE3pWjewa a1EHkv9eP+5xa4usrwwxWP0v0oxVAL3TtEOUxDUNv2BFWm4sr9JsK7qloW3Ssy39oORI O+P5JKSTXUKvuz38oBfixI6JtjJ/M8q2lDLXY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xQ8MhwOxfAim2qnrZ0l4y2It3bLdPmUEOfX6l3rj+lk=; b=NoW+IHpGX+pNictyDf6vASKCnboTu3xFVwUfs/dm5I+cyeL/5WJMdok+EHgCGSVgVl v1GPBfE/6tI91GNroF7I4GIpa8Eka7cxlHlJPBEhZwqqvTeluZrwqFpcvHGJW1+y3aLH jHCM3aO8OflCUyYaGeJ7KrecVvcEqj1WyCVle6zQaeQHLTG6rtFS2SLkHcrhDPpObRzt BuNit2X7cXr4T3uhiQRUGzCDtkLeRMBzWhyBciqX+Y4WgaVCSuuiX3pHMSZu/412+DVC 4erICECIlF8ab3cDuP+PTbvUwdo3g88yXU2DD1DBUBzDP9anCXCyJnigrdvUnxuOx5lU cPuw== X-Gm-Message-State: APt69E0Bnh4qhmbnpQx+y7oHM8naRhbQWDwf/ycODPLRan7ZDJ2/USAA ZM4yIQaoClCBodAQiWvncRCF63rTNpA= X-Google-Smtp-Source: ADUXVKJ36TRIbhMmaNBxWW3/aw4jKcjbdkQONUn8OEM1Ln7UYe+LhnmfCvrNax4pg6m630rjmFIcyA== X-Received: by 2002:adf:bd89:: with SMTP id l9-v6mr20970050wrh.266.1529568801489; Thu, 21 Jun 2018 01:13:21 -0700 (PDT) Received: from dogfood.home ([2a01:cb1d:112:6f00:104b:ef1a:8c01:a5bb]) by smtp.gmail.com with ESMTPSA id q17-v6sm4803152wro.30.2018.06.21.01.13.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 21 Jun 2018 01:13:20 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, Christopher.Co@microsoft.com, Ard Biesheuvel Date: Thu, 21 Jun 2018 10:13:15 +0200 Message-Id: <20180621081315.16228-3-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180621081315.16228-1-ard.biesheuvel@linaro.org> References: <20180621081315.16228-1-ard.biesheuvel@linaro.org> Subject: [PATCH v2 2/2] ArmPkg/ArmMmuLib ARM: assume page tables are in writeback cacheable memory X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jun 2018 08:13:23 -0000 Given that these days, our ARM port only supports ARMv7 and later, we can assume that the page table walker's memory accesses are cache coherent, and so there is no need to perform cache maintenance. It does require the page tables themselves to reside in memory mapped as writeback cacheable so ASSERT() that this is the case. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 2 -- ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 14 +++----------- 2 files changed, 3 insertions(+), 13 deletions(-) diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S index 149b57e059ee..f2a517671f0a 100644 --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S @@ -100,8 +100,6 @@ ASM_FUNC(ArmGetTTBR0BaseAddress) // IN VOID *MVA // R1 // ); ASM_FUNC(ArmUpdateTranslationTableEntry) - mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA - dsb mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp dsb diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c index 9c2578979e44..3037b642d40c 100644 --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c @@ -343,17 +343,12 @@ ArmConfigureMmu ( } // Translate the Memory Attributes into Translation Table Register Attributes - if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) || - (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) { - TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_NON_CACHEABLE : TTBR_NON_CACHEABLE; - } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || + if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) { TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC; - } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) || - (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) { - TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_THROUGH : TTBR_WRITE_THROUGH; } else { - ASSERT (0); // No support has been found for the attributes of the memory region that the translation table belongs to. + // Page tables must reside in memory mapped as writeback cacheable + ASSERT (0); return RETURN_UNSUPPORTED; } @@ -461,9 +456,6 @@ ConvertSectionToPages ( PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor; } - // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks - WriteBackInvalidateDataCacheRange ((VOID *)PageTable, TT_DESCRIPTOR_PAGE_SIZE); - // Formulate page table entry, Domain=0, NS=0 PageTableDescriptor = (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE; -- 2.17.1