From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 4EEB2210CBAFE for ; Thu, 21 Jun 2018 07:01:43 -0700 (PDT) Received: by mail-wr0-x242.google.com with SMTP id k6-v6so3335348wrp.4 for ; Thu, 21 Jun 2018 07:01:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=IZ3MlmzQcBLMxMZ6cAGtKKypc2rFQfr6PzXodvvn9QM=; b=VRT9EVB1XQ4Vo+Aw6EQIOgUsw5nxERFhsI+oRGszkHmKu7MkGDydgCNLWa7pGkKPfc TgYVQNKB1pF5FjpgMN5mLgIzW0Su230U4KtnBBIBBryIGZkoMxWOF7ukNBzKgkHy3Mo1 SvyuOkaNpyXleIBpjsZIFQ91qUm5Wkfw09ZZU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=IZ3MlmzQcBLMxMZ6cAGtKKypc2rFQfr6PzXodvvn9QM=; b=rfdTfK3xiRcLhOnPZOVxzRysx8UR1h2USg31gR3oRX+99FAhaiW+Tb5ldPu4U6iBX1 lKBameGPQAq9RTuGpDXFs7M1mZdLuvJDep/ZE4Z1BoS1K1icfiZzbTJdMuxSqUygI9RP 2gI8JmQJFaIJjB+odnocffXLs9gFG7En11uXdrkqktLGvmTeY2goMlM5gHuipmExM+Mn M2pm9/QTtdzcfsgnYf9EfzoJuEGddp1OL4KgLsqS9m4/ee5mClueVBftySDoiBw6y9dc eZ7q9MquFXaaSJF+gwWb2grZGDIyLaqIHqHwM06/8iJRmwXZVOag5XIRt6vL6duL5z0O o+Qw== X-Gm-Message-State: APt69E2beR7JBUF9tqXeVNgymkCk4Zvm0CclsySs/Aba6bFzrI+Ydwqk /Nz0f9ClBGtoljw6PSc2gDWhEddMAM4= X-Google-Smtp-Source: ADUXVKJx44MGkpyqvidcEVZpPl5dOTpiO8gXaxlDcdPTffD3die9tb0c6sRlaqStYXhXtkg1QZ5lMQ== X-Received: by 2002:a5d:464e:: with SMTP id j14-v6mr17622955wrs.52.1529589701703; Thu, 21 Jun 2018 07:01:41 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id m10-v6sm1315119wrn.93.2018.06.21.07.01.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 21 Jun 2018 07:01:40 -0700 (PDT) Date: Thu, 21 Jun 2018 15:01:38 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, Christopher.Co@microsoft.com Message-ID: <20180621140138.pvco42ieamb2cl5x@bivouac.eciton.net> References: <20180621081315.16228-1-ard.biesheuvel@linaro.org> <20180621081315.16228-3-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180621081315.16228-3-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH v2 2/2] ArmPkg/ArmMmuLib ARM: assume page tables are in writeback cacheable memory X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jun 2018 14:01:43 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Jun 21, 2018 at 10:13:15AM +0200, Ard Biesheuvel wrote: > Given that these days, our ARM port only supports ARMv7 and later, we > can assume that the page table walker's memory accesses are cache > coherent, and so there is no need to perform cache maintenance. It > does require the page tables themselves to reside in memory mapped as > writeback cacheable so ASSERT() that this is the case. One minor nit. > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S | 2 -- > ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c | 14 +++----------- > 2 files changed, 3 insertions(+), 13 deletions(-) > > diff --git a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > index 149b57e059ee..f2a517671f0a 100644 > --- a/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > +++ b/ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S > @@ -100,8 +100,6 @@ ASM_FUNC(ArmGetTTBR0BaseAddress) > // IN VOID *MVA // R1 > // ); > ASM_FUNC(ArmUpdateTranslationTableEntry) > - mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA > - dsb > mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA > mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp > dsb > diff --git a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c > index 9c2578979e44..3037b642d40c 100644 > --- a/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c > +++ b/ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c > @@ -343,17 +343,12 @@ ArmConfigureMmu ( > } > > // Translate the Memory Attributes into Translation Table Register Attributes > - if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) || > - (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) { > - TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_NON_CACHEABLE : TTBR_NON_CACHEABLE; > - } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || > + if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) || > (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) { > TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC; > - } else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) || > - (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) { > - TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_THROUGH : TTBR_WRITE_THROUGH; > } else { > - ASSERT (0); // No support has been found for the attributes of the memory region that the translation table belongs to. > + // Page tables must reside in memory mapped as writeback cacheable ARM ARM always uses "write-back" - could you add the hyphen to assist greppability? If so, for the series: Reviewed-by: Leif Lindholm > + ASSERT (0); > return RETURN_UNSUPPORTED; > } > > @@ -461,9 +456,6 @@ ConvertSectionToPages ( > PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor; > } > > - // Flush d-cache so descriptors make it back to uncached memory for subsequent table walks > - WriteBackInvalidateDataCacheRange ((VOID *)PageTable, TT_DESCRIPTOR_PAGE_SIZE); > - > // Formulate page table entry, Domain=0, NS=0 > PageTableDescriptor = (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE; > > -- > 2.17.1 >