From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id DC7CB20337359 for ; Tue, 26 Jun 2018 03:44:30 -0700 (PDT) Received: by mail-wm0-x242.google.com with SMTP id p126-v6so1345372wmb.2 for ; Tue, 26 Jun 2018 03:44:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ncn1osWfMrS7upp6S4ylRtmpn8KuTXIK//8lCKzczSk=; b=k1prieOzs/VHAFNyNt9Em9S74fJddmFEGNu9e0ML8K3a9T+KlbfK48i0nPPNweMHKy uKX/QGaYAxGIEwT3Jhxt82Y9cuUa99t8VlrrWE1W2OEZPk9JnHy9sv+lOXAoJlwLHupx m8NEXVCoOk2edP7fPxtP3qWvbrbIBqZZSzakQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ncn1osWfMrS7upp6S4ylRtmpn8KuTXIK//8lCKzczSk=; b=q4j9ofN0SKQTK9HQXRrDMlnyNwCLhFFWPsT59ixAxSWArw5IgEyfrK9EXFJNx93MwU SL8rIiUta0LOwZg+PVYgpMkXxJOSjoWBsPyh5XIVqMygSI0IqEi1uJqL4Jj41aSa/+L8 LU4PArNIGBRPrxIxJOiuFqQ14naFVOzpO9HTOfiTzoqEneB32Pz5auQx2zWECxgR2Hvs C08aI124JzWjYalk8kSGEWWPYsvsEvM7lR9kHEGEZUdnuCtjDdqnFqL6S1gcyMB40+0N w0Yf095ThemPTKCyrZoGBm0/TrscwtqteXYZ78p8o5T3PB3hkXDFFivRGbOTsAHkaL0/ gRCg== X-Gm-Message-State: APt69E0IRd4MRUxu/egdhue8V8f+64TYJ769eUS8aGuO+jAodLaMg/8q kYTtJDf0OZbNwexpJNUaznzZoiWhqrw= X-Google-Smtp-Source: AAOMgpcT2lAsxeiFv3lIrvrF1+ippwTygOwLjOzNJrScq0J6NWrrmdaUqhp0vUeMpGOGEwZzCCVMkQ== X-Received: by 2002:a1c:5b0d:: with SMTP id p13-v6mr1174942wmb.53.1530009868774; Tue, 26 Jun 2018 03:44:28 -0700 (PDT) Received: from dogfood.home ([2a01:cb1d:112:6f00:a044:5ea2:f748:d67a]) by smtp.gmail.com with ESMTPSA id m58-v6sm2557745wrf.61.2018.06.26.03.44.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 26 Jun 2018 03:44:27 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org Cc: leif.lindholm@linaro.org, Ard Biesheuvel Date: Tue, 26 Jun 2018 12:44:23 +0200 Message-Id: <20180626104424.3524-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180626104424.3524-1-ard.biesheuvel@linaro.org> References: <20180626104424.3524-1-ard.biesheuvel@linaro.org> Subject: [PATCH edk2-platforms 1/2] Silicon/SynQuacer: add preliminary support for PCIe MMIO32 translation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jun 2018 10:44:31 -0000 Add the basic support for enabling PCIe MMIO32 translation on the SynQuacer, without actually enabling it just yet. It would allow us to increase the bus range to 255 MB [from 127 MB] and the MMIO32 range to 512 MB or more [from 128 MB], but it is more likely to cause compatibility issues with code ported from the PC platform. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl | 8 ++++---- Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 2 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 6 ++++-- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 2 +- 4 files changed, 11 insertions(+), 7 deletions(-) diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl index 51e9d0b22c3d..77d4763d1a85 100644 --- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl @@ -86,14 +86,14 @@ DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR", SYNQUACER_PCI_SEG0_BUSNUM_RANGE // RangeLength - # of Busses ) - DWordMemory ( // 32-bit BAR Windows + QWordMemory ( // 32-bit BAR Windows ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity SYNQUACER_PCI_SEG0_MMIO32_MIN, // Min Base Address SYNQUACER_PCI_SEG0_MMIO32_MAX, // Max Base Address - 0x00000000, // Translate + SYNQUACER_PCI_SEG0_MMIO32_XLATE, // Translate SYNQUACER_PCI_SEG0_MMIO32_SIZE // Length ) @@ -224,14 +224,14 @@ DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR", SYNQUACER_PCI_SEG1_BUSNUM_RANGE // RangeLength - # of Busses ) - DWordMemory ( // 32-bit BAR Windows + QWordMemory ( // 32-bit BAR Windows ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, 0x00000000, // Granularity SYNQUACER_PCI_SEG1_MMIO32_MIN, // Min Base Address SYNQUACER_PCI_SEG1_MMIO32_MAX, // Max Base Address - 0x00000000, // Translate + SYNQUACER_PCI_SEG1_MMIO32_XLATE, // Translate SYNQUACER_PCI_SEG1_MMIO32_SIZE // Length ) diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h index 950cece13e81..798f59db2a94 100644 --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h @@ -34,6 +34,7 @@ #define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x68000000 #define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fffffff #define SYNQUACER_PCI_SEG0_MMIO32_SIZE 0x08000000 +#define SYNQUACER_PCI_SEG0_MMIO32_XLATE 0x0 #define SYNQUACER_PCI_SEG0_MMIO64_MIN 0x3e00000000 #define SYNQUACER_PCI_SEG0_MMIO64_MAX 0x3effffffff @@ -57,6 +58,7 @@ #define SYNQUACER_PCI_SEG1_MMIO32_MIN 0x78000000 #define SYNQUACER_PCI_SEG1_MMIO32_MAX 0x7fffffff #define SYNQUACER_PCI_SEG1_MMIO32_SIZE 0x08000000 +#define SYNQUACER_PCI_SEG1_MMIO32_XLATE 0x0 #define SYNQUACER_PCI_SEG1_MMIO64_MIN 0x3f00000000 #define SYNQUACER_PCI_SEG1_MMIO64_MAX 0x3fffffffff diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c index 341939876bd3..7c096f0801dd 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c @@ -107,7 +107,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = { SYNQUACER_PCI_SEG0_PORTIO_MAX, MAX_UINT64 - SYNQUACER_PCI_SEG0_PORTIO_OFFSET + 1 }, // Io { SYNQUACER_PCI_SEG0_MMIO32_MIN, - SYNQUACER_PCI_SEG0_MMIO32_MAX }, // Mem + SYNQUACER_PCI_SEG0_MMIO32_MAX, + MAX_UINT64 - SYNQUACER_PCI_SEG0_MMIO32_XLATE + 1 }, // Mem { SYNQUACER_PCI_SEG0_MMIO64_MIN, SYNQUACER_PCI_SEG0_MMIO64_MAX }, // MemAbove4G { MAX_UINT64, 0x0 }, // PMem @@ -127,7 +128,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = { SYNQUACER_PCI_SEG1_PORTIO_MAX, MAX_UINT64 - SYNQUACER_PCI_SEG1_PORTIO_OFFSET + 1 }, // Io { SYNQUACER_PCI_SEG1_MMIO32_MIN, - SYNQUACER_PCI_SEG1_MMIO32_MAX }, // Mem + SYNQUACER_PCI_SEG1_MMIO32_MAX, + MAX_UINT64 - SYNQUACER_PCI_SEG1_MMIO32_XLATE + 1 }, // Mem { SYNQUACER_PCI_SEG1_MMIO64_MIN, SYNQUACER_PCI_SEG1_MMIO64_MAX }, // MemAbove4G { MAX_UINT64, 0x0 }, // PMem diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index 227f9a725ce8..75a663e974e1 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -322,7 +322,7 @@ PciInitControllerPost ( // Region 0: MMIO32 range ConfigureWindow (DbiBase, 0, - RootBridge->Mem.Base, + RootBridge->Mem.Base - RootBridge->Mem.Translation, RootBridge->Mem.Base, RootBridge->Mem.Limit - RootBridge->Mem.Base + 1, IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | -- 2.17.1