From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C15B92096FAA0 for ; Tue, 26 Jun 2018 07:24:13 -0700 (PDT) Received: by mail-wm0-x244.google.com with SMTP id i139-v6so2171710wmf.4 for ; Tue, 26 Jun 2018 07:24:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=OtsZD68S61+K4Fts9M0NyaJ1QVsWB3mYsFPqdZBPWzs=; b=atYHuU/ILEnVUsEmhJRbHbS63UTMtv4BEjBNFVPhn/ErjE00Bz3QIYnrSKOJ8VTJYP llvaum/STk0J9v7XzhV5Rozf91Su99rRfjRsR7Qwb8M4LiNX/x+eCxEAGWsfhWtb9E9L ZyAw5Xj8xhbD5zXLBHsusC+rAmTkWZ2xsqk/4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=OtsZD68S61+K4Fts9M0NyaJ1QVsWB3mYsFPqdZBPWzs=; b=jG/SY3FTc1A/WlVnEtR2iB9p5EfN33V1yQossJFbBxHet7lYGH9rmm4G9F65c+r/9+ IVuxKDOUSGosFt4b/csofMKXT0xIblqBjXb68C7h/c/UDy7rwIRiAGSonnVTLRqfGwtu 4MEVxgjkQnFK4PJf/185IPh5svVLL1IrRYnS139Gsbd0MGG8DVpPLa7qlRnOq1nQRJDw rvr3UDnyXPOp8GhJD78GASZuXL9Reru/Q4nRoGYkpQ2IoldvtOcbckjSmjZQdVbnaXaP rhR/V2tVn3YsKTCKcU8K4uMRLOGXvFXzgLo+nxZV16+PHyTOvAxx/IrBQUuMfgZy7vuT xyMQ== X-Gm-Message-State: APt69E1q67k5dOIbKNGc7+Qdls/qQebzNW8dWfWuLhowiJ1udKM3LUKm q/swofPRqEvHu2zfIiDA7H3QbmJPQXk= X-Google-Smtp-Source: AAOMgpf11FiAeu56oYxS74d8YVdNsvUS/BbWeZ7UZ7qVYr2pVzLvj8Rh04bxwD/EXKlsBZ0ymOrLvw== X-Received: by 2002:a1c:5e90:: with SMTP id s138-v6mr1903912wmb.96.1530023052062; Tue, 26 Jun 2018 07:24:12 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id i6-v6sm2484951wrr.2.2018.06.26.07.24.10 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Jun 2018 07:24:10 -0700 (PDT) Date: Tue, 26 Jun 2018 15:24:09 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: edk2-devel@lists.01.org Message-ID: <20180626142409.gwn6daatv3vbnqxe@bivouac.eciton.net> References: <20180626104424.3524-1-ard.biesheuvel@linaro.org> <20180626104424.3524-2-ard.biesheuvel@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180626104424.3524-2-ard.biesheuvel@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms 1/2] Silicon/SynQuacer: add preliminary support for PCIe MMIO32 translation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Jun 2018 14:24:14 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Jun 26, 2018 at 12:44:23PM +0200, Ard Biesheuvel wrote: > Add the basic support for enabling PCIe MMIO32 translation on the > SynQuacer, without actually enabling it just yet. It would allow us > to increase the bus range to 255 MB [from 127 MB] and the MMIO32 > range to 512 MB or more [from 128 MB], but it is more likely to > cause compatibility issues with code ported from the PC platform. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ard Biesheuvel > --- > Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl | 8 ++++---- > Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h | 2 ++ > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 6 ++++-- > Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 2 +- > 4 files changed, 11 insertions(+), 7 deletions(-) > > diff --git a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl > index 51e9d0b22c3d..77d4763d1a85 100644 > --- a/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl > +++ b/Silicon/Socionext/SynQuacer/AcpiTables/AcpiSsdtRootPci.asl > @@ -86,14 +86,14 @@ DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR", > SYNQUACER_PCI_SEG0_BUSNUM_RANGE // RangeLength - # of Busses > ) > > - DWordMemory ( // 32-bit BAR Windows > + QWordMemory ( // 32-bit BAR Windows > ResourceProducer, PosDecode, > MinFixed, MaxFixed, > Cacheable, ReadWrite, > 0x00000000, // Granularity > SYNQUACER_PCI_SEG0_MMIO32_MIN, // Min Base Address > SYNQUACER_PCI_SEG0_MMIO32_MAX, // Max Base Address > - 0x00000000, // Translate > + SYNQUACER_PCI_SEG0_MMIO32_XLATE, // Translate > SYNQUACER_PCI_SEG0_MMIO32_SIZE // Length > ) > > @@ -224,14 +224,14 @@ DefinitionBlock ("SsdtPci.aml", "SSDT", 1, "SNI", "SYNQUACR", > SYNQUACER_PCI_SEG1_BUSNUM_RANGE // RangeLength - # of Busses > ) > > - DWordMemory ( // 32-bit BAR Windows > + QWordMemory ( // 32-bit BAR Windows > ResourceProducer, PosDecode, > MinFixed, MaxFixed, > Cacheable, ReadWrite, > 0x00000000, // Granularity > SYNQUACER_PCI_SEG1_MMIO32_MIN, // Min Base Address > SYNQUACER_PCI_SEG1_MMIO32_MAX, // Max Base Address > - 0x00000000, // Translate > + SYNQUACER_PCI_SEG1_MMIO32_XLATE, // Translate > SYNQUACER_PCI_SEG1_MMIO32_SIZE // Length > ) > > diff --git a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > index 950cece13e81..798f59db2a94 100644 > --- a/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > +++ b/Silicon/Socionext/SynQuacer/Include/Platform/Pcie.h > @@ -34,6 +34,7 @@ > #define SYNQUACER_PCI_SEG0_MMIO32_MIN 0x68000000 > #define SYNQUACER_PCI_SEG0_MMIO32_MAX 0x6fffffff > #define SYNQUACER_PCI_SEG0_MMIO32_SIZE 0x08000000 > +#define SYNQUACER_PCI_SEG0_MMIO32_XLATE 0x0 > > #define SYNQUACER_PCI_SEG0_MMIO64_MIN 0x3e00000000 > #define SYNQUACER_PCI_SEG0_MMIO64_MAX 0x3effffffff > @@ -57,6 +58,7 @@ > #define SYNQUACER_PCI_SEG1_MMIO32_MIN 0x78000000 > #define SYNQUACER_PCI_SEG1_MMIO32_MAX 0x7fffffff > #define SYNQUACER_PCI_SEG1_MMIO32_SIZE 0x08000000 > +#define SYNQUACER_PCI_SEG1_MMIO32_XLATE 0x0 > > #define SYNQUACER_PCI_SEG1_MMIO64_MIN 0x3f00000000 > #define SYNQUACER_PCI_SEG1_MMIO64_MAX 0x3fffffffff > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c > index 341939876bd3..7c096f0801dd 100644 > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c > @@ -107,7 +107,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = { > SYNQUACER_PCI_SEG0_PORTIO_MAX, > MAX_UINT64 - SYNQUACER_PCI_SEG0_PORTIO_OFFSET + 1 }, // Io > { SYNQUACER_PCI_SEG0_MMIO32_MIN, > - SYNQUACER_PCI_SEG0_MMIO32_MAX }, // Mem > + SYNQUACER_PCI_SEG0_MMIO32_MAX, > + MAX_UINT64 - SYNQUACER_PCI_SEG0_MMIO32_XLATE + 1 }, // Mem So, this had me scratching my head for a second. I may get pickier about requring explicitly initializing the Translation field in future, but for this patch: Reviewed-by: Leif Lindholm > { SYNQUACER_PCI_SEG0_MMIO64_MIN, > SYNQUACER_PCI_SEG0_MMIO64_MAX }, // MemAbove4G > { MAX_UINT64, 0x0 }, // PMem > @@ -127,7 +128,8 @@ PCI_ROOT_BRIDGE mPciRootBridges[] = { > SYNQUACER_PCI_SEG1_PORTIO_MAX, > MAX_UINT64 - SYNQUACER_PCI_SEG1_PORTIO_OFFSET + 1 }, // Io > { SYNQUACER_PCI_SEG1_MMIO32_MIN, > - SYNQUACER_PCI_SEG1_MMIO32_MAX }, // Mem > + SYNQUACER_PCI_SEG1_MMIO32_MAX, > + MAX_UINT64 - SYNQUACER_PCI_SEG1_MMIO32_XLATE + 1 }, // Mem > { SYNQUACER_PCI_SEG1_MMIO64_MIN, > SYNQUACER_PCI_SEG1_MMIO64_MAX }, // MemAbove4G > { MAX_UINT64, 0x0 }, // PMem > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > index 227f9a725ce8..75a663e974e1 100644 > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c > @@ -322,7 +322,7 @@ PciInitControllerPost ( > > // Region 0: MMIO32 range > ConfigureWindow (DbiBase, 0, > - RootBridge->Mem.Base, > + RootBridge->Mem.Base - RootBridge->Mem.Translation, > RootBridge->Mem.Base, > RootBridge->Mem.Limit - RootBridge->Mem.Base + 1, > IATU_REGION_CTRL_1_OFF_OUTBOUND_0_TYPE_MEM | > -- > 2.17.1 >