public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed
From: Ming Huang <ming.huang@linaro.org>
To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org,
	edk2-devel@lists.01.org, graeme.gregory@linaro.org
Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com,
	wanghuiqiang@huawei.com, huangming23@huawei.com,
	zhangjinsong2@huawei.com, huangdaode@hisilicon.com,
	john.garry@huawei.com, Heyi Guo <heyi.guo@linaro.org>,
	Ming Huang <ming.huang@linaro.org>
Subject: [PATCH edk2-platforms v1 2/6] Hisilicon/D03/D05: Correct ATU Cfg0/Cfg1 base address
Date: Wed, 27 Jun 2018 15:04:39 +0800	[thread overview]
Message-ID: <20180627070443.42886-3-ming.huang@linaro.org> (raw)
In-Reply-To: <20180627070443.42886-1-ming.huang@linaro.org>

From: Jason Zhang <zhangjinsong2@huawei.com>

1. During test PCIe mcs9922 UART card, the card can't
   work because the IO ATU config is overlap by Cfg0/Cfg1
   ATU address.
2. After adjust the ATU windows, Cfg0/Cfg1 config as below:
     Cfg0 is equal to "ECAM + (BusBase, 0, 0)"
     Cfg1 is equal to "ECAM + (BusBase + 2, 0, 0)"

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Ming Huang <ming.huang@linaro.org>
---
 Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
index 55b80aa4e4..e5f66eaa4a 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -640,11 +640,12 @@ void SetAtuConfig0RW (
 {
     UINTN RbPciBase = Private->RbPciBar;
     UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1;
+    UINT64 Cfg0Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0, 0, 0);
 
 
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
-    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
-    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg0Base));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg0Base >> 32));
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
@@ -666,12 +667,12 @@ void SetAtuConfig1RW (
 {
     UINTN RbPciBase = Private->RbPciBar;
     UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1;
-
+    UINT64 Cfg1Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0);
 
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1);
-    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
-    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg1Base));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg1Base >> 32));
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
-- 
2.17.0



  parent reply	other threads:[~2018-06-27  7:04 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-27  7:04 [PATCH edk2-platforms v1 0/6] Improve D0x platforms and bug fix Ming Huang
2018-06-27  7:04 ` [PATCH edk2-platforms v1 1/6] Hisilicon/D0x: Fix invoke SetMemorySpaceAttributes error bug Ming Huang
2018-06-27  7:20   ` Ard Biesheuvel
2018-07-03  9:53     ` Ming
2018-07-04  6:46     ` Ming
2018-06-27  7:04 ` Ming Huang [this message]
2018-06-27  7:26   ` [PATCH edk2-platforms v1 2/6] Hisilicon/D03/D05: Correct ATU Cfg0/Cfg1 base address Ard Biesheuvel
2018-06-27  7:04 ` [PATCH edk2-platforms v1 3/6] Hisilicon/D0x: Fix SetAtuConfig1RW bug Ming Huang
2018-06-27  7:04 ` [PATCH edk2-platforms v1 4/6] Hisilicon/D05: Add PlatformMiscDxe driver Ming Huang
2018-06-27  7:33   ` Ard Biesheuvel
     [not found]     ` <d4c99a0d-c906-807d-13d2-78adbba4a042@linaro.org>
2018-06-28 10:54       ` Ard Biesheuvel
2018-06-29  7:26         ` Ming
2018-06-27  7:04 ` [PATCH edk2-platforms v1 5/6] Hisilicon/D05/Pcie: optimize two pcie ports space Ming Huang
2018-06-27  7:35   ` Ard Biesheuvel
2018-06-27  7:04 ` [PATCH edk2-platforms v1 6/6] Hisilicon/D0x: Correct smbios product name Ming Huang

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-list from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20180627070443.42886-3-ming.huang@linaro.org \
    --to=devel@edk2.groups.io \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox