From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::242; helo=mail-pl0-x242.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x242.google.com (mail-pl0-x242.google.com [IPv6:2607:f8b0:400e:c01::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A26EA202E540B for ; Wed, 27 Jun 2018 00:05:02 -0700 (PDT) Received: by mail-pl0-x242.google.com with SMTP id a7-v6so614761plp.3 for ; Wed, 27 Jun 2018 00:05:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=xRe/urAWwysMHHsxtHieSYgrQAtjQI696BfNH4z434g=; b=Psb44A9Aotb4St5BHa/Nz2hsjJ32pk4mi3y8gmRClVH9rxuCPXOXy33eV1rG5rcqav TXfA8HPASkFRj4hTTylLZ2gwkbea/3DKHCIRJ8kYqPPTrjg+u+uRsmO9Oh4B3xn9NmjM OK5fCTfCqIS4584swP4F7yprjvnAm+RvywKQ0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=xRe/urAWwysMHHsxtHieSYgrQAtjQI696BfNH4z434g=; b=uW6VBv7RsUWIm871WMEipJReyO6JhLYYE62rGKsMnYz4PRn2O/eRmZTw+kpPTPIKgF WEzMypvuHn3US4HkHjIGvb7HxJQBo/PbZni9ua8NT0nj5hcp9uylRX6lDMQqc6pZ/kq8 hpxXsGBeP7jVZ9HAPvMoY2pgGfvco17Y7gFEBBhXb6KO2fBClfHDBuqSAijOz6uONBNo 0DIhMdNnyQZr+xgU0MOt2cIJ1C6CYczJleIwdJLvShSCdHcEpWeWiGczjdbXsxv8E4/+ 4GJ+ukjDSG9AwW+FA1FjVw3zO8uRlOO6yRtBnqOZK+heSK+tSKSDDsWdPWzzDwL/CQch gTRQ== X-Gm-Message-State: APt69E3oN1aH9NiATbIgClrQZYVeSvSAS7vZRcBnj/9GrdIAuIhBYniQ lU3ULqjAhxIhHo1EPfBWe5bSmtmi7Nw= X-Google-Smtp-Source: ADUXVKJ4WXCqjr6KQTj0rIdgNpL+J7EU2mGv1FsY8LJjPar2e6Cpj+ElzgeR7Zvq5wVzIKHMI1f6hA== X-Received: by 2002:a17:902:c85:: with SMTP id 5-v6mr4937935plt.126.1530083102296; Wed, 27 Jun 2018 00:05:02 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id q6-v6sm4128833pgc.21.2018.06.27.00.04.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Jun 2018 00:05:01 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, Ming Huang , Heyi Guo Date: Wed, 27 Jun 2018 15:04:41 +0800 Message-Id: <20180627070443.42886-5-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180627070443.42886-1-ming.huang@linaro.org> References: <20180627070443.42886-1-ming.huang@linaro.org> Subject: [PATCH edk2-platforms v1 4/6] Hisilicon/D05: Add PlatformMiscDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 27 Jun 2018 07:05:02 -0000 Fix the issue of onboard Nic not work kerenl with AMD GPU and NVME SSD in board. The GPU don't support 64 MSI, so need to allocate INTx, but the default interrupt number 255 is invalid, so Change all the PCI Device interrupt number to 0. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Platform/Hisilicon/D05/D05.dsc | 1 + Platform/Hisilicon/D05/D05.fdf | 1 + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c | 99 ++++++++++++++++++++ Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf | 47 ++++++++++ 4 files changed, 148 insertions(+) diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc index b6e1a9d98a..0e6d5912a0 100644 --- a/Platform/Hisilicon/D05/D05.dsc +++ b/Platform/Hisilicon/D05/D05.dsc @@ -629,6 +629,7 @@ Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf + Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf # # Memory test diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf index 37d9cc0c18..32374e245e 100644 --- a/Platform/Hisilicon/D05/D05.fdf +++ b/Platform/Hisilicon/D05/D05.fdf @@ -358,6 +358,7 @@ READ_LOCK_STATUS = TRUE INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf INF Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf + INF Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c new file mode 100644 index 0000000000..8519b7139d --- /dev/null +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c @@ -0,0 +1,99 @@ +/** @file +* +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016, Linaro Limited. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include +#include +#include +#include +#include + +VOID +SetIntLine ( + ) +{ + EFI_STATUS Status; + UINTN HandleIndex; + EFI_HANDLE *HandleBuffer; + UINTN HandleCount; + EFI_PCI_IO_PROTOCOL *PciIo; + UINT8 INTLine; + UINTN Segment; + UINTN Bus; + UINTN Device; + UINTN Fun; + + Status = gBS->LocateHandleBuffer ( + ByProtocol, + &gEfiPciIoProtocolGuid, + NULL, + &HandleCount, + &HandleBuffer + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, " Locate gEfiPciIoProtocol Failed.\n")); + gBS->FreePool ((VOID *)HandleBuffer); + return; + } + + for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) { + Status = gBS->HandleProtocol ( + HandleBuffer[HandleIndex], + &gEfiPciIoProtocolGuid, + (VOID **)&PciIo + ); + if (EFI_ERROR (Status)) { + continue; + } + + INTLine = 0; + (VOID)PciIo->Pci.Write ( + PciIo, + EfiPciIoWidthUint8, + PCI_INT_LINE_OFFSET, + 1, + &INTLine); + (VOID)PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Fun); + DEBUG ((DEBUG_INFO, "Set BDF(%x-%x-%x) IntLine to 0\n", Bus, Device, Fun)); + } + + gBS->FreePool ((VOID *)HandleBuffer); + return; +} + +EFI_STATUS +EFIAPI +PlatformMiscDxeEntry ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status; + EFI_EVENT Event; + + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_CALLBACK, + SetIntLine, + NULL, + &gEfiEventReadyToBootGuid, + &Event + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Create event for SetIntLine, %r!\n", Status)); + } + + return EFI_SUCCESS; +} + diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf new file mode 100644 index 0000000000..0b365e7a53 --- /dev/null +++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf @@ -0,0 +1,47 @@ +#/** @file +# +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. +# Copyright (c) 2016, Linaro Limited. All rights reserved. +# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = PlatformMiscDxe + FILE_GUID = a48f7a09-253f-468b-87c6-caf78baf47bb + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = PlatformMiscDxeEntry + +[Sources.common] + PlatformMiscDxe.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Hisilicon/HisiPkg.dec + +[Guids] + gEfiEventReadyToBootGuid + +[Protocols] + gEfiPciIoProtocolGuid + +[LibraryClasses] + BaseLib + DebugLib + UefiBootServicesTableLib + UefiDriverEntryPoint + +[FixedPcd] + +[Depex] + TRUE -- 2.17.0