From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.126; helo=mga18.intel.com; envelope-from=david.wei@intel.com; receiver=edk2-devel@lists.01.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B2E03202E5477 for ; Fri, 29 Jun 2018 02:01:42 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Jun 2018 02:01:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,285,1526367600"; d="scan'208";a="63134998" Received: from zwei4-mobl1.ccr.corp.intel.com ([10.239.192.56]) by orsmga003.jf.intel.com with ESMTP; 29 Jun 2018 02:01:41 -0700 From: zwei4 To: edk2-devel@lists.01.org Date: Fri, 29 Jun 2018 17:01:37 +0800 Message-Id: <20180629090137.12416-1-david.wei@intel.com> X-Mailer: git-send-email 2.14.1.windows.1 Subject: [Patch][edk2-platforms/devel-MinnowBoardMax-UDK2017] Fix GCC build error. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 29 Jun 2018 09:01:42 -0000 Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: zwei4 --- Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c b/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c index 8c1dc152b8..58c0e63f1e 100644 --- a/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c +++ b/Vlv2TbltDevicePkg/Library/PchPlatformLib/PchPlatformLibrary.c @@ -267,9 +267,7 @@ VOID UINT32 GpioValue; UINT32 SSUSOffset = 0x2000; UINT32 IoBase = 0; - UINT32 MmioConf0 = 0; UINT32 MmioPadval = 0; - UINT32 PConf0Offset = 0x210; //GPIO_S5_1 pad_conf0 register offset UINT32 PValueOffset = 0x218; //GPIO_S5_1 pad_value register offset PciD31F0RegBase = MmPciAddress (0, @@ -283,7 +281,6 @@ VOID // // 0xFED0E1E0/0xFED0E0A8 is pad_Conf/pad_val register address of GPIO_S5_17 // - MmioConf0 = IoBase + SSUSOffset + PConf0Offset; MmioPadval = IoBase + SSUSOffset + PValueOffset; GpioValue = MmioRead32 (MmioPadval); @@ -312,9 +309,7 @@ VOID UINT32 GpioValue; UINT32 SSUSOffset = 0x2000; UINT32 IoBase = 0; - UINT32 MmioConf0 = 0; UINT32 MmioPadval = 0; - UINT32 PConf0Offset = 0x1E0; //GPIO_S5_2 pad_conf0 register offset UINT32 PValueOffset = 0x1E8; //GPIO_S5_2 pad_value register offset PciD31F0RegBase = MmPciAddress (0, @@ -328,7 +323,6 @@ VOID // // 0xFED0E1E0/0xFED0E0A8 is pad_Conf/pad_val register address of GPIO_S5_17 // - MmioConf0 = IoBase + SSUSOffset + PConf0Offset; MmioPadval = IoBase + SSUSOffset + PValueOffset; GpioValue = MmioRead32 (MmioPadval); -- 2.14.1.windows.1