[PATCH edk2-platforms v2 0/6] Improve D0x platforms and bug fix

[PATCH edk2-platforms v2 0/6] Improve D0x platforms and bug fix

[Ming Huang]

The major features of this patchset include:
1 Fix invoke SetMemorySpaceAttributes error bug
2 Correct ATU Cfg0/Cfg1 base address
3 Fix SetAtuConfig1RW bug
4 Add PlatformMiscDxe driver
5 optimize two pcie prots space
6 Correct smbios product name

BTW:
1 D06 source will upstream in July;
2 Installing OS by iso is supported by edk2 commit(824b6e3b5f).

Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git
branch: platforms-20180627-v2


Jason Zhang (1):
  Hisilicon/D03/D05: Correct ATU Cfg0/Cfg1 base address

Ming Huang (5):
  Hisilicon/D0x: Fix invoke SetMemorySpaceAttributes error bug
  Hisilicon/D0x: Fix SetAtuConfig1RW bug
  Hisilicon/D05: Add PlatformMiscDxe driver
  Hisilicon/D05/Pcie: optimize two pcie ports space
  Hisilicon/D0x: Correct smbios product name

 Platform/Hisilicon/D03/D03.fdf                |  4 +
 .../DS3231RealTimeClockLib.inf                |  2 +
 Platform/Hisilicon/D05/D05.dsc                | 13 +--
 Platform/Hisilicon/D05/D05.fdf                |  1 +
 .../Drivers/PlatformMiscDxe/PlatformMiscDxe.c | 99 +++++++++++++++++++
 .../PlatformMiscDxe/PlatformMiscDxe.inf       | 47 +++++++++
 .../Library/PlatformPciLib/PlatformPciLib.c   |  8 +-
 .../PciHostBridgeDxe/PciRootBridgeIo.c        | 13 +--
 .../Type01/MiscSystemManufacturerFunction.c   |  1 -
 .../Hi1616/D05AcpiTables/D05Iort.asl          |  8 +-
 .../Hi1616/D05AcpiTables/D05Mcfg.aslc         |  8 +-
 .../Hi1616/D05AcpiTables/Dsdt/D05Pci.asl      | 32 +++---
 12 files changed, 195 insertions(+), 41 deletions(-)
 create mode 100644 Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c
 create mode 100644 Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf

-- 
2.17.0

[PATCH edk2-platforms v2 1/6] Hisilicon/D0x: Fix invoke SetMemorySpaceAttributes error bug

[Ming Huang]

The edk2 commit bacfd6e let CpuDxe running latter.
CpuDxe is needed by gDS->SetMemorySpaceAttributes, and
gDS->SetMemorySpaceAttributes is invoked by some drivers.

This issue can solve by adding Depex on gEfiCpuArchProtocolGuid
to RealTimeClockLib.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
 Platform/Hisilicon/D03/D03.fdf                                                   | 4 ++++
 Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf | 2 ++
 2 files changed, 6 insertions(+)

diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
index 1383aa1091..73e2b7e958 100644
--- a/Platform/Hisilicon/D03/D03.fdf
+++ b/Platform/Hisilicon/D03/D03.fdf
@@ -146,6 +146,10 @@ READ_STATUS        = TRUE
 READ_LOCK_CAP      = TRUE
 READ_LOCK_STATUS   = TRUE
 
+  APRIORI DXE {
+    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  }
+
   INF MdeModulePkg/Core/Dxe/DxeMain.inf
   INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
 
diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
index 319c35c724..ae7116dc31 100644
--- a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
+++ b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
@@ -46,3 +46,5 @@
 
 [Pcd]
 
+[Depex]
+  gEfiCpuArchProtocolGuid
-- 
2.17.0

[PATCH edk2-platforms v2 2/6] Hisilicon/D03/D05: Correct ATU Cfg0/Cfg1 base address

[Ming Huang]

From: Jason Zhang <zhangjinsong2@huawei.com>

1. During test PCIe mcs9922 UART card, the card can't
   work because the IO ATU config is overlap by Cfg0/Cfg1
   ATU address.
2. After adjust the ATU windows, Cfg0/Cfg1 config as below:
     Cfg0 is equal to "ECAM + (BusBase, 0, 0)"
     Cfg1 is equal to "ECAM + (BusBase + 2, 0, 0)"

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Ming Huang <ming.huang@linaro.org>
---
 Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
index 55b80aa4e4..e5f66eaa4a 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -640,11 +640,12 @@ void SetAtuConfig0RW (
 {
     UINTN RbPciBase = Private->RbPciBar;
     UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1;
+    UINT64 Cfg0Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0, 0, 0);
 
 
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
-    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
-    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg0Base));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg0Base >> 32));
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
@@ -666,12 +667,12 @@ void SetAtuConfig1RW (
 {
     UINTN RbPciBase = Private->RbPciBar;
     UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1;
-
+    UINT64 Cfg1Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0);
 
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1);
-    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Private->Ecam));
-    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(Private->Ecam) >> 32));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg1Base));
+    MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg1Base >> 32));
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
-- 
2.17.0

[PATCH edk2-platforms v2 3/6] Hisilicon/D0x: Fix SetAtuConfig1RW bug

[Ming Huang]

The MemLimit is wrong when the Private->BusLimit equal 0xFF.
This patch fix enumerating device plug in switch cart failed issue.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
 Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
index e5f66eaa4a..3f894e8eec 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -666,7 +666,7 @@ void SetAtuConfig1RW (
     )
 {
     UINTN RbPciBase = Private->RbPciBar;
-    UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1;
+    UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit, 0x1F, 0x07, 0xFFF);
     UINT64 Cfg1Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0);
 
     MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
-- 
2.17.0

[PATCH edk2-platforms v2 4/6] Hisilicon/D05: Add PlatformMiscDxe driver

[Ming Huang]

Fix the issue of onboard Nic not work kerenl with AMD GPU and
NVME SSD in board. The GPU don't support 64 MSI, so need to
allocate INTx, but the default interrupt number 255 is invalid,
so Change all the PCI Device interrupt number to 0.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
 Platform/Hisilicon/D05/D05.dsc                                     |  1 +
 Platform/Hisilicon/D05/D05.fdf                                     |  1 +
 Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c   | 99 ++++++++++++++++++++
 Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf | 47 ++++++++++
 4 files changed, 148 insertions(+)

diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index b6e1a9d98a..0e6d5912a0 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -629,6 +629,7 @@
 
 
   Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+  Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
 
   #
   # Memory test
diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
index 4503776d63..61e8d907f9 100644
--- a/Platform/Hisilicon/D05/D05.fdf
+++ b/Platform/Hisilicon/D05/D05.fdf
@@ -354,6 +354,7 @@ READ_LOCK_STATUS   = TRUE
   INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
   INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
   INF Platform/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
+  INF Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
 
   INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
 
diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c
new file mode 100644
index 0000000000..8519b7139d
--- /dev/null
+++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c
@@ -0,0 +1,99 @@
+/** @file
+*
+*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <IndustryStandard/Pci.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/PciIo.h>
+
+VOID
+SetIntLine (
+  )
+{
+  EFI_STATUS                         Status;
+  UINTN                              HandleIndex;
+  EFI_HANDLE                         *HandleBuffer;
+  UINTN                              HandleCount;
+  EFI_PCI_IO_PROTOCOL                *PciIo;
+  UINT8                              INTLine;
+  UINTN                              Segment;
+  UINTN                              Bus;
+  UINTN                              Device;
+  UINTN                              Fun;
+
+  Status = gBS->LocateHandleBuffer (
+                  ByProtocol,
+                  &gEfiPciIoProtocolGuid,
+                  NULL,
+                  &HandleCount,
+                  &HandleBuffer
+                  );
+  if (EFI_ERROR (Status)) {
+      DEBUG  ((DEBUG_ERROR, " Locate gEfiPciIoProtocol Failed.\n"));
+      gBS->FreePool ((VOID *)HandleBuffer);
+      return;
+  }
+
+  for (HandleIndex = 0; HandleIndex < HandleCount; HandleIndex++) {
+      Status = gBS->HandleProtocol (
+                      HandleBuffer[HandleIndex],
+                      &gEfiPciIoProtocolGuid,
+                      (VOID **)&PciIo
+                      );
+      if (EFI_ERROR (Status)) {
+          continue;
+      }
+
+      INTLine = 0;
+      (VOID)PciIo->Pci.Write (
+                         PciIo,
+                         EfiPciIoWidthUint8,
+                         PCI_INT_LINE_OFFSET,
+                         1,
+                         &INTLine);
+      (VOID)PciIo->GetLocation (PciIo, &Segment, &Bus, &Device, &Fun);
+      DEBUG ((DEBUG_INFO, "Set BDF(%x-%x-%x) IntLine to 0\n", Bus, Device, Fun));
+  }
+
+  gBS->FreePool ((VOID *)HandleBuffer);
+  return;
+}
+
+EFI_STATUS
+EFIAPI
+PlatformMiscDxeEntry (
+  IN EFI_HANDLE           ImageHandle,
+  IN EFI_SYSTEM_TABLE     *SystemTable
+  )
+{
+  EFI_STATUS  Status;
+  EFI_EVENT   Event;
+
+  Status = gBS->CreateEventEx (
+                  EVT_NOTIFY_SIGNAL,
+                  TPL_CALLBACK,
+                  SetIntLine,
+                  NULL,
+                  &gEfiEventReadyToBootGuid,
+                  &Event
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "Create event for SetIntLine, %r!\n", Status));
+  }
+
+  return EFI_SUCCESS;
+}
+
diff --git a/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
new file mode 100644
index 0000000000..0b365e7a53
--- /dev/null
+++ b/Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf
@@ -0,0 +1,47 @@
+#/** @file
+#
+#    Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = PlatformMiscDxe
+  FILE_GUID                      = a48f7a09-253f-468b-87c6-caf78baf47bb
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = PlatformMiscDxeEntry
+
+[Sources.common]
+  PlatformMiscDxe.c
+
+[Packages]
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Hisilicon/HisiPkg.dec
+
+[Guids]
+  gEfiEventReadyToBootGuid
+
+[Protocols]
+  gEfiPciIoProtocolGuid
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+
+[FixedPcd]
+
+[Depex]
+  TRUE
-- 
2.17.0

[PATCH edk2-platforms v2 5/6] Hisilicon/D05/Pcie: optimize two pcie ports space

[Ming Huang]

Optimize pcie space for promoting usage rate.Change regions order
of NA-Pcie2 and NB-Pcie1 to MEM-ECAM-IO in DAW,so MemoryRegion
can satisfy the requirement of larger address alignment.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
 Platform/Hisilicon/D05/D05.dsc                                 | 12 ++++----
 Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c |  8 ++---
 Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl             |  8 ++---
 Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc            |  8 ++---
 Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl         | 32 ++++++++++----------
 5 files changed, 34 insertions(+), 34 deletions(-)

diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
index 0e6d5912a0..ab7c5caf86 100644
--- a/Platform/Hisilicon/D05/D05.dsc
+++ b/Platform/Hisilicon/D05/D05.dsc
@@ -305,13 +305,13 @@
   gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbf0000
   gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000
   gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbf0000
-  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8000000
   gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77f0000
   gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000
   gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbf0000
   gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000
   gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2ff0000
-  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0000000
   gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77f0000
   gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000
   gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36f0000
@@ -336,10 +336,10 @@
 
   gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000
   gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000
-  gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8000000
   gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000
   gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000
-  gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0000000
   gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000
   gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
   gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
@@ -353,10 +353,10 @@
 
   gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000
   gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000
-  gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xaf7f0000
   gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000
   gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000
-  gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b77f0000
   gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000
   gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000
   gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000
diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
index 57283a1053..ed6c4ac321 100644
--- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
+++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
@@ -60,8 +60,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
   /* Port 2 */
   {
       PCI_HB0RB2_ECAM_BASE,
-      0x80,  //BusBase
-      0x87, //BusLimit
+      0xF8,  //BusBase
+      0xFF, //BusLimit
       PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase
       PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit
       (PCI_HB0RB2_IO_BASE),  //IOBase
@@ -106,8 +106,8 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
   /* Port 5 */
   {
       PCI_HB0RB5_ECAM_BASE,//ecam
-      0x0,  //BusBase
-      0x7, //BusLimit
+      0x78,  //BusBase
+      0x7F, //BusLimit
       PCI_HB0RB5_CPUMEMREGIONBASE, //Membase
       PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit
       (PCI_HB0RB5_IO_BASE),  //IoBase
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl
index 50ccac1b06..9955f6dbeb 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl
@@ -412,9 +412,9 @@
 [0004]                      ATS Attribute : 00000000
 [0004]                 PCI Segment Number : 00000002
 
-[0004]                         Input base : 00008000
+[0004]                         Input base : 0000f800
 [0004]                           ID Count : 00000800
-[0004]                        Output Base : 00008000
+[0004]                        Output Base : 0000f800
 [0004]                   Output Reference : 00000064
 [0004]              Flags (decoded below) : 00000000
                            Single Mapping : 0
@@ -469,9 +469,9 @@
 [0004]                      ATS Attribute : 00000000
 [0004]                 PCI Segment Number : 00000005
 
-[0004]                         Input base : 00000000
+[0004]                         Input base : 00007800
 [0004]                           ID Count : 00000800
-[0004]                        Output Base : 00000000
+[0004]                        Output Base : 00007800
 [0004]                   Output Reference : 0000007c
 [0004]              Flags (decoded below) : 00000000
                            Single Mapping : 0
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc
index b47cfec7bd..64807b1714 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc
@@ -57,8 +57,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
     {
       0xa0000000,                                         //Base Address
       0x2,                                                //Segment Group Number
-      0x80,                                               //Start Bus Number
-      0x87,                                               //End Bus Number
+      0xF8,                                               //Start Bus Number
+      0xFF,                                               //End Bus Number
       0x00000000,                                         //Reserved
     },
     //1p NB PCIe0
@@ -73,8 +73,8 @@ EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
     {
       0x8b0000000,                                        //Base Address
       0x5,                                                //Segment Group Number
-      0x0,                                                //Start Bus Number
-      0x7,                                                //End Bus Number
+      0x78,                                                //Start Bus Number
+      0x7F,                                                //End Bus Number
       0x00000000,                                         //Reserved
     },
     //1p NB PCIe2
diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
index 122e4f072c..3f09e5e568 100644
--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
+++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
@@ -89,15 +89,15 @@ Scope(_SB)
     Name (_HID, "PNP0A08") // PCI Express Root Bridge
     Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
     Name(_SEG, 2) // Segment of this Root complex
-    Name(_BBN, 0x80) // Base Bus Number
+    Name(_BBN, 0xF8) // Base Bus Number
     Name(_CCA, 1)
     Method (_CRS, 0, Serialized) { // Root complex resources
       Name (RBUF, ResourceTemplate () {
         WordBusNumber ( // Bus numbers assigned to this root
           ResourceProducer, MinFixed, MaxFixed, PosDecode,
           0, // AddressGranularity
-          0x80, // AddressMinimum - Minimum Bus Number
-          0x87, // AddressMaximum - Maximum Bus Number
+          0xF8, // AddressMinimum - Minimum Bus Number
+          0xFF, // AddressMaximum - Maximum Bus Number
           0, // AddressTranslation - Set to 0
           0x8 // RangeLength - Number of Busses
         )
@@ -109,8 +109,8 @@ Scope(_SB)
           Cacheable,
           ReadWrite,
           0x0, // Granularity
-          0xa8800000, // Min Base Address
-          0xaffeffff, // Max Base Address
+          0xa8000000, // Min Base Address
+          0xaf7effff, // Max Base Address
           0x0, // Translate
           0x77f0000 // Length
         )
@@ -123,7 +123,7 @@ Scope(_SB)
           0x0, // Granularity
           0x0, // Min Base Address
           0xffff, // Max Base Address
-          0xafff0000, // Translate
+          0xaf7f0000, // Translate
           0x10000 // Length
         )
       }) // Name(RBUF)
@@ -165,7 +165,7 @@ Scope(_SB)
   {
     Name (_HID, "PNP0C02")  // Motherboard reserved resource
     Name (_CRS, ResourceTemplate (){
-      Memory32Fixed (ReadWrite, 0xa8000000 , 0x800000) //ECAM space for [bus 80-87]
+      Memory32Fixed (ReadWrite, 0xaf800000 , 0x800000) //ECAM space for [bus f8-ff]
     })
     Method (_STA, 0x0, NotSerialized)
     {
@@ -280,15 +280,15 @@ Scope(_SB)
     Name (_HID, "PNP0A08") // PCI Express Root Bridge
     Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
     Name(_SEG, 5) // Segment of this Root complex
-    Name(_BBN, 0x0) // Base Bus Number
+    Name(_BBN, 0x78) // Base Bus Number
     Name(_CCA, 1)
     Method (_CRS, 0, Serialized) { // Root complex resources
       Name (RBUF, ResourceTemplate () {
         WordBusNumber ( // Bus numbers assigned to this root
           ResourceProducer, MinFixed, MaxFixed, PosDecode,
           0, // AddressGranularity
-          0x0, // AddressMinimum - Minimum Bus Number
-          0x7, // AddressMaximum - Maximum Bus Number
+          0x78, // AddressMinimum - Minimum Bus Number
+          0x7f, // AddressMaximum - Maximum Bus Number
           0, // AddressTranslation - Set to 0
           0x8 // RangeLength - Number of Busses
         )
@@ -300,8 +300,8 @@ Scope(_SB)
           Cacheable,
           ReadWrite,
           0x0, // Granularity
-          0xb0800000, // Min Base Address
-          0xb7feffff, // Max Base Address
+          0xb0000000, // Min Base Address
+          0xb77effff, // Max Base Address
           0x800000000, // Translate
           0x77f0000 // Length
         )
@@ -314,7 +314,7 @@ Scope(_SB)
           0x0, // Granularity
           0x0, // Min Base Address
           0xffff, // Max Base Address
-          0x8b7ff0000, // Translate
+          0x8b77f0000, // Translate
           0x10000 // Length
         )
       }) // Name(RBUF)
@@ -593,7 +593,7 @@ Scope(_SB)
         0x0, // Translate
         0x800000 // Length
       )
-      QwordMemory ( //ECAM space for [bus 0-7]
+      QwordMemory ( //ECAM space for [bus 78-7f]
         ResourceConsumer,
         PosDecode,
         MinFixed,
@@ -601,8 +601,8 @@ Scope(_SB)
         NonCacheable,
         ReadWrite,
         0x0, // Granularity
-        0x8b0000000, // Min Base Address
-        0x8b07fffff, // Max Base Address
+        0x8b7800000, // Min Base Address
+        0x8b7ffffff, // Max Base Address
         0x0, // Translate
         0x800000 // Length
       )
-- 
2.17.0

[PATCH edk2-platforms v2 6/6] Hisilicon/D0x: Correct smbios product name

[Ming Huang]

The product name getting from BMC is not suitable.
It may cause ambiguity.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <ming.huang@linaro.org>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
 Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c
index fcefe2442c..5e965c996c 100644
--- a/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c
+++ b/Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type01/MiscSystemManufacturerFunction.c
@@ -86,7 +86,6 @@ MISC_SMBIOS_TABLE_FUNCTION(MiscSystemManufacturer)
         TokenToUpdate = STRING_TOKEN (STR_MISC_SYSTEM_VERSION);
         HiiSetString (mHiiHandle, TokenToUpdate, pVersion, NULL);
     }
-    UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_PRODUCT_NAME), ProductNameType01);
     UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_SERIAL_NUMBER), SerialNumType01);
     UpdateSmbiosInfo(mHiiHandle, STRING_TOKEN (STR_MISC_SYSTEM_MANUFACTURER), SystemManufacturerType01);
 
-- 
2.17.0

Re: [PATCH edk2-platforms v2 1/6] Hisilicon/D0x: Fix invoke SetMemorySpaceAttributes error bug

[Ard Biesheuvel]

On 4 July 2018 at 09:51, Ming Huang <ming.huang@linaro.org> wrote:
> The edk2 commit bacfd6e let CpuDxe running latter.
> CpuDxe is needed by gDS->SetMemorySpaceAttributes, and
> gDS->SetMemorySpaceAttributes is invoked by some drivers.
>
> This issue can solve by adding Depex on gEfiCpuArchProtocolGuid
> to RealTimeClockLib.
>

If this is the case, why do we still need the APRIORI DXE section?

> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Ming Huang <ming.huang@linaro.org>
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
> ---
>  Platform/Hisilicon/D03/D03.fdf                                                   | 4 ++++
>  Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf | 2 ++
>  2 files changed, 6 insertions(+)
>
> diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
> index 1383aa1091..73e2b7e958 100644
> --- a/Platform/Hisilicon/D03/D03.fdf
> +++ b/Platform/Hisilicon/D03/D03.fdf
> @@ -146,6 +146,10 @@ READ_STATUS        = TRUE
>  READ_LOCK_CAP      = TRUE
>  READ_LOCK_STATUS   = TRUE
>
> +  APRIORI DXE {
> +    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
> +  }
> +
>    INF MdeModulePkg/Core/Dxe/DxeMain.inf
>    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
>
> diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
> index 319c35c724..ae7116dc31 100644
> --- a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
> +++ b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
> @@ -46,3 +46,5 @@
>
>  [Pcd]
>
> +[Depex]
> +  gEfiCpuArchProtocolGuid
> --
> 2.17.0
>

Re: [PATCH edk2-platforms v2 1/6] Hisilicon/D0x: Fix invoke SetMemorySpaceAttributes error bug

[Ming]

在 11/07/2018 22:19, Ard Biesheuvel 写道:
> On 4 July 2018 at 09:51, Ming Huang <ming.huang@linaro.org> wrote:
>> The edk2 commit bacfd6e let CpuDxe running latter.
>> CpuDxe is needed by gDS->SetMemorySpaceAttributes, and
>> gDS->SetMemorySpaceAttributes is invoked by some drivers.
>>
>> This issue can solve by adding Depex on gEfiCpuArchProtocolGuid
>> to RealTimeClockLib.
>>
> 
> If this is the case, why do we still need the APRIORI DXE section?
> 

This APRIORI DXE will be removed in V3.

The new PciHostBridge which is developed by Heyi.Guo will add in V3.

Thanks.

>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Ming Huang <ming.huang@linaro.org>
>> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
>> ---
>>  Platform/Hisilicon/D03/D03.fdf                                                   | 4 ++++
>>  Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf | 2 ++
>>  2 files changed, 6 insertions(+)
>>
>> diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
>> index 1383aa1091..73e2b7e958 100644
>> --- a/Platform/Hisilicon/D03/D03.fdf
>> +++ b/Platform/Hisilicon/D03/D03.fdf
>> @@ -146,6 +146,10 @@ READ_STATUS        = TRUE
>>  READ_LOCK_CAP      = TRUE
>>  READ_LOCK_STATUS   = TRUE
>>
>> +  APRIORI DXE {
>> +    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
>> +  }
>> +
>>    INF MdeModulePkg/Core/Dxe/DxeMain.inf
>>    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
>>
>> diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
>> index 319c35c724..ae7116dc31 100644
>> --- a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
>> +++ b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
>> @@ -46,3 +46,5 @@
>>
>>  [Pcd]
>>
>> +[Depex]
>> +  gEfiCpuArchProtocolGuid
>> --
>> 2.17.0
>>

Re: [PATCH edk2-platforms v2 1/6] Hisilicon/D0x: Fix invoke SetMemorySpaceAttributes error bug

[Ard Biesheuvel]

On 12 July 2018 at 10:50, Ming <ming.huang@linaro.org> wrote:
>
>
> 在 11/07/2018 22:19, Ard Biesheuvel 写道:
>> On 4 July 2018 at 09:51, Ming Huang <ming.huang@linaro.org> wrote:
>>> The edk2 commit bacfd6e let CpuDxe running latter.
>>> CpuDxe is needed by gDS->SetMemorySpaceAttributes, and
>>> gDS->SetMemorySpaceAttributes is invoked by some drivers.
>>>
>>> This issue can solve by adding Depex on gEfiCpuArchProtocolGuid
>>> to RealTimeClockLib.
>>>
>>
>> If this is the case, why do we still need the APRIORI DXE section?
>>
>
> This APRIORI DXE will be removed in V3.
>
> The new PciHostBridge which is developed by Heyi.Guo will add in V3.
>

OK, so should I wait for the v3 series then?


>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>> Signed-off-by: Ming Huang <ming.huang@linaro.org>
>>> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
>>> ---
>>>  Platform/Hisilicon/D03/D03.fdf                                                   | 4 ++++
>>>  Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf | 2 ++
>>>  2 files changed, 6 insertions(+)
>>>
>>> diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
>>> index 1383aa1091..73e2b7e958 100644
>>> --- a/Platform/Hisilicon/D03/D03.fdf
>>> +++ b/Platform/Hisilicon/D03/D03.fdf
>>> @@ -146,6 +146,10 @@ READ_STATUS        = TRUE
>>>  READ_LOCK_CAP      = TRUE
>>>  READ_LOCK_STATUS   = TRUE
>>>
>>> +  APRIORI DXE {
>>> +    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
>>> +  }
>>> +
>>>    INF MdeModulePkg/Core/Dxe/DxeMain.inf
>>>    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
>>>
>>> diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
>>> index 319c35c724..ae7116dc31 100644
>>> --- a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
>>> +++ b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
>>> @@ -46,3 +46,5 @@
>>>
>>>  [Pcd]
>>>
>>> +[Depex]
>>> +  gEfiCpuArchProtocolGuid
>>> --
>>> 2.17.0
>>>

Re: [PATCH edk2-platforms v2 1/6] Hisilicon/D0x: Fix invoke SetMemorySpaceAttributes error bug

[Ming]

在 13/07/2018 14:46, Ard Biesheuvel 写道:
> On 12 July 2018 at 10:50, Ming <ming.huang@linaro.org> wrote:
>>
>>
>> 在 11/07/2018 22:19, Ard Biesheuvel 写道:
>>> On 4 July 2018 at 09:51, Ming Huang <ming.huang@linaro.org> wrote:
>>>> The edk2 commit bacfd6e let CpuDxe running latter.
>>>> CpuDxe is needed by gDS->SetMemorySpaceAttributes, and
>>>> gDS->SetMemorySpaceAttributes is invoked by some drivers.
>>>>
>>>> This issue can solve by adding Depex on gEfiCpuArchProtocolGuid
>>>> to RealTimeClockLib.
>>>>
>>>
>>> If this is the case, why do we still need the APRIORI DXE section?
>>>
>>
>> This APRIORI DXE will be removed in V3.
>>
>> The new PciHostBridge which is developed by Heyi.Guo will add in V3.
>>
> 
> OK, so should I wait for the v3 series then?
> 
> 

Heyi.Guo suggest that the new PciHostBridge patch set upstream in addition patch set
for clarity.
This patch set v3 will send soon.

Thanks.

>>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>>> Signed-off-by: Ming Huang <ming.huang@linaro.org>
>>>> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
>>>> ---
>>>>  Platform/Hisilicon/D03/D03.fdf                                                   | 4 ++++
>>>>  Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf | 2 ++
>>>>  2 files changed, 6 insertions(+)
>>>>
>>>> diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
>>>> index 1383aa1091..73e2b7e958 100644
>>>> --- a/Platform/Hisilicon/D03/D03.fdf
>>>> +++ b/Platform/Hisilicon/D03/D03.fdf
>>>> @@ -146,6 +146,10 @@ READ_STATUS        = TRUE
>>>>  READ_LOCK_CAP      = TRUE
>>>>  READ_LOCK_STATUS   = TRUE
>>>>
>>>> +  APRIORI DXE {
>>>> +    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
>>>> +  }
>>>> +
>>>>    INF MdeModulePkg/Core/Dxe/DxeMain.inf
>>>>    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
>>>>
>>>> diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
>>>> index 319c35c724..ae7116dc31 100644
>>>> --- a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
>>>> +++ b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
>>>> @@ -46,3 +46,5 @@
>>>>
>>>>  [Pcd]
>>>>
>>>> +[Depex]
>>>> +  gEfiCpuArchProtocolGuid
>>>> --
>>>> 2.17.0
>>>>