From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c00::244; helo=mail-pf0-x244.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9BBD82097F556 for ; Fri, 13 Jul 2018 01:15:48 -0700 (PDT) Received: by mail-pf0-x244.google.com with SMTP id q7-v6so21119213pff.2 for ; Fri, 13 Jul 2018 01:15:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=WrSsyfmvsoJuLBfJjIJdYJOBv8xRTzruP3aUr5FW1MQ=; b=BcBn7rkvwsEVSQ/WaQMhCu9GZSpGWdMvP//OTh+Hzle5w2c5tL6Ztr1ju/KO3aLbid Al6LEW+1G2kwzjKnq5cvvaJtz0IlX9uq43owAAUq5FlTdhHO5mmrMXk2YCpc4dqWeMIz nBgooty9z02WAocMTLTMXLXEO+VD+TLHvymUg= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=WrSsyfmvsoJuLBfJjIJdYJOBv8xRTzruP3aUr5FW1MQ=; b=ghawf+eXa1Hr5ONPTQwghJOoCTXPKo8Yx81NMf6HUdK1Wa4uI9CWwiZUa6cpw5X02q H00HQgGuE9ksfUZZjJhvNNGJzgP9kI2AYgN12AxPXEE8d4jCCP8JQIzTUPVl6Afv39/a tktI+Iow1osUbsFYLuu0Z0Ql55SzKT4kPB2VPvevcItsz41lV+mizmsO8jOIOUuRqbb0 mjejc4R1A1aH5exnZ9agZXlKvYDmnRtG8K/WNsHxqXzKDTRas33kZoAy6KmtWyUWSZOY Y+jlHXz7yjzhmMChbQsdRGatIRcrTo6M2BFHDGaZaaIs0RpdCd0/5gVNYNC01ZOzPZZM iJKw== X-Gm-Message-State: AOUpUlEC/oEGPZlI5JKrheCMvMC6MrMMyweGaSb0yxehOBSpwdf5YL3I ryT/mDeWGZ4+snPC5cptZa6euKCCqtQ= X-Google-Smtp-Source: AAOMgpetDjLkvW6cJ9TC0QYPqe+On5dtH+McY8s3C5vtDPsrqkH7qZ62dEYnCL85CNzKDgLbQ+94oA== X-Received: by 2002:a62:e0d5:: with SMTP id d82-v6mr6004220pfm.59.1531469747916; Fri, 13 Jul 2018 01:15:47 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id e7-v6sm24400196pgc.55.2018.07.13.01.15.45 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 13 Jul 2018 01:15:47 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, Ming Huang Date: Fri, 13 Jul 2018 16:15:34 +0800 Message-Id: <20180713081540.8414-1-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 Subject: [PATCH edk2-platforms v3 0/6] Improve D0x platforms and bug fix X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 13 Jul 2018 08:15:48 -0000 The major features of this patchset include: 1 Fix invoke SetMemorySpaceAttributes error bug 2 Correct ATU Cfg0/Cfg1 base address 3 Fix SetAtuConfig1RW bug 4 Add PlatformMiscDxe driver 5 optimize two pcie prots space 6 Correct smbios product name BTW: 1 D06 source will upstream in July; 2 Installing OS by iso is supported by edk2 commit(824b6e3b5f). Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git branch: platforms-20180627-v3 Jason Zhang (1): Hisilicon/D03/D05: Correct ATU Cfg0/Cfg1 base address Ming Huang (5): Hisilicon/D0x: Fix invoke SetMemorySpaceAttributes error bug Hisilicon/D0x: Fix SetAtuConfig1RW bug Hisilicon/D05: Add PlatformMiscDxe driver Hisilicon/D05/Pcie: optimize two pcie ports space Hisilicon/D0x: Correct smbios product name .../DS3231RealTimeClockLib.inf | 2 + Platform/Hisilicon/D05/D05.dsc | 13 +-- Platform/Hisilicon/D05/D05.fdf | 1 + .../Drivers/PlatformMiscDxe/PlatformMiscDxe.c | 99 +++++++++++++++++++ .../PlatformMiscDxe/PlatformMiscDxe.inf | 47 +++++++++ .../Library/PlatformPciLib/PlatformPciLib.c | 8 +- .../PciHostBridgeDxe/PciRootBridgeIo.c | 13 +-- .../Type01/MiscSystemManufacturerFunction.c | 1 - .../Hi1616/D05AcpiTables/D05Iort.asl | 8 +- .../Hi1616/D05AcpiTables/D05Mcfg.aslc | 8 +- .../Hi1616/D05AcpiTables/Dsdt/D05Pci.asl | 32 +++--- 11 files changed, 191 insertions(+), 41 deletions(-) create mode 100644 Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.c create mode 100644 Platform/Hisilicon/D05/Drivers/PlatformMiscDxe/PlatformMiscDxe.inf -- 2.17.0