* [platforms: PATCH v2 0/6] Armada7k8k ICU support @ 2018-07-13 8:12 Marcin Wojtas 2018-07-13 8:12 ` [platforms: PATCH v2 1/6] Marvell/Armada70x0Db: Set correct CP110 count Marcin Wojtas ` (6 more replies) 0 siblings, 7 replies; 10+ messages in thread From: Marcin Wojtas @ 2018-07-13 8:12 UTC (permalink / raw) To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, hannah, mw, jsd, jaz Hi, The second version of the ICU patchset brings all corrections according to all review remarks. They were mostly style / naming - detailed list can be found in the changelog below. The patches are available in the github: https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/icu-upstream-r20180713 I'm looking forward to review and any comments/remarks. Best regards, Marcin Changelog v1 -> v2 * 1,6 - Add Ard's RB * 2 - Change ICU_IRQ_TYPE to IcuIrqTypeLevel / IcuIrqTypeEdge * 3 - Use EFI_PHYSICAL_ADDRESS * 4 - Put a space after { and before } - Change enum values to IcuGroupXxx format * 5 - Use ICU_GROUP_REGISTER_BASE_OFFSET instead of a raw value in macros - Add missing parentheses and use sizeof (UINT32) in ICU_INT_CFG macro - Use mEfiExitBootServicesEvent - not initialized and STATIC - s/IcuConfigDefault/IcuInitialConfig/ - Break to long lines Marcin Wojtas (6): Marvell/Armada70x0Db: Set correct CP110 count Marvell/Library: Introduce ArmadaIcuLib class Marvell/Library: Armada7k8kSoCDescLib: Enable getting CP base address Marvell/Library: Armada7k8kSoCDescLib: Introduce ICU information Marvell/Library: Implement common ArmadaIcuLib Marvell/Armada7k8k: Enable ICU configuration Silicon/Marvell/Marvell.dec | 1 + Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 + Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 7 +- Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf | 1 + Silicon/Marvell/Library/IcuLib/IcuLib.inf | 38 +++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 12 + Silicon/Marvell/Include/Library/ArmadaIcuLib.h | 45 +++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 39 +++ Silicon/Marvell/Library/IcuLib/IcuLib.h | 47 +++ Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c | 2 + Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 50 +++ Silicon/Marvell/Library/IcuLib/IcuLib.c | 317 ++++++++++++++++++++ 12 files changed, 558 insertions(+), 2 deletions(-) create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.inf create mode 100644 Silicon/Marvell/Include/Library/ArmadaIcuLib.h create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.h create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.c -- 2.7.4 ^ permalink raw reply [flat|nested] 10+ messages in thread
* [platforms: PATCH v2 1/6] Marvell/Armada70x0Db: Set correct CP110 count 2018-07-13 8:12 [platforms: PATCH v2 0/6] Armada7k8k ICU support Marcin Wojtas @ 2018-07-13 8:12 ` Marcin Wojtas 2018-07-13 8:12 ` [platforms: PATCH v2 2/6] Marvell/Library: Introduce ArmadaIcuLib class Marcin Wojtas ` (5 subsequent siblings) 6 siblings, 0 replies; 10+ messages in thread From: Marcin Wojtas @ 2018-07-13 8:12 UTC (permalink / raw) To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, hannah, mw, jsd, jaz As a preparation for adding the ICU (Interrupt Consolidation Unit) library implementation a correct CP110 count is required. Do it for Armada70x0Db and fix depending XHCI/AHCI PCD's accordingly. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc index 5ccee1b..2240a57 100644 --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc @@ -53,6 +53,9 @@ # ################################################################################ [PcdsFixedAtBuild.common] + #CP110 count + gMarvellTokenSpaceGuid.PcdMaxCpCount|1 + #MPP gMarvellTokenSpaceGuid.PcdMppChipCount|2 @@ -129,8 +132,8 @@ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 } #PciEmulation - gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x0 } - gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x0 } + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 } + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 } gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } #RTC -- 2.7.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [platforms: PATCH v2 2/6] Marvell/Library: Introduce ArmadaIcuLib class 2018-07-13 8:12 [platforms: PATCH v2 0/6] Armada7k8k ICU support Marcin Wojtas 2018-07-13 8:12 ` [platforms: PATCH v2 1/6] Marvell/Armada70x0Db: Set correct CP110 count Marcin Wojtas @ 2018-07-13 8:12 ` Marcin Wojtas 2018-07-13 8:12 ` [platforms: PATCH v2 3/6] Marvell/Library: Armada7k8kSoCDescLib: Enable getting CP base address Marcin Wojtas ` (4 subsequent siblings) 6 siblings, 0 replies; 10+ messages in thread From: Marcin Wojtas @ 2018-07-13 8:12 UTC (permalink / raw) To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, hannah, mw, jsd, jaz ICU (Interrupt Consolidation Unit) is a mechanism, that allows to send a message-based interrupts from the CP110 unit (South Bridge) to the Application Processor hardware block. After dispatching the interrupts in the GIC are generated. This patch adds a basic version of the library, that allows to configure a static mapping between CP110 interfaces and GIC. It is required for the cases, where the OS does not support the ICU controller on its own (e.g. ACPI boot). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> --- Silicon/Marvell/Marvell.dec | 1 + Silicon/Marvell/Include/Library/ArmadaIcuLib.h | 45 ++++++++++++++++++++ 2 files changed, 46 insertions(+) create mode 100644 Silicon/Marvell/Include/Library/ArmadaIcuLib.h diff --git a/Silicon/Marvell/Marvell.dec b/Silicon/Marvell/Marvell.dec index 4def897..616624e 100644 --- a/Silicon/Marvell/Marvell.dec +++ b/Silicon/Marvell/Marvell.dec @@ -61,6 +61,7 @@ [LibraryClasses] ArmadaBoardDescLib|Include/Library/ArmadaBoardDescLib.h + ArmadaIcuLib|Include/Library/ArmadaIcuLib.h ArmadaSoCDescLib|Include/Library/ArmadaSoCDescLib.h SampleAtResetLib|Include/Library/SampleAtResetLib.h diff --git a/Silicon/Marvell/Include/Library/ArmadaIcuLib.h b/Silicon/Marvell/Include/Library/ArmadaIcuLib.h new file mode 100644 index 0000000..426734e --- /dev/null +++ b/Silicon/Marvell/Include/Library/ArmadaIcuLib.h @@ -0,0 +1,45 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ +#ifndef __ARMADA_ICU_LIB_H__ +#define __ARMADA_ICU_LIB_H__ + +typedef enum { + IcuIrqTypeLevel = 0, + IcuIrqTypeEdge = 1 +} ICU_IRQ_TYPE; + +typedef struct { + UINTN IcuId; + UINTN SpiId; + ICU_IRQ_TYPE IrqType; +} ICU_IRQ; + +typedef struct { + const ICU_IRQ *Map; + UINTN Size; +} ICU_CONFIG_ENTRY; + +typedef struct { + ICU_CONFIG_ENTRY NonSecure; + ICU_CONFIG_ENTRY Sei; + ICU_CONFIG_ENTRY Rei; +} ICU_CONFIG; + +EFI_STATUS +EFIAPI +ArmadaIcuInitialize ( + VOID + ); + +#endif /* __ARMADA_ICU_LIB_H__ */ -- 2.7.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [platforms: PATCH v2 3/6] Marvell/Library: Armada7k8kSoCDescLib: Enable getting CP base address 2018-07-13 8:12 [platforms: PATCH v2 0/6] Armada7k8k ICU support Marcin Wojtas 2018-07-13 8:12 ` [platforms: PATCH v2 1/6] Marvell/Armada70x0Db: Set correct CP110 count Marcin Wojtas 2018-07-13 8:12 ` [platforms: PATCH v2 2/6] Marvell/Library: Introduce ArmadaIcuLib class Marcin Wojtas @ 2018-07-13 8:12 ` Marcin Wojtas 2018-07-13 8:12 ` [platforms: PATCH v2 4/6] Marvell/Library: Armada7k8kSoCDescLib: Introduce ICU information Marcin Wojtas ` (3 subsequent siblings) 6 siblings, 0 replies; 10+ messages in thread From: Marcin Wojtas @ 2018-07-13 8:12 UTC (permalink / raw) To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, hannah, mw, jsd, jaz For upcoming patches there is a need to get the CP110 base address, introduce according getter function for it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> --- Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 9 +++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 11 +++++++++++ 2 files changed, 20 insertions(+) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h index d2bcf2a..30e6378 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -37,6 +37,15 @@ ArmadaSoCDescComPhyGet ( ); // +// South Bridge description +// +EFI_PHYSICAL_ADDRESS +EFIAPI +ArmadaSoCDescCpBaseGet ( + IN UINTN CpIndex + ); + +// // I2C // typedef struct { diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c index 6ce6bad..7184ab6 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c @@ -61,6 +61,17 @@ ArmadaSoCDescComPhyGet ( return EFI_SUCCESS; } +EFI_PHYSICAL_ADDRESS +EFIAPI +ArmadaSoCDescCpBaseGet ( + IN UINTN CpIndex + ) +{ + ASSERT (CpIndex < FixedPcdGet8 (PcdMaxCpCount)); + + return MV_SOC_CP_BASE (CpIndex); +} + EFI_STATUS EFIAPI ArmadaSoCDescI2cGet ( -- 2.7.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [platforms: PATCH v2 4/6] Marvell/Library: Armada7k8kSoCDescLib: Introduce ICU information 2018-07-13 8:12 [platforms: PATCH v2 0/6] Armada7k8k ICU support Marcin Wojtas ` (2 preceding siblings ...) 2018-07-13 8:12 ` [platforms: PATCH v2 3/6] Marvell/Library: Armada7k8kSoCDescLib: Enable getting CP base address Marcin Wojtas @ 2018-07-13 8:12 ` Marcin Wojtas 2018-07-13 8:12 ` [platforms: PATCH v2 5/6] Marvell/Library: Implement common ArmadaIcuLib Marcin Wojtas ` (2 subsequent siblings) 6 siblings, 0 replies; 10+ messages in thread From: Marcin Wojtas @ 2018-07-13 8:12 UTC (permalink / raw) To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, hannah, mw, jsd, jaz This patch introduces new library callback (ArmadaSoCDescIcuGet ()), which dynamically allocates and fills MV_SOC_ICU_DESC structure with the SoC description of ICU (Interrupt Consolidation Unit). Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> --- Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 12 ++++++ Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 30 +++++++++++++++ Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 39 ++++++++++++++++++++ 3 files changed, 81 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h index 3072883..c14b985 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h @@ -44,6 +44,18 @@ #define MV_SOC_I2C_BASE(I2c) (0x701000 + ((I2c) * 0x100)) // +// Platform description of ICU (Interrupt Consolidation Unit) controllers +// +#define ICU_GIC_MAPPING_OFFSET 0 +#define ICU_NSR_SET_SPI_BASE 0xf03f0040 +#define ICU_NSR_CLEAR_SPI_BASE 0xf03f0048 +#define ICU_SEI_SET_SPI_BASE 0xf03f0230 +#define ICU_SEI_CLEAR_SPI_BASE 0xf03f0230 +#define ICU_REI_SET_SPI_BASE 0xf03f0270 +#define ICU_REI_CLEAR_SPI_BASE 0xf03f0270 +#define ICU_GROUP_UNSUPPORTED 0x0 + +// // Platform description of MDIO controllers // #define MV_SOC_MDIO_BASE(Cp) (MV_SOC_CP_BASE (Cp) + 0x12A200) diff --git a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h index 30e6378..cdfb51b 100644 --- a/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h +++ b/Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h @@ -61,6 +61,36 @@ ArmadaSoCDescI2cGet ( ); // +// ICU (Interrupt Consolidation Unit) +// +typedef enum { + IcuGroupNsr = 0, + IcuGroupSr = 1, + IcuGroupLpi = 2, + IcuGroupVlpi = 3, + IcuGroupSei = 4, + IcuGroupRei = 5, + IcuGroupMax, +} ICU_GROUP; + +typedef struct { + ICU_GROUP Group; + UINTN SetSpiAddr; + UINTN ClrSpiAddr; +} ICU_MSI; + +typedef struct { + UINTN IcuSpiBase; + ICU_MSI IcuMsi[IcuGroupMax]; +} MV_SOC_ICU_DESC; + +EFI_STATUS +EFIAPI +ArmadaSoCDescIcuGet ( + IN OUT MV_SOC_ICU_DESC **IcuDesc + ); + +// // MDIO // typedef struct { diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c index 7184ab6..6902fda 100644 --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c @@ -103,6 +103,45 @@ ArmadaSoCDescI2cGet ( return EFI_SUCCESS; } +// +// Allocate the MSI address per interrupt Group, +// unsupported Groups get NULL address. +// +STATIC +MV_SOC_ICU_DESC mA7k8kIcuDescTemplate = { + ICU_GIC_MAPPING_OFFSET, + { + /* Non secure interrupts */ + { IcuGroupNsr, ICU_NSR_SET_SPI_BASE, ICU_NSR_CLEAR_SPI_BASE }, + /* Secure interrupts */ + { IcuGroupSr, ICU_GROUP_UNSUPPORTED, ICU_GROUP_UNSUPPORTED }, + /* LPI interrupts */ + { IcuGroupLpi, ICU_GROUP_UNSUPPORTED, ICU_GROUP_UNSUPPORTED }, + /* Virtual LPI interrupts */ + { IcuGroupVlpi, ICU_GROUP_UNSUPPORTED, ICU_GROUP_UNSUPPORTED }, + /* System error interrupts */ + { IcuGroupSei, ICU_SEI_SET_SPI_BASE, ICU_SEI_CLEAR_SPI_BASE }, + /* RAM error interrupts */ + { IcuGroupRei, ICU_REI_SET_SPI_BASE, ICU_REI_CLEAR_SPI_BASE }, + } +}; + +EFI_STATUS +EFIAPI +ArmadaSoCDescIcuGet ( + IN OUT MV_SOC_ICU_DESC **IcuDesc + ) +{ + *IcuDesc = AllocateCopyPool (sizeof (mA7k8kIcuDescTemplate), + &mA7k8kIcuDescTemplate); + if (*IcuDesc == NULL) { + DEBUG ((DEBUG_ERROR, "%a: Cannot allocate memory\n", __FUNCTION__)); + return EFI_OUT_OF_RESOURCES; + } + + return EFI_SUCCESS; +} + EFI_STATUS EFIAPI ArmadaSoCDescMdioGet ( -- 2.7.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [platforms: PATCH v2 5/6] Marvell/Library: Implement common ArmadaIcuLib 2018-07-13 8:12 [platforms: PATCH v2 0/6] Armada7k8k ICU support Marcin Wojtas ` (3 preceding siblings ...) 2018-07-13 8:12 ` [platforms: PATCH v2 4/6] Marvell/Library: Armada7k8kSoCDescLib: Introduce ICU information Marcin Wojtas @ 2018-07-13 8:12 ` Marcin Wojtas 2018-07-13 8:44 ` Leif Lindholm 2018-07-13 8:12 ` [platforms: PATCH v2 6/6] Marvell/Armada7k8k: Enable ICU configuration Marcin Wojtas 2018-07-25 9:33 ` [platforms: PATCH v2 0/6] Armada7k8k ICU support Ard Biesheuvel 6 siblings, 1 reply; 10+ messages in thread From: Marcin Wojtas @ 2018-07-13 8:12 UTC (permalink / raw) To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, hannah, mw, jsd, jaz ICU (Interrupt Consolidation Unit) is a mechanism, that allows to send-message based interrupts from the CP110 unit (South Bridge) to the Application Processor hardware block. After dispatching the interrupts in the GIC are generated. This patch adds a basic version of the library, that allows to configure a static mapping between CP110 interfaces and GICv2 of the Armada7k8k SoC family. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> --- Silicon/Marvell/Library/IcuLib/IcuLib.inf | 38 +++ Silicon/Marvell/Library/IcuLib/IcuLib.h | 47 +++ Silicon/Marvell/Library/IcuLib/IcuLib.c | 317 ++++++++++++++++++++ 3 files changed, 402 insertions(+) create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.inf create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.h create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.c diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.inf b/Silicon/Marvell/Library/IcuLib/IcuLib.inf new file mode 100644 index 0000000..0010141 --- /dev/null +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.inf @@ -0,0 +1,38 @@ +## @file +# +# Copyright (C) 2018, Marvell International Ltd. and its affiliates<BR> +# +# This program and the accompanying materials are licensed and made available +# under the terms and conditions of the BSD License which accompanies this +# distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR +# IMPLIED. +# +## + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = IcuLib + FILE_GUID = 0301c9cb-43e6-40a8-96bf-41bd0501e86d + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = ArmadaIcuLib + +[Sources] + IcuLib.c + +[Packages] + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Marvell/Marvell.dec + +[LibraryClasses] + ArmadaSoCDescLib + DebugLib + IoLib + PcdLib + +[FixedPcd] + gMarvellTokenSpaceGuid.PcdMaxCpCount diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.h b/Silicon/Marvell/Library/IcuLib/IcuLib.h new file mode 100644 index 0000000..fba1115 --- /dev/null +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.h @@ -0,0 +1,47 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Glossary - abbreviations used in Marvell SampleAtReset library implementation: +* ICU - Interrupt Consolidation Unit +* AP - Application Processor hardware block (Armada 7k8k incorporates AP806) +* CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) +* +**/ + +#include <Uefi.h> + +#include <Library/ArmadaIcuLib.h> +#include <Library/ArmadaSoCDescLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/IoLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/PcdLib.h> +#include <Library/UefiBootServicesTableLib.h> + +#define ICU_REG_BASE(Cp) ArmadaSoCDescCpBaseGet (CpIndex) + 0x1E0000 + +#define ICU_GROUP_REGISTER_BASE_OFFSET 0x10 +#define ICU_SET_SPI_AL(x) (0x10 + (ICU_GROUP_REGISTER_BASE_OFFSET * x)) +#define ICU_SET_SPI_AH(x) (0x14 + (ICU_GROUP_REGISTER_BASE_OFFSET * x)) +#define ICU_CLR_SPI_AL(x) (0x18 + (ICU_GROUP_REGISTER_BASE_OFFSET * x)) +#define ICU_CLR_SPI_AH(x) (0x1c + (ICU_GROUP_REGISTER_BASE_OFFSET * x)) +#define ICU_INT_CFG(x) (0x100 + (sizeof (UINT32) * x)) + +#define ICU_INT_ENABLE_OFFSET 24 +#define ICU_IS_EDGE_OFFSET 28 +#define ICU_GROUP_OFFSET 29 + +#define ICU_MAX_SUPPORTED_UNITS 2 +#define ICU_MAX_IRQS_PER_CP 64 + +#define MAX_ICU_IRQS 207 diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.c b/Silicon/Marvell/Library/IcuLib/IcuLib.c new file mode 100644 index 0000000..e88337c --- /dev/null +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.c @@ -0,0 +1,317 @@ +/** +* +* Copyright (C) 2018, Marvell International Ltd. and its affiliates. +* +* This program and the accompanying materials are licensed and made available +* under the terms and conditions of the BSD License which accompanies this +* distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +* Glossary - abbreviations used in Marvell SampleAtReset library implementation: +* ICU - Interrupt Consolidation Unit +* AP - Application Processor hardware block (Armada 7k8k incorporates AP806) +* CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) +* +**/ + +#include "IcuLib.h" + +STATIC EFI_EVENT mEfiExitBootServicesEvent; + +STATIC CONST ICU_IRQ IrqMapNonSecure[] = { + {22, 0, IcuIrqTypeLevel}, /* PCIx4 INT A interrupt */ + {23, 1, IcuIrqTypeLevel}, /* PCIx1 INT A interrupt */ + {24, 2, IcuIrqTypeLevel}, /* PCIx1 INT A interrupt */ + {27, 3, IcuIrqTypeLevel}, /* SD/MMC */ + {33, 4, IcuIrqTypeLevel}, /* PPv2 DBG AXI monitor */ + {34, 4, IcuIrqTypeLevel}, /* HB1 AXI monitor */ + {35, 4, IcuIrqTypeLevel}, /* AP AXI monitor */ + {36, 4, IcuIrqTypeLevel}, /* PPv2 AXI monitor */ + {39, 5, IcuIrqTypeLevel}, /* PPv2 Irq */ + {40, 6, IcuIrqTypeLevel}, /* PPv2 Irq */ + {41, 7, IcuIrqTypeLevel}, /* PPv2 Irq */ + {43, 8, IcuIrqTypeLevel}, /* PPv2 Irq */ + {44, 9, IcuIrqTypeLevel}, /* PPv2 Irq */ + {45, 10, IcuIrqTypeLevel}, /* PPv2 Irq */ + {47, 11, IcuIrqTypeLevel}, /* PPv2 Irq */ + {48, 12, IcuIrqTypeLevel}, /* PPv2 Irq */ + {49, 13, IcuIrqTypeLevel}, /* PPv2 Irq */ + {51, 14, IcuIrqTypeLevel}, /* PPv2 Irq */ + {52, 15, IcuIrqTypeLevel}, /* PPv2 Irq */ + {53, 16, IcuIrqTypeLevel}, /* PPv2 Irq */ + {55, 17, IcuIrqTypeLevel}, /* PPv2 Irq */ + {56, 18, IcuIrqTypeLevel}, /* PPv2 Irq */ + {57, 19, IcuIrqTypeLevel}, /* PPv2 Irq */ + {59, 20, IcuIrqTypeLevel}, /* PPv2 Irq */ + {60, 21, IcuIrqTypeLevel}, /* PPv2 Irq */ + {61, 22, IcuIrqTypeLevel}, /* PPv2 Irq */ + {63, 23, IcuIrqTypeLevel}, /* PPv2 Irq */ + {64, 24, IcuIrqTypeLevel}, /* PPv2 Irq */ + {65, 25, IcuIrqTypeLevel}, /* PPv2 Irq */ + {67, 26, IcuIrqTypeLevel}, /* PPv2 Irq */ + {68, 27, IcuIrqTypeLevel}, /* PPv2 Irq */ + {69, 28, IcuIrqTypeLevel}, /* PPv2 Irq */ + {71, 29, IcuIrqTypeLevel}, /* PPv2 Irq */ + {72, 30, IcuIrqTypeLevel}, /* PPv2 Irq */ + {73, 31, IcuIrqTypeLevel}, /* PPv2 Irq */ + {78, 32, IcuIrqTypeLevel}, /* MG Irq */ + {79, 33, IcuIrqTypeLevel}, /* GPIO 56-63 */ + {80, 34, IcuIrqTypeLevel}, /* GPIO 48-55 */ + {81, 35, IcuIrqTypeLevel}, /* GPIO 40-47 */ + {82, 36, IcuIrqTypeLevel}, /* GPIO 32-39 */ + {83, 37, IcuIrqTypeLevel}, /* GPIO 24-31 */ + {84, 38, IcuIrqTypeLevel}, /* GPIO 16-23 */ + {85, 39, IcuIrqTypeLevel}, /* GPIO 8-15 */ + {86, 40, IcuIrqTypeLevel}, /* GPIO 0-7 */ + {88, 41, IcuIrqTypeLevel}, /* EIP-197 ring-0 */ + {89, 42, IcuIrqTypeLevel}, /* EIP-197 ring-1 */ + {90, 43, IcuIrqTypeLevel}, /* EIP-197 ring-2 */ + {91, 44, IcuIrqTypeLevel}, /* EIP-197 ring-3 */ + {92, 45, IcuIrqTypeLevel}, /* EIP-197 int */ + {95, 46, IcuIrqTypeLevel}, /* EIP-150 Irq */ + {102, 47, IcuIrqTypeLevel}, /* USB3 Device Irq */ + {105, 48, IcuIrqTypeLevel}, /* USB3 Host-1 Irq */ + {106, 49, IcuIrqTypeLevel}, /* USB3 Host-0 Irq */ + {107, 50, IcuIrqTypeLevel}, /* SATA Host-1 Irq */ + {109, 50, IcuIrqTypeLevel}, /* SATA Host-0 Irq */ + {115, 52, IcuIrqTypeLevel}, /* NAND Irq */ + {117, 53, IcuIrqTypeLevel}, /* SPI-1 Irq */ + {118, 54, IcuIrqTypeLevel}, /* SPI-0 Irq */ + {120, 55, IcuIrqTypeLevel}, /* I2C 0 Irq */ + {121, 56, IcuIrqTypeLevel}, /* I2C 1 Irq */ + {122, 57, IcuIrqTypeLevel}, /* UART 0 Irq */ + {123, 58, IcuIrqTypeLevel}, /* UART 1 Irq */ + {124, 59, IcuIrqTypeLevel}, /* UART 2 Irq */ + {125, 60, IcuIrqTypeLevel}, /* UART 3 Irq */ + {127, 61, IcuIrqTypeLevel}, /* GOP-3 Irq */ + {128, 62, IcuIrqTypeLevel}, /* GOP-2 Irq */ + {129, 63, IcuIrqTypeLevel}, /* GOP-0 Irq */ +}; + +/* + * SEI - System Error Interrupts + * Note: SPI ID 0-20 are reserved for North-Bridge + */ +STATIC ICU_IRQ IrqMapSei[] = { + {11, 21, IcuIrqTypeLevel}, /* SEI error CP-2-CP */ + {15, 22, IcuIrqTypeLevel}, /* PIDI-64 SOC */ + {16, 23, IcuIrqTypeLevel}, /* D2D error Irq */ + {17, 24, IcuIrqTypeLevel}, /* D2D Irq */ + {18, 25, IcuIrqTypeLevel}, /* NAND error */ + {19, 26, IcuIrqTypeLevel}, /* PCIx4 error */ + {20, 27, IcuIrqTypeLevel}, /* PCIx1_0 error */ + {21, 28, IcuIrqTypeLevel}, /* PCIx1_1 error */ + {25, 29, IcuIrqTypeLevel}, /* SDIO reg error */ + {75, 30, IcuIrqTypeLevel}, /* IOB error */ + {94, 31, IcuIrqTypeLevel}, /* EIP150 error */ + {97, 32, IcuIrqTypeLevel}, /* XOR-1 system error */ + {99, 33, IcuIrqTypeLevel}, /* XOR-0 system error */ + {108, 34, IcuIrqTypeLevel}, /* SATA-1 error */ + {110, 35, IcuIrqTypeLevel}, /* SATA-0 error */ + {114, 36, IcuIrqTypeLevel}, /* TDM-MC error */ + {116, 37, IcuIrqTypeLevel}, /* DFX server Irq */ + {117, 38, IcuIrqTypeLevel}, /* Device bus error */ + {147, 39, IcuIrqTypeLevel}, /* Audio error */ + {171, 40, IcuIrqTypeLevel}, /* PIDI Sync error */ +}; + +/* REI - RAM Error Interrupts */ +STATIC CONST ICU_IRQ IrqMapRei[] = { + {12, 0, IcuIrqTypeLevel}, /* REI error CP-2-CP */ + {26, 1, IcuIrqTypeLevel}, /* SDIO memory error */ + {87, 2, IcuIrqTypeLevel}, /* EIP-197 ECC error */ + {93, 3, IcuIrqTypeEdge}, /* EIP-150 RAM error */ + {96, 4, IcuIrqTypeLevel}, /* XOR-1 memory Irq */ + {98, 5, IcuIrqTypeLevel}, /* XOR-0 memory Irq */ + {100, 6, IcuIrqTypeEdge}, /* USB3 device tx parity */ + {101, 7, IcuIrqTypeEdge}, /* USB3 device rq parity */ + {103, 8, IcuIrqTypeEdge}, /* USB3H-1 RAM error */ + {104, 9, IcuIrqTypeEdge}, /* USB3H-0 RAM error */ +}; + +STATIC CONST ICU_CONFIG IcuInitialConfig = { + .NonSecure = { IrqMapNonSecure, ARRAY_SIZE (IrqMapNonSecure) }, + .Sei = { IrqMapSei, ARRAY_SIZE (IrqMapSei) }, + .Rei = { IrqMapRei, ARRAY_SIZE (IrqMapRei) }, +}; + +STATIC +VOID +IcuClearIrq ( + IN UINTN IcuBase, + IN UINTN Nr +) +{ + MmioWrite32 (IcuBase + ICU_INT_CFG (Nr), 0); +} + +STATIC +VOID +IcuSetIrq ( + IN UINTN IcuBase, + IN CONST ICU_IRQ *Irq, + IN UINTN SpiBase, + IN ICU_GROUP Group + ) +{ + UINT32 IcuInt; + + IcuInt = (Irq->SpiId + SpiBase) | (1 << ICU_INT_ENABLE_OFFSET); + IcuInt |= Irq->IrqType << ICU_IS_EDGE_OFFSET; + IcuInt |= Group << ICU_GROUP_OFFSET; + + MmioWrite32 (IcuBase + ICU_INT_CFG (Irq->IcuId), IcuInt); +} + +STATIC +VOID +IcuConfigure ( + IN UINTN CpIndex, + IN MV_SOC_ICU_DESC *IcuDesc, + IN CONST ICU_CONFIG *Config + ) +{ + UINTN IcuBase, Index, SpiOffset, SpiBase; + CONST ICU_IRQ *Irq; + ICU_MSI *Msi; + + /* Get ICU registers base address */ + IcuBase = ICU_REG_BASE (CpIndex); + /* Get the base of the GIC SPI ID in the MSI message */ + SpiBase = IcuDesc->IcuSpiBase; + /* Get multiple CP110 instances SPI ID shift */ + SpiOffset = CpIndex * ICU_MAX_IRQS_PER_CP; + /* Get MSI addresses per interrupt group */ + Msi = IcuDesc->IcuMsi; + + /* Set the address for SET_SPI and CLR_SPI registers in AP */ + for (Index = 0; Index < IcuGroupMax; Index++, Msi++) { + MmioWrite32 (IcuBase + ICU_SET_SPI_AL (Msi->Group), + Msi->SetSpiAddr & 0xFFFFFFFF); + MmioWrite32 (IcuBase + ICU_SET_SPI_AH (Msi->Group), Msi->SetSpiAddr >> 32); + MmioWrite32 (IcuBase + ICU_CLR_SPI_AL (Msi->Group), + Msi->ClrSpiAddr & 0xFFFFFFFF); + MmioWrite32 (IcuBase + ICU_CLR_SPI_AH (Msi->Group), Msi->ClrSpiAddr >> 32); + } + + /* Mask all ICU interrupts */ + for (Index = 0; Index < MAX_ICU_IRQS; Index++) { + IcuClearIrq (IcuBase, Index); + } + + /* Configure the ICU interrupt lines */ + Irq = Config->NonSecure.Map; + for (Index = 0; Index < Config->NonSecure.Size; Index++, Irq++) { + IcuSetIrq (IcuBase, Irq, SpiBase + SpiOffset, IcuGroupNsr); + } + + Irq = Config->Sei.Map; + for (Index = 0; Index < Config->Sei.Size; Index++, Irq++) { + IcuSetIrq (IcuBase, Irq, SpiBase, IcuGroupSei); + } + + Irq = Config->Rei.Map; + for (Index = 0; Index < Config->Rei.Size; Index++, Irq++) { + IcuSetIrq (IcuBase, Irq, SpiBase, IcuGroupRei); + } +} + +STATIC +VOID +IcuClearGicSpi ( + IN UINTN CpIndex, + IN MV_SOC_ICU_DESC *IcuDesc + ) +{ + CONST ICU_CONFIG *Config; + UINTN Index, SpiOffset, SpiBase; + CONST ICU_IRQ *Irq; + ICU_MSI *Msi; + + Config = &IcuInitialConfig; + + /* Get the base of the GIC SPI ID in the MSI message */ + SpiBase = IcuDesc->IcuSpiBase; + /* Get multiple CP110 instances SPI ID shift */ + SpiOffset = CpIndex * ICU_MAX_IRQS_PER_CP; + /* Get MSI addresses per interrupt group */ + Msi = IcuDesc->IcuMsi; + + /* Clear ICU-generated GIC SPI interrupts */ + Irq = Config->NonSecure.Map; + for (Index = 0; Index < Config->NonSecure.Size; Index++, Irq++) { + MmioWrite32 (Msi->ClrSpiAddr, Irq->SpiId + SpiBase + SpiOffset); + } +} + +VOID +EFIAPI +IcuCleanUp ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + MV_SOC_ICU_DESC *IcuDesc; + UINTN CpCount, CpIndex; + + IcuDesc = Context; + + CpCount = FixedPcdGet8 (PcdMaxCpCount); + if (CpCount > ICU_MAX_SUPPORTED_UNITS) { + CpCount = ICU_MAX_SUPPORTED_UNITS; + } + + for (CpIndex = 0; CpIndex < CpCount; CpIndex++) { + IcuClearGicSpi (CpIndex, IcuDesc); + } +} + +EFI_STATUS +EFIAPI +ArmadaIcuInitialize ( + ) +{ + MV_SOC_ICU_DESC *IcuDesc; + UINTN CpCount, CpIndex; + EFI_STATUS Status; + + /* + * Due to limited amount of interrupt lanes, only 2 units can be + * wired to the GIC. + */ + CpCount = FixedPcdGet8 (PcdMaxCpCount); + if (CpCount > ICU_MAX_SUPPORTED_UNITS) { + DEBUG ((DEBUG_ERROR, + "%a: Default ICU to GIC mapping is available for maximum %d CP110 units", + ICU_MAX_SUPPORTED_UNITS, + __FUNCTION__)); + CpCount = ICU_MAX_SUPPORTED_UNITS; + } + + /* Obtain SoC description of the ICU */ + Status = ArmadaSoCDescIcuGet (&IcuDesc); + if (EFI_ERROR (Status)) { + return Status; + } + + /* Configure default ICU to GIC interrupt mapping for each CP110 */ + for (CpIndex = 0; CpIndex < CpCount; CpIndex++) { + IcuConfigure (CpIndex, IcuDesc, &IcuInitialConfig); + } + + /* + * In order to be immune to the OS capability of clearing ICU-generated + * GIC interrupts, register ExitBootServices event, that will + * make sure they remain disabled during OS boot. + */ + Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, + TPL_NOTIFY, + IcuCleanUp, + IcuDesc, + &mEfiExitBootServicesEvent); + + return Status; +} -- 2.7.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [platforms: PATCH v2 5/6] Marvell/Library: Implement common ArmadaIcuLib 2018-07-13 8:12 ` [platforms: PATCH v2 5/6] Marvell/Library: Implement common ArmadaIcuLib Marcin Wojtas @ 2018-07-13 8:44 ` Leif Lindholm 0 siblings, 0 replies; 10+ messages in thread From: Leif Lindholm @ 2018-07-13 8:44 UTC (permalink / raw) To: Marcin Wojtas; +Cc: edk2-devel, ard.biesheuvel, nadavh, hannah, jsd, jaz On Fri, Jul 13, 2018 at 10:12:12AM +0200, Marcin Wojtas wrote: > ICU (Interrupt Consolidation Unit) is a mechanism, > that allows to send-message based interrupts from the > CP110 unit (South Bridge) to the Application Processor > hardware block. After dispatching the interrupts in the > GIC are generated. > > This patch adds a basic version of the library, that > allows to configure a static mapping between CP110 > interfaces and GICv2 of the Armada7k8k SoC family. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas <mw@semihalf.com> > --- > Silicon/Marvell/Library/IcuLib/IcuLib.inf | 38 +++ > Silicon/Marvell/Library/IcuLib/IcuLib.h | 47 +++ > Silicon/Marvell/Library/IcuLib/IcuLib.c | 317 ++++++++++++++++++++ > 3 files changed, 402 insertions(+) > create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.inf > create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.h > create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.c > > diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.inf b/Silicon/Marvell/Library/IcuLib/IcuLib.inf > new file mode 100644 > index 0000000..0010141 > --- /dev/null > +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.inf > @@ -0,0 +1,38 @@ > +## @file > +# > +# Copyright (C) 2018, Marvell International Ltd. and its affiliates<BR> > +# > +# This program and the accompanying materials are licensed and made available > +# under the terms and conditions of the BSD License which accompanies this > +# distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR > +# IMPLIED. > +# > +## > + > +[Defines] > + INF_VERSION = 0x0001001A > + BASE_NAME = IcuLib > + FILE_GUID = 0301c9cb-43e6-40a8-96bf-41bd0501e86d > + MODULE_TYPE = BASE > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = ArmadaIcuLib > + > +[Sources] > + IcuLib.c > + > +[Packages] > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + Silicon/Marvell/Marvell.dec > + > +[LibraryClasses] > + ArmadaSoCDescLib > + DebugLib > + IoLib > + PcdLib > + > +[FixedPcd] > + gMarvellTokenSpaceGuid.PcdMaxCpCount > diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.h b/Silicon/Marvell/Library/IcuLib/IcuLib.h > new file mode 100644 > index 0000000..fba1115 > --- /dev/null > +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.h > @@ -0,0 +1,47 @@ > +/** > +* > +* Copyright (C) 2018, Marvell International Ltd. and its affiliates. > +* > +* This program and the accompanying materials are licensed and made available > +* under the terms and conditions of the BSD License which accompanies this > +* distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +* Glossary - abbreviations used in Marvell SampleAtReset library implementation: > +* ICU - Interrupt Consolidation Unit > +* AP - Application Processor hardware block (Armada 7k8k incorporates AP806) > +* CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) > +* > +**/ > + > +#include <Uefi.h> > + > +#include <Library/ArmadaIcuLib.h> > +#include <Library/ArmadaSoCDescLib.h> > +#include <Library/BaseMemoryLib.h> > +#include <Library/DebugLib.h> > +#include <Library/IoLib.h> > +#include <Library/MemoryAllocationLib.h> > +#include <Library/PcdLib.h> > +#include <Library/UefiBootServicesTableLib.h> > + > +#define ICU_REG_BASE(Cp) ArmadaSoCDescCpBaseGet (CpIndex) + 0x1E0000 This macro is still missing parentheses. Please resend this individual patch. / Leif > + > +#define ICU_GROUP_REGISTER_BASE_OFFSET 0x10 > +#define ICU_SET_SPI_AL(x) (0x10 + (ICU_GROUP_REGISTER_BASE_OFFSET * x)) > +#define ICU_SET_SPI_AH(x) (0x14 + (ICU_GROUP_REGISTER_BASE_OFFSET * x)) > +#define ICU_CLR_SPI_AL(x) (0x18 + (ICU_GROUP_REGISTER_BASE_OFFSET * x)) > +#define ICU_CLR_SPI_AH(x) (0x1c + (ICU_GROUP_REGISTER_BASE_OFFSET * x)) > +#define ICU_INT_CFG(x) (0x100 + (sizeof (UINT32) * x)) > + > +#define ICU_INT_ENABLE_OFFSET 24 > +#define ICU_IS_EDGE_OFFSET 28 > +#define ICU_GROUP_OFFSET 29 > + > +#define ICU_MAX_SUPPORTED_UNITS 2 > +#define ICU_MAX_IRQS_PER_CP 64 > + > +#define MAX_ICU_IRQS 207 > diff --git a/Silicon/Marvell/Library/IcuLib/IcuLib.c b/Silicon/Marvell/Library/IcuLib/IcuLib.c > new file mode 100644 > index 0000000..e88337c > --- /dev/null > +++ b/Silicon/Marvell/Library/IcuLib/IcuLib.c > @@ -0,0 +1,317 @@ > +/** > +* > +* Copyright (C) 2018, Marvell International Ltd. and its affiliates. > +* > +* This program and the accompanying materials are licensed and made available > +* under the terms and conditions of the BSD License which accompanies this > +* distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +* Glossary - abbreviations used in Marvell SampleAtReset library implementation: > +* ICU - Interrupt Consolidation Unit > +* AP - Application Processor hardware block (Armada 7k8k incorporates AP806) > +* CP - South Bridge hardware blocks (Armada 7k8k incorporates CP110) > +* > +**/ > + > +#include "IcuLib.h" > + > +STATIC EFI_EVENT mEfiExitBootServicesEvent; > + > +STATIC CONST ICU_IRQ IrqMapNonSecure[] = { > + {22, 0, IcuIrqTypeLevel}, /* PCIx4 INT A interrupt */ > + {23, 1, IcuIrqTypeLevel}, /* PCIx1 INT A interrupt */ > + {24, 2, IcuIrqTypeLevel}, /* PCIx1 INT A interrupt */ > + {27, 3, IcuIrqTypeLevel}, /* SD/MMC */ > + {33, 4, IcuIrqTypeLevel}, /* PPv2 DBG AXI monitor */ > + {34, 4, IcuIrqTypeLevel}, /* HB1 AXI monitor */ > + {35, 4, IcuIrqTypeLevel}, /* AP AXI monitor */ > + {36, 4, IcuIrqTypeLevel}, /* PPv2 AXI monitor */ > + {39, 5, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {40, 6, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {41, 7, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {43, 8, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {44, 9, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {45, 10, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {47, 11, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {48, 12, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {49, 13, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {51, 14, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {52, 15, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {53, 16, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {55, 17, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {56, 18, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {57, 19, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {59, 20, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {60, 21, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {61, 22, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {63, 23, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {64, 24, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {65, 25, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {67, 26, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {68, 27, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {69, 28, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {71, 29, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {72, 30, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {73, 31, IcuIrqTypeLevel}, /* PPv2 Irq */ > + {78, 32, IcuIrqTypeLevel}, /* MG Irq */ > + {79, 33, IcuIrqTypeLevel}, /* GPIO 56-63 */ > + {80, 34, IcuIrqTypeLevel}, /* GPIO 48-55 */ > + {81, 35, IcuIrqTypeLevel}, /* GPIO 40-47 */ > + {82, 36, IcuIrqTypeLevel}, /* GPIO 32-39 */ > + {83, 37, IcuIrqTypeLevel}, /* GPIO 24-31 */ > + {84, 38, IcuIrqTypeLevel}, /* GPIO 16-23 */ > + {85, 39, IcuIrqTypeLevel}, /* GPIO 8-15 */ > + {86, 40, IcuIrqTypeLevel}, /* GPIO 0-7 */ > + {88, 41, IcuIrqTypeLevel}, /* EIP-197 ring-0 */ > + {89, 42, IcuIrqTypeLevel}, /* EIP-197 ring-1 */ > + {90, 43, IcuIrqTypeLevel}, /* EIP-197 ring-2 */ > + {91, 44, IcuIrqTypeLevel}, /* EIP-197 ring-3 */ > + {92, 45, IcuIrqTypeLevel}, /* EIP-197 int */ > + {95, 46, IcuIrqTypeLevel}, /* EIP-150 Irq */ > + {102, 47, IcuIrqTypeLevel}, /* USB3 Device Irq */ > + {105, 48, IcuIrqTypeLevel}, /* USB3 Host-1 Irq */ > + {106, 49, IcuIrqTypeLevel}, /* USB3 Host-0 Irq */ > + {107, 50, IcuIrqTypeLevel}, /* SATA Host-1 Irq */ > + {109, 50, IcuIrqTypeLevel}, /* SATA Host-0 Irq */ > + {115, 52, IcuIrqTypeLevel}, /* NAND Irq */ > + {117, 53, IcuIrqTypeLevel}, /* SPI-1 Irq */ > + {118, 54, IcuIrqTypeLevel}, /* SPI-0 Irq */ > + {120, 55, IcuIrqTypeLevel}, /* I2C 0 Irq */ > + {121, 56, IcuIrqTypeLevel}, /* I2C 1 Irq */ > + {122, 57, IcuIrqTypeLevel}, /* UART 0 Irq */ > + {123, 58, IcuIrqTypeLevel}, /* UART 1 Irq */ > + {124, 59, IcuIrqTypeLevel}, /* UART 2 Irq */ > + {125, 60, IcuIrqTypeLevel}, /* UART 3 Irq */ > + {127, 61, IcuIrqTypeLevel}, /* GOP-3 Irq */ > + {128, 62, IcuIrqTypeLevel}, /* GOP-2 Irq */ > + {129, 63, IcuIrqTypeLevel}, /* GOP-0 Irq */ > +}; > + > +/* > + * SEI - System Error Interrupts > + * Note: SPI ID 0-20 are reserved for North-Bridge > + */ > +STATIC ICU_IRQ IrqMapSei[] = { > + {11, 21, IcuIrqTypeLevel}, /* SEI error CP-2-CP */ > + {15, 22, IcuIrqTypeLevel}, /* PIDI-64 SOC */ > + {16, 23, IcuIrqTypeLevel}, /* D2D error Irq */ > + {17, 24, IcuIrqTypeLevel}, /* D2D Irq */ > + {18, 25, IcuIrqTypeLevel}, /* NAND error */ > + {19, 26, IcuIrqTypeLevel}, /* PCIx4 error */ > + {20, 27, IcuIrqTypeLevel}, /* PCIx1_0 error */ > + {21, 28, IcuIrqTypeLevel}, /* PCIx1_1 error */ > + {25, 29, IcuIrqTypeLevel}, /* SDIO reg error */ > + {75, 30, IcuIrqTypeLevel}, /* IOB error */ > + {94, 31, IcuIrqTypeLevel}, /* EIP150 error */ > + {97, 32, IcuIrqTypeLevel}, /* XOR-1 system error */ > + {99, 33, IcuIrqTypeLevel}, /* XOR-0 system error */ > + {108, 34, IcuIrqTypeLevel}, /* SATA-1 error */ > + {110, 35, IcuIrqTypeLevel}, /* SATA-0 error */ > + {114, 36, IcuIrqTypeLevel}, /* TDM-MC error */ > + {116, 37, IcuIrqTypeLevel}, /* DFX server Irq */ > + {117, 38, IcuIrqTypeLevel}, /* Device bus error */ > + {147, 39, IcuIrqTypeLevel}, /* Audio error */ > + {171, 40, IcuIrqTypeLevel}, /* PIDI Sync error */ > +}; > + > +/* REI - RAM Error Interrupts */ > +STATIC CONST ICU_IRQ IrqMapRei[] = { > + {12, 0, IcuIrqTypeLevel}, /* REI error CP-2-CP */ > + {26, 1, IcuIrqTypeLevel}, /* SDIO memory error */ > + {87, 2, IcuIrqTypeLevel}, /* EIP-197 ECC error */ > + {93, 3, IcuIrqTypeEdge}, /* EIP-150 RAM error */ > + {96, 4, IcuIrqTypeLevel}, /* XOR-1 memory Irq */ > + {98, 5, IcuIrqTypeLevel}, /* XOR-0 memory Irq */ > + {100, 6, IcuIrqTypeEdge}, /* USB3 device tx parity */ > + {101, 7, IcuIrqTypeEdge}, /* USB3 device rq parity */ > + {103, 8, IcuIrqTypeEdge}, /* USB3H-1 RAM error */ > + {104, 9, IcuIrqTypeEdge}, /* USB3H-0 RAM error */ > +}; > + > +STATIC CONST ICU_CONFIG IcuInitialConfig = { > + .NonSecure = { IrqMapNonSecure, ARRAY_SIZE (IrqMapNonSecure) }, > + .Sei = { IrqMapSei, ARRAY_SIZE (IrqMapSei) }, > + .Rei = { IrqMapRei, ARRAY_SIZE (IrqMapRei) }, > +}; > + > +STATIC > +VOID > +IcuClearIrq ( > + IN UINTN IcuBase, > + IN UINTN Nr > +) > +{ > + MmioWrite32 (IcuBase + ICU_INT_CFG (Nr), 0); > +} > + > +STATIC > +VOID > +IcuSetIrq ( > + IN UINTN IcuBase, > + IN CONST ICU_IRQ *Irq, > + IN UINTN SpiBase, > + IN ICU_GROUP Group > + ) > +{ > + UINT32 IcuInt; > + > + IcuInt = (Irq->SpiId + SpiBase) | (1 << ICU_INT_ENABLE_OFFSET); > + IcuInt |= Irq->IrqType << ICU_IS_EDGE_OFFSET; > + IcuInt |= Group << ICU_GROUP_OFFSET; > + > + MmioWrite32 (IcuBase + ICU_INT_CFG (Irq->IcuId), IcuInt); > +} > + > +STATIC > +VOID > +IcuConfigure ( > + IN UINTN CpIndex, > + IN MV_SOC_ICU_DESC *IcuDesc, > + IN CONST ICU_CONFIG *Config > + ) > +{ > + UINTN IcuBase, Index, SpiOffset, SpiBase; > + CONST ICU_IRQ *Irq; > + ICU_MSI *Msi; > + > + /* Get ICU registers base address */ > + IcuBase = ICU_REG_BASE (CpIndex); > + /* Get the base of the GIC SPI ID in the MSI message */ > + SpiBase = IcuDesc->IcuSpiBase; > + /* Get multiple CP110 instances SPI ID shift */ > + SpiOffset = CpIndex * ICU_MAX_IRQS_PER_CP; > + /* Get MSI addresses per interrupt group */ > + Msi = IcuDesc->IcuMsi; > + > + /* Set the address for SET_SPI and CLR_SPI registers in AP */ > + for (Index = 0; Index < IcuGroupMax; Index++, Msi++) { > + MmioWrite32 (IcuBase + ICU_SET_SPI_AL (Msi->Group), > + Msi->SetSpiAddr & 0xFFFFFFFF); > + MmioWrite32 (IcuBase + ICU_SET_SPI_AH (Msi->Group), Msi->SetSpiAddr >> 32); > + MmioWrite32 (IcuBase + ICU_CLR_SPI_AL (Msi->Group), > + Msi->ClrSpiAddr & 0xFFFFFFFF); > + MmioWrite32 (IcuBase + ICU_CLR_SPI_AH (Msi->Group), Msi->ClrSpiAddr >> 32); > + } > + > + /* Mask all ICU interrupts */ > + for (Index = 0; Index < MAX_ICU_IRQS; Index++) { > + IcuClearIrq (IcuBase, Index); > + } > + > + /* Configure the ICU interrupt lines */ > + Irq = Config->NonSecure.Map; > + for (Index = 0; Index < Config->NonSecure.Size; Index++, Irq++) { > + IcuSetIrq (IcuBase, Irq, SpiBase + SpiOffset, IcuGroupNsr); > + } > + > + Irq = Config->Sei.Map; > + for (Index = 0; Index < Config->Sei.Size; Index++, Irq++) { > + IcuSetIrq (IcuBase, Irq, SpiBase, IcuGroupSei); > + } > + > + Irq = Config->Rei.Map; > + for (Index = 0; Index < Config->Rei.Size; Index++, Irq++) { > + IcuSetIrq (IcuBase, Irq, SpiBase, IcuGroupRei); > + } > +} > + > +STATIC > +VOID > +IcuClearGicSpi ( > + IN UINTN CpIndex, > + IN MV_SOC_ICU_DESC *IcuDesc > + ) > +{ > + CONST ICU_CONFIG *Config; > + UINTN Index, SpiOffset, SpiBase; > + CONST ICU_IRQ *Irq; > + ICU_MSI *Msi; > + > + Config = &IcuInitialConfig; > + > + /* Get the base of the GIC SPI ID in the MSI message */ > + SpiBase = IcuDesc->IcuSpiBase; > + /* Get multiple CP110 instances SPI ID shift */ > + SpiOffset = CpIndex * ICU_MAX_IRQS_PER_CP; > + /* Get MSI addresses per interrupt group */ > + Msi = IcuDesc->IcuMsi; > + > + /* Clear ICU-generated GIC SPI interrupts */ > + Irq = Config->NonSecure.Map; > + for (Index = 0; Index < Config->NonSecure.Size; Index++, Irq++) { > + MmioWrite32 (Msi->ClrSpiAddr, Irq->SpiId + SpiBase + SpiOffset); > + } > +} > + > +VOID > +EFIAPI > +IcuCleanUp ( > + IN EFI_EVENT Event, > + IN VOID *Context > + ) > +{ > + MV_SOC_ICU_DESC *IcuDesc; > + UINTN CpCount, CpIndex; > + > + IcuDesc = Context; > + > + CpCount = FixedPcdGet8 (PcdMaxCpCount); > + if (CpCount > ICU_MAX_SUPPORTED_UNITS) { > + CpCount = ICU_MAX_SUPPORTED_UNITS; > + } > + > + for (CpIndex = 0; CpIndex < CpCount; CpIndex++) { > + IcuClearGicSpi (CpIndex, IcuDesc); > + } > +} > + > +EFI_STATUS > +EFIAPI > +ArmadaIcuInitialize ( > + ) > +{ > + MV_SOC_ICU_DESC *IcuDesc; > + UINTN CpCount, CpIndex; > + EFI_STATUS Status; > + > + /* > + * Due to limited amount of interrupt lanes, only 2 units can be > + * wired to the GIC. > + */ > + CpCount = FixedPcdGet8 (PcdMaxCpCount); > + if (CpCount > ICU_MAX_SUPPORTED_UNITS) { > + DEBUG ((DEBUG_ERROR, > + "%a: Default ICU to GIC mapping is available for maximum %d CP110 units", > + ICU_MAX_SUPPORTED_UNITS, > + __FUNCTION__)); > + CpCount = ICU_MAX_SUPPORTED_UNITS; > + } > + > + /* Obtain SoC description of the ICU */ > + Status = ArmadaSoCDescIcuGet (&IcuDesc); > + if (EFI_ERROR (Status)) { > + return Status; > + } > + > + /* Configure default ICU to GIC interrupt mapping for each CP110 */ > + for (CpIndex = 0; CpIndex < CpCount; CpIndex++) { > + IcuConfigure (CpIndex, IcuDesc, &IcuInitialConfig); > + } > + > + /* > + * In order to be immune to the OS capability of clearing ICU-generated > + * GIC interrupts, register ExitBootServices event, that will > + * make sure they remain disabled during OS boot. > + */ > + Status = gBS->CreateEvent (EVT_SIGNAL_EXIT_BOOT_SERVICES, > + TPL_NOTIFY, > + IcuCleanUp, > + IcuDesc, > + &mEfiExitBootServicesEvent); > + > + return Status; > +} > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* [platforms: PATCH v2 6/6] Marvell/Armada7k8k: Enable ICU configuration 2018-07-13 8:12 [platforms: PATCH v2 0/6] Armada7k8k ICU support Marcin Wojtas ` (4 preceding siblings ...) 2018-07-13 8:12 ` [platforms: PATCH v2 5/6] Marvell/Library: Implement common ArmadaIcuLib Marcin Wojtas @ 2018-07-13 8:12 ` Marcin Wojtas 2018-07-25 9:33 ` [platforms: PATCH v2 0/6] Armada7k8k ICU support Ard Biesheuvel 6 siblings, 0 replies; 10+ messages in thread From: Marcin Wojtas @ 2018-07-13 8:12 UTC (permalink / raw) To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, hannah, mw, jsd, jaz This patch enables the ICU (Interrupt Consolidation Unit) configuration in the common platform initialization driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 + Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf | 1 + Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc index a9d67a2..27b14ed 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -32,6 +32,7 @@ #SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # [LibraryClasses.common] + ArmadaIcuLib|Silicon/Marvell/Library/IcuLib/IcuLib.inf ArmadaSoCDescLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.inf ArmPlatformLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf ComPhyLib|Silicon/Marvell/Library/ComPhyLib/ComPhyLib.inf diff --git a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf index 803dc6e..5503463 100644 --- a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf +++ b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf @@ -30,6 +30,7 @@ Silicon/Marvell/Marvell.dec [LibraryClasses] + ArmadaIcuLib ComPhyLib DebugLib MppLib diff --git a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c index 1efad77..18b6783 100644 --- a/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c +++ b/Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c @@ -12,6 +12,7 @@ **/ +#include <Library/ArmadaIcuLib.h> #include <Library/DebugLib.h> #include <Library/MppLib.h> #include <Library/MvComPhyLib.h> @@ -40,6 +41,7 @@ ArmadaPlatInitDxeEntryPoint ( MvComPhyInit (); UtmiPhyInit (); MppInitialize (); + ArmadaIcuInitialize (); return EFI_SUCCESS; } -- 2.7.4 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [platforms: PATCH v2 0/6] Armada7k8k ICU support 2018-07-13 8:12 [platforms: PATCH v2 0/6] Armada7k8k ICU support Marcin Wojtas ` (5 preceding siblings ...) 2018-07-13 8:12 ` [platforms: PATCH v2 6/6] Marvell/Armada7k8k: Enable ICU configuration Marcin Wojtas @ 2018-07-25 9:33 ` Ard Biesheuvel 2018-07-25 9:47 ` Marcin Wojtas 6 siblings, 1 reply; 10+ messages in thread From: Ard Biesheuvel @ 2018-07-25 9:33 UTC (permalink / raw) To: Marcin Wojtas Cc: edk2-devel@lists.01.org, Leif Lindholm, Nadav Haklai, Hanna Hawa, Jan Dąbroś, Grzegorz Jaszczyk On 13 July 2018 at 10:12, Marcin Wojtas <mw@semihalf.com> wrote: > Hi, > > The second version of the ICU patchset brings all corrections > according to all review remarks. They were mostly style / naming > - detailed list can be found in the changelog below. > > The patches are available in the github: > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/icu-upstream-r20180713 > > I'm looking forward to review and any comments/remarks. > > Best regards, > Marcin > > Changelog > v1 -> v2 > * 1,6 > - Add Ard's RB > > * 2 > - Change ICU_IRQ_TYPE to IcuIrqTypeLevel / IcuIrqTypeEdge > > * 3 > - Use EFI_PHYSICAL_ADDRESS > > * 4 > - Put a space after { and before } > - Change enum values to IcuGroupXxx format > > * 5 > - Use ICU_GROUP_REGISTER_BASE_OFFSET instead of a raw value in macros > - Add missing parentheses and use sizeof (UINT32) in ICU_INT_CFG macro > - Use mEfiExitBootServicesEvent - not initialized and STATIC > - s/IcuConfigDefault/IcuInitialConfig/ > - Break to long lines > > Marcin Wojtas (6): > Marvell/Armada70x0Db: Set correct CP110 count > Marvell/Library: Introduce ArmadaIcuLib class > Marvell/Library: Armada7k8kSoCDescLib: Enable getting CP base address > Marvell/Library: Armada7k8kSoCDescLib: Introduce ICU information > Marvell/Library: Implement common ArmadaIcuLib > Marvell/Armada7k8k: Enable ICU configuration > Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Pushed as 80f6be6eb12b..bd325517ba42 (with 5/6 updated to the v3 version) > Silicon/Marvell/Marvell.dec | 1 + > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 + > Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 7 +- > Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf | 1 + > Silicon/Marvell/Library/IcuLib/IcuLib.inf | 38 +++ > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 12 + > Silicon/Marvell/Include/Library/ArmadaIcuLib.h | 45 +++ > Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 39 +++ > Silicon/Marvell/Library/IcuLib/IcuLib.h | 47 +++ > Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c | 2 + > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 50 +++ > Silicon/Marvell/Library/IcuLib/IcuLib.c | 317 ++++++++++++++++++++ > 12 files changed, 558 insertions(+), 2 deletions(-) > create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.inf > create mode 100644 Silicon/Marvell/Include/Library/ArmadaIcuLib.h > create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.h > create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.c > > -- > 2.7.4 > ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [platforms: PATCH v2 0/6] Armada7k8k ICU support 2018-07-25 9:33 ` [platforms: PATCH v2 0/6] Armada7k8k ICU support Ard Biesheuvel @ 2018-07-25 9:47 ` Marcin Wojtas 0 siblings, 0 replies; 10+ messages in thread From: Marcin Wojtas @ 2018-07-25 9:47 UTC (permalink / raw) To: Ard Biesheuvel Cc: edk2-devel@lists.01.org, Leif Lindholm, Nadav Haklai, Hanna Hawa, Jan Dąbroś, Grzegorz Jaszczyk 2018-07-25 11:33 GMT+02:00 Ard Biesheuvel <ard.biesheuvel@linaro.org>: > On 13 July 2018 at 10:12, Marcin Wojtas <mw@semihalf.com> wrote: >> Hi, >> >> The second version of the ICU patchset brings all corrections >> according to all review remarks. They were mostly style / naming >> - detailed list can be found in the changelog below. >> >> The patches are available in the github: >> https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/icu-upstream-r20180713 >> >> I'm looking forward to review and any comments/remarks. >> >> Best regards, >> Marcin >> >> Changelog >> v1 -> v2 >> * 1,6 >> - Add Ard's RB >> >> * 2 >> - Change ICU_IRQ_TYPE to IcuIrqTypeLevel / IcuIrqTypeEdge >> >> * 3 >> - Use EFI_PHYSICAL_ADDRESS >> >> * 4 >> - Put a space after { and before } >> - Change enum values to IcuGroupXxx format >> >> * 5 >> - Use ICU_GROUP_REGISTER_BASE_OFFSET instead of a raw value in macros >> - Add missing parentheses and use sizeof (UINT32) in ICU_INT_CFG macro >> - Use mEfiExitBootServicesEvent - not initialized and STATIC >> - s/IcuConfigDefault/IcuInitialConfig/ >> - Break to long lines >> >> Marcin Wojtas (6): >> Marvell/Armada70x0Db: Set correct CP110 count >> Marvell/Library: Introduce ArmadaIcuLib class >> Marvell/Library: Armada7k8kSoCDescLib: Enable getting CP base address >> Marvell/Library: Armada7k8kSoCDescLib: Introduce ICU information >> Marvell/Library: Implement common ArmadaIcuLib >> Marvell/Armada7k8k: Enable ICU configuration >> > > Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> > > Pushed as 80f6be6eb12b..bd325517ba42 (with 5/6 updated to the v3 version) > Thanks! >> Silicon/Marvell/Marvell.dec | 1 + >> Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 1 + >> Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 7 +- >> Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.inf | 1 + >> Silicon/Marvell/Library/IcuLib/IcuLib.inf | 38 +++ >> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.h | 12 + >> Silicon/Marvell/Include/Library/ArmadaIcuLib.h | 45 +++ >> Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h | 39 +++ >> Silicon/Marvell/Library/IcuLib/IcuLib.h | 47 +++ >> Silicon/Marvell/Armada7k8k/Drivers/PlatInitDxe/PlatInitDxe.c | 2 + >> Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCDescLib.c | 50 +++ >> Silicon/Marvell/Library/IcuLib/IcuLib.c | 317 ++++++++++++++++++++ >> 12 files changed, 558 insertions(+), 2 deletions(-) >> create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.inf >> create mode 100644 Silicon/Marvell/Include/Library/ArmadaIcuLib.h >> create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.h >> create mode 100644 Silicon/Marvell/Library/IcuLib/IcuLib.c >> >> -- >> 2.7.4 >> ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2018-07-25 9:47 UTC | newest] Thread overview: 10+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-07-13 8:12 [platforms: PATCH v2 0/6] Armada7k8k ICU support Marcin Wojtas 2018-07-13 8:12 ` [platforms: PATCH v2 1/6] Marvell/Armada70x0Db: Set correct CP110 count Marcin Wojtas 2018-07-13 8:12 ` [platforms: PATCH v2 2/6] Marvell/Library: Introduce ArmadaIcuLib class Marcin Wojtas 2018-07-13 8:12 ` [platforms: PATCH v2 3/6] Marvell/Library: Armada7k8kSoCDescLib: Enable getting CP base address Marcin Wojtas 2018-07-13 8:12 ` [platforms: PATCH v2 4/6] Marvell/Library: Armada7k8kSoCDescLib: Introduce ICU information Marcin Wojtas 2018-07-13 8:12 ` [platforms: PATCH v2 5/6] Marvell/Library: Implement common ArmadaIcuLib Marcin Wojtas 2018-07-13 8:44 ` Leif Lindholm 2018-07-13 8:12 ` [platforms: PATCH v2 6/6] Marvell/Armada7k8k: Enable ICU configuration Marcin Wojtas 2018-07-25 9:33 ` [platforms: PATCH v2 0/6] Armada7k8k ICU support Ard Biesheuvel 2018-07-25 9:47 ` Marcin Wojtas
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox