From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.20; helo=mga02.intel.com; envelope-from=chao.b.zhang@intel.com; receiver=edk2-devel@lists.01.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C4BA820988476 for ; Mon, 16 Jul 2018 00:20:44 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jul 2018 00:20:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,360,1526367600"; d="scan'208";a="72651827" Received: from czhan46-mobl1.ccr.corp.intel.com ([10.249.169.219]) by fmsmga001.fm.intel.com with ESMTP; 16 Jul 2018 00:20:43 -0700 From: "Zhang, Chao B" To: edk2-devel@lists.01.org Cc: Long Qin , Jiewen Yao , Chao Zhang Date: Mon, 16 Jul 2018 15:20:39 +0800 Message-Id: <20180716072039.27660-1-chao.b.zhang@intel.com> X-Mailer: git-send-email 2.11.0.windows.1 Subject: [Patch] SecurityPkg:Tcg: Fix comment typos X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 16 Jul 2018 07:20:44 -0000 "Triggle" is a typo. Fix it with "Trigger" Cc: Long Qin Cc: Jiewen Yao Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Chao Zhang Signed-off-by: Zhang, Chao B --- SecurityPkg/Tcg/Tcg2Smm/Tpm.asl | 16 ++++++++-------- SecurityPkg/Tcg/TcgSmm/Tpm.asl | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl b/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl index 50dea0ab9a..471b6b1fa1 100644 --- a/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl +++ b/SecurityPkg/Tcg/Tcg2Smm/Tpm.asl @@ -257,16 +257,16 @@ DefinitionBlock ( // Bit4 -- DisableAutoDetect. 0 -- Firmware MAY autodetect. // If (LNot (And (MORD, 0x10))) { // - // Triggle the SMI through ACPI _PTS method. + // Trigger the SMI through ACPI _PTS method. // Store (0x02, MCIP) // - // Triggle the SMI interrupt + // Trigger the SMI interrupt // Store (MCIN, IOB2) } } Return (0) @@ -363,11 +363,11 @@ DefinitionBlock ( Store (DerefOf (Index (Arg2, 0x00)), PPRQ) Store (0, PPRM) Store (0x02, PPIP) // - // Triggle the SMI interrupt + // Trigger the SMI interrupt // Store (PPIN, IOB2) Return (FRET) @@ -394,11 +394,11 @@ DefinitionBlock ( // e) Return TPM Operation Response to OS Environment // Store (0x05, PPIP) // - // Triggle the SMI interrupt + // Trigger the SMI interrupt // Store (PPIN, IOB2) Store (LPPR, Index (TPM3, 0x01)) Store (PPRP, Index (TPM3, 0x02)) @@ -426,11 +426,11 @@ DefinitionBlock ( If (LEqual (PPRQ, 23)) { Store (DerefOf (Index (Arg2, 0x01)), PPRM) } // - // Triggle the SMI interrupt + // Trigger the SMI interrupt // Store (PPIN, IOB2) Return (FRET) } Case (8) @@ -440,11 +440,11 @@ DefinitionBlock ( // Store (8, PPIP) Store (DerefOf (Index (Arg2, 0x00)), UCRQ) // - // Triggle the SMI interrupt + // Trigger the SMI interrupt // Store (PPIN, IOB2) Return (FRET) } @@ -474,16 +474,16 @@ DefinitionBlock ( // Save the Operation Value of the Request to MORD (reserved memory) // Store (DerefOf (Index (Arg2, 0x00)), MORD) // - // Triggle the SMI through ACPI _DSM method. + // Trigger the SMI through ACPI _DSM method. // Store (0x01, MCIP) // - // Triggle the SMI interrupt + // Trigger the SMI interrupt // Store (MCIN, IOB2) Return (MRET) } Default {BreakPoint} diff --git a/SecurityPkg/Tcg/TcgSmm/Tpm.asl b/SecurityPkg/Tcg/TcgSmm/Tpm.asl index 12f24f3996..2114283b45 100644 --- a/SecurityPkg/Tcg/TcgSmm/Tpm.asl +++ b/SecurityPkg/Tcg/TcgSmm/Tpm.asl @@ -93,16 +93,16 @@ DefinitionBlock ( // Bit4 -- DisableAutoDetect. 0 -- Firmware MAY autodetect. // If (LNot (And (MORD, 0x10))) { // - // Triggle the SMI through ACPI _PTS method. + // Trigger the SMI through ACPI _PTS method. // Store (0x02, MCIP) // - // Triggle the SMI interrupt + // Trigger the SMI interrupt // Store (MCIN, IOB2) } } Return (0) @@ -198,11 +198,11 @@ DefinitionBlock ( Store (DerefOf (Index (Arg2, 0x00)), PPRQ) Store (0x02, PPIP) // - // Triggle the SMI interrupt + // Trigger the SMI interrupt // Store (PPIN, IOB2) Return (FRET) @@ -229,11 +229,11 @@ DefinitionBlock ( // e) Return TPM Operation Response to OS Environment // Store (0x05, PPIP) // - // Triggle the SMI interrupt + // Trigger the SMI interrupt // Store (PPIN, IOB2) Store (LPPR, Index (TPM3, 0x01)) Store (PPRP, Index (TPM3, 0x02)) @@ -257,11 +257,11 @@ DefinitionBlock ( // Store (7, PPIP) Store (DerefOf (Index (Arg2, 0x00)), PPRQ) // - // Triggle the SMI interrupt + // Trigger the SMI interrupt // Store (PPIN, IOB2) Return (FRET) } Case (8) @@ -271,11 +271,11 @@ DefinitionBlock ( // Store (8, PPIP) Store (DerefOf (Index (Arg2, 0x00)), UCRQ) // - // Triggle the SMI interrupt + // Trigger the SMI interrupt // Store (PPIN, IOB2) Return (FRET) } @@ -305,16 +305,16 @@ DefinitionBlock ( // Save the Operation Value of the Request to MORD (reserved memory) // Store (DerefOf (Index (Arg2, 0x00)), MORD) // - // Triggle the SMI through ACPI _DSM method. + // Trigger the SMI through ACPI _DSM method. // Store (0x01, MCIP) // - // Triggle the SMI interrupt + // Trigger the SMI interrupt // Store (MCIN, IOB2) Return (MRET) } Default {BreakPoint} -- 2.16.2.windows.1