From: Chris Co <Christopher.Co@microsoft.com>
To: "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>,
Leif Lindholm <leif.lindholm@linaro.org>,
Michael D Kinney <michael.d.kinney@intel.com>
Subject: [PATCH edk2-platforms 7/7] Silicon/NXP: Add headers for other iMX packages to use
Date: Thu, 19 Jul 2018 04:11:27 +0000 [thread overview]
Message-ID: <20180719041103.9072-8-christopher.co@microsoft.com> (raw)
In-Reply-To: <20180719041103.9072-1-christopher.co@microsoft.com>
This adds common headers for NXP i.MX platforms. More specifically,
common i.MX platform definitions and macros.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Christopher Co <christopher.co@microsoft.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
---
Silicon/NXP/iMXPlatformPkg/Include/Platform.h | 86 +++
Silicon/NXP/iMXPlatformPkg/Include/common_macros.h | 561 ++++++++++++++++++++
Silicon/NXP/iMXPlatformPkg/Include/iMXIoMux.h | 24 +
3 files changed, 671 insertions(+)
diff --git a/Silicon/NXP/iMXPlatformPkg/Include/Platform.h b/Silicon/NXP/iMXPlatformPkg/Include/Platform.h
new file mode 100644
index 000000000000..7fb3bdfacf7c
--- /dev/null
+++ b/Silicon/NXP/iMXPlatformPkg/Include/Platform.h
@@ -0,0 +1,86 @@
+/** @file
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+//
+// Freescale i.MX Platform specific defines for constructing ACPI tables
+//
+
+#ifndef _PLATFORM_IMX_H_
+#define _PLATFORM_IMX_H_
+
+#include <IndustryStandard/Acpi50.h>
+
+#define EFI_ACPI_OEM_ID {'M','C','R','S','F','T'} // OEMID 6 bytes long
+
+#define EFI_ACPI_VENDOR_ID SIGNATURE_32('M','S','F','T')
+#define EFI_ACPI_CSRT_REVISION 0x00000005
+
+#define EFI_ACPI_5_0_CSRT_REVISION 0x00000000
+
+//
+// Resource Descriptor Types
+//
+
+#define EFI_ACPI_CSRT_RD_TYPE_INTERRUPT 1
+#define EFI_ACPI_CSRT_RD_TYPE_TIMER 2
+#define EFI_ACPI_CSRT_RD_TYPE_DMA 3
+#define EFI_ACPI_CSRT_RD_TYPE_CACHE 4
+
+//
+// Resource Descriptor Subtypes
+//
+
+#define EFI_ACPI_CSRT_RD_SUBTYPE_INTERRUPT_LINES 0
+#define EFI_ACPI_CSRT_RD_SUBTYPE_INTERRUPT_CONTROLLER 1
+#define EFI_ACPI_CSRT_RD_SUBTYPE_TIMER 0
+#define EFI_ACPI_CSRT_RD_SUBTYPE_DMA_CHANNEL 0
+#define EFI_ACPI_CSRT_RD_SUBTYPE_DMA_CONTROLLER 1
+#define EFI_ACPI_CSRT_RD_SUBTYPE_CACHE 0
+
+//
+// Fixed device IDs
+//
+
+#define EFI_ACPI_CSRT_DEVICE_ID_DMA 0x00000009
+
+#pragma pack(push, 1)
+
+//------------------------------------------------------------------------
+// CSRT Resource Group header 24 bytes long
+//------------------------------------------------------------------------
+typedef struct
+{
+ UINT32 Length; // Length
+ UINT32 VendorID; // 4 bytes
+ UINT32 SubVendorId; // 4 bytes
+ UINT16 DeviceId; // 2 bytes
+ UINT16 SubdeviceId; // 2 bytes
+ UINT16 Revision; // 2 bytes
+ UINT16 Reserved; // 2 bytes
+ UINT32 SharedInfoLength; // 4 bytes
+} EFI_ACPI_5_0_CSRT_RESOURCE_GROUP_HEADER;
+
+//------------------------------------------------------------------------
+// CSRT Resource Descriptor 12 bytes total
+//------------------------------------------------------------------------
+typedef struct
+{
+ UINT32 Length; // 4 bytes
+ UINT16 ResourceType; // 2 bytes
+ UINT16 ResourceSubType; // 2 bytes
+ UINT32 UID; // 4 bytes
+} EFI_ACPI_5_0_CSRT_RESOURCE_DESCRIPTOR_HEADER;
+
+#pragma pack (pop)
+
+#endif // !_PLATFORM_IMX_H_
diff --git a/Silicon/NXP/iMXPlatformPkg/Include/common_macros.h b/Silicon/NXP/iMXPlatformPkg/Include/common_macros.h
new file mode 100644
index 000000000000..5f28f31050c6
--- /dev/null
+++ b/Silicon/NXP/iMXPlatformPkg/Include/common_macros.h
@@ -0,0 +1,561 @@
+/** @file
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+//-----------------------------------------------------------------------------
+//
+// Header: common_macros.h
+//
+// Provides common macro definitions SOC/BSP code development.
+//
+//------------------------------------------------------------------------------
+//
+// Copyright (C) 2007-2010, Freescale Semiconductor, Inc. All Rights Reserved.
+// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
+// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
+//
+//------------------------------------------------------------------------------
+
+#ifndef __SOCARM_MACROS_H__
+#define __SOCARM_MACROS_H__
+
+// Bitfield macros that use rely on bitfield width/shift information
+// defined in SOC header files
+#define CSP_BITFMASK(bit) (((1U << (bit ## _WID)) - 1) << (bit ## _LSH))
+#define CSP_BITFVAL(bit, val) ((val) << (bit ## _LSH))
+
+// Undefine previous implementations of peripheral access macros since
+// we want to "own" the definitions and avoid redefinition warnings
+// resulting from source code that includes oal_io.h
+#undef INREG8
+#undef OUTREG8
+#undef SETREG8
+#undef CLRREG8
+#undef INREG16
+#undef OUTREG16
+#undef SETREG16
+#undef CLRREG16
+#undef INREG32
+#undef OUTREG32
+#undef SETREG32
+#undef CLRREG32
+
+#define READ_REGISTER_ULONG(reg) \
+ (*(volatile unsigned long * const)(reg))
+
+#define WRITE_REGISTER_ULONG(reg, val) \
+ (*(volatile unsigned long * const)(reg)) = (val)
+
+#define READ_REGISTER_USHORT(reg) \
+ (*(volatile unsigned short * const)(reg))
+
+#define WRITE_REGISTER_USHORT(reg, val) \
+ (*(volatile unsigned short * const)(reg)) = (val)
+
+#define READ_REGISTER_UCHAR(reg) \
+ (*(volatile unsigned char * const)(reg))
+
+#define WRITE_REGISTER_UCHAR(reg, val) \
+ (*(volatile unsigned char * const)(reg)) = (val)
+
+
+// Macros for accessing peripheral registers using DDK macros/functions
+#define INREG8(x) READ_REGISTER_UCHAR((UCHAR*)(x))
+#define OUTREG8(x, y) WRITE_REGISTER_UCHAR((UCHAR*)(x), (UCHAR)(y))
+#define SETREG8(x, y) OUTREG8(x, INREG8(x)|(y))
+#define CLRREG8(x, y) OUTREG8(x, INREG8(x)&~(y))
+#define INSREG8(addr, mask, val) OUTREG8(addr, ((INREG8(addr)&(~(mask))) | val))
+#define EXTREG8(addr, mask, lsh) ((INREG8(addr) & mask) >> lsh)
+#define EXTREG8BF(addr, bit) (EXTREG8(addr, CSP_BITFMASK(bit), (bit ## _LSH)))
+#define INSREG8BF(addr, bit, val) (INSREG8(addr, CSP_BITFMASK(bit), CSP_BITFVAL(bit, val)))
+
+#define INREG16(x) READ_REGISTER_USHORT((USHORT*)(x))
+#define OUTREG16(x, y) WRITE_REGISTER_USHORT((USHORT*)(x),(USHORT)(y))
+#define SETREG16(x, y) OUTREG16(x, INREG16(x)|(y))
+#define CLRREG16(x, y) OUTREG16(x, INREG16(x)&~(y))
+#define INSREG16(addr, mask, val) OUTREG16(addr, ((INREG16(addr)&(~(mask))) | val))
+#define EXTREG16(addr, mask, lsh) ((INREG16(addr) & mask) >> lsh)
+#define EXTREG16BF(addr, bit) (EXTREG16(addr, CSP_BITFMASK(bit), (bit ## _LSH)))
+#define INSREG16BF(addr, bit, val) (INSREG16(addr, CSP_BITFMASK(bit), CSP_BITFVAL(bit, val)))
+
+#define INREG32(x) READ_REGISTER_ULONG((long*)(x))
+#define OUTREG32(x, y) WRITE_REGISTER_ULONG((long*)(x), (long)(y))
+#define SETREG32(x, y) OUTREG32(x, INREG32(x)|(y))
+#define CLRREG32(x, y) OUTREG32(x, INREG32(x)&~(y))
+#define INSREG32(addr, mask, val) OUTREG32(addr, ((INREG32(addr)&(~(mask))) | val))
+#define EXTREG32(addr, mask, lsh) ((INREG32(addr) & mask) >> lsh)
+#define EXTREG32BF(addr, bit) (EXTREG32(addr, CSP_BITFMASK(bit), (bit ## _LSH)))
+#define INSREG32BF(addr, bit, val) (INSREG32(addr, CSP_BITFMASK(bit), CSP_BITFVAL(bit, val)))
+
+// macros for pin mux
+#define OAL_IOMUX_SET_MUX(pIOMUX, pin, muxmode, sion) \
+ OUTREG32(&pIOMUX->SW_MUX_CTL[pin], (muxmode | sion))
+
+#define OAL_IOMUX_SET_PAD(pIOMUX, pad, slew, drive, openDrain, pull, hysteresis, inputMode, outputVolt) \
+ OUTREG32(&pIOMUX->SW_PAD_CTL[pad], (slew | drive | openDrain | pull | hysteresis | inputMode | outputVolt))
+
+
+// Macros for bitfield operations on data variables. DO NOT use for peripheral
+// register accesses. Use the INREG/OUTREG based macros above for peripheral
+// accesses.
+#define CSP_BITFEXT(var, bit) ((var & CSP_BITFMASK(bit)) >> (bit ## _LSH))
+
+#define CSP_BITFCLR(var, bit) (var &= (~CSP_BITFMASK(bit)))
+
+#define CSP_BITFINS(var, bit, val) \
+ (CSP_BITFCLR(var, bit)); (var |= CSP_BITFVAL(bit, val))
+
+// Macros for generating 64-bit IRQ masks
+#define CSP_IRQMASK(irq) (((ULONGLONG) 1) << irq)
+
+// Macros to create Unicode function name
+#define WIDEN2(x) L ## x
+#define WIDEN(x) WIDEN2(x)
+#define __WFUNCTION__ WIDEN(__FUNCTION__)
+
+// Macros for function tracing (better to use debug zones as these
+// macros will be phases out)
+#define CSP_FUNC_TRACE_ENTRY() \
+ DEBUGMSG(1, (TEXT("+%s\r\n"), __WFUNCTION__))
+
+#define CSP_FUNC_TRACE_EXIT() \
+ DEBUGMSG(1, (TEXT("-%s\r\n"), __WFUNCTION__))
+
+// Macros for importing/exporting DLL interface
+#define DllExport __declspec( dllexport )
+
+
+//STMP macros for single instance registers
+#define BF_SET(reg, field) HW_ ## reg ## _SET(BM_ ## reg ## _ ## field)
+#define BF_CLR(reg, field) HW_ ## reg ## _CLR(BM_ ## reg ## _ ## field)
+#define BF_TOG(reg, field) HW_ ## reg ## _TOG(BM_ ## reg ## _ ## field)
+
+#define BF_SETV(reg, field, v) HW_ ## reg ## _SET(BF_ ## reg ## _ ## field(v))
+#define BF_CLRV(reg, field, v) HW_ ## reg ## _CLR(BF_ ## reg ## _ ## field(v))
+#define BF_TOGV(reg, field, v) HW_ ## reg ## _TOG(BF_ ## reg ## _ ## field(v))
+
+#define BV_FLD(reg, field, sym) BF_ ## reg ## _ ## field(BV_ ## reg ## _ ## field ## __ ## sym)
+#define BV_VAL(reg, field, sym) BV_ ## reg ## _ ## field ## __ ## sym
+
+#define BF_RD(reg, field) HW_ ## reg.B.field
+#define BF_WR(reg, field, v) BW_ ## reg ## _ ## field(v)
+
+#define BF_CS1(reg, f1, v1) \
+ (HW_ ## reg ## _CLR(BM_ ## reg ## _ ## f1), \
+ HW_ ## reg ## _SET(BF_ ## reg ## _ ## f1(v1)))
+
+#define BF_CS2(reg, f1, v1, f2, v2) \
+ (HW_ ## reg ## _CLR(BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2), \
+ HW_ ## reg ## _SET(BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2)))
+
+#define BF_CS3(reg, f1, v1, f2, v2, f3, v3) \
+ (HW_ ## reg ## _CLR(BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3), \
+ HW_ ## reg ## _SET(BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3)))
+
+#define BF_CS4(reg, f1, v1, f2, v2, f3, v3, f4, v4) \
+ (HW_ ## reg ## _CLR(BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4), \
+ HW_ ## reg ## _SET(BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4)))
+
+#define BF_CS5(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
+ (HW_ ## reg ## _CLR(BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5), \
+ HW_ ## reg ## _SET(BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5)))
+
+#define BF_CS6(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
+ (HW_ ## reg ## _CLR(BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5 | \
+ BM_ ## reg ## _ ## f6), \
+ HW_ ## reg ## _SET(BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5) | \
+ BF_ ## reg ## _ ## f6(v6)))
+
+#define BF_CS7(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
+ (HW_ ## reg ## _CLR(BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5 | \
+ BM_ ## reg ## _ ## f6 | \
+ BM_ ## reg ## _ ## f7), \
+ HW_ ## reg ## _SET(BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5) | \
+ BF_ ## reg ## _ ## f6(v6) | \
+ BF_ ## reg ## _ ## f7(v7)))
+
+#define BF_CS8(reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
+ (HW_ ## reg ## _CLR(BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5 | \
+ BM_ ## reg ## _ ## f6 | \
+ BM_ ## reg ## _ ## f7 | \
+ BM_ ## reg ## _ ## f8), \
+ HW_ ## reg ## _SET(BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5) | \
+ BF_ ## reg ## _ ## f6(v6) | \
+ BF_ ## reg ## _ ## f7(v7) | \
+ BF_ ## reg ## _ ## f8(v8)))
+
+
+//
+// macros for multiple instance registers
+//
+
+#define BF_SETn(reg, n, field) HW_ ## reg ## _SET(n, BM_ ## reg ## _ ## field)
+#define BF_CLRn(reg, n, field) HW_ ## reg ## _CLR(n, BM_ ## reg ## _ ## field)
+#define BF_TOGn(reg, n, field) HW_ ## reg ## _TOG(n, BM_ ## reg ## _ ## field)
+
+#define BF_SETVn(reg, n, field, v) HW_ ## reg ## _SET(n, BF_ ## reg ## _ ## field(v))
+#define BF_CLRVn(reg, n, field, v) HW_ ## reg ## _CLR(n, BF_ ## reg ## _ ## field(v))
+#define BF_TOGVn(reg, n, field, v) HW_ ## reg ## _TOG(n, BF_ ## reg ## _ ## field(v))
+
+#define BV_FLDn(reg, n, field, sym) BF_ ## reg ## _ ## field(BV_ ## reg ## _ ## field ## __ ## sym)
+#define BV_VALn(reg, n, field, sym) BV_ ## reg ## _ ## field ## __ ## sym
+
+#define BF_RDn(reg, n, field) HW_ ## reg(n).B.field
+#define BF_WRn(reg, n, field, v) BW_ ## reg ## _ ## field(n, v)
+
+#define BF_CS1n(reg, n, f1, v1) \
+ (HW_ ## reg ## _CLR(n, (BM_ ## reg ## _ ## f1)), \
+ HW_ ## reg ## _SET(n, (BF_ ## reg ## _ ## f1(v1))))
+
+#define BF_CS2n(reg, n, f1, v1, f2, v2) \
+ (HW_ ## reg ## _CLR(n, (BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2)), \
+ HW_ ## reg ## _SET(n, (BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2))))
+
+#define BF_CS3n(reg, n, f1, v1, f2, v2, f3, v3) \
+ (HW_ ## reg ## _CLR(n, (BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3)), \
+ HW_ ## reg ## _SET(n, (BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3))))
+
+#define BF_CS4n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \
+ (HW_ ## reg ## _CLR(n, (BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4)), \
+ HW_ ## reg ## _SET(n, (BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4))))
+
+#define BF_CS5n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
+ (HW_ ## reg ## _CLR(n, (BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5)), \
+ HW_ ## reg ## _SET(n, (BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5))))
+
+#define BF_CS6n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
+ (HW_ ## reg ## _CLR(n, (BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5 | \
+ BM_ ## reg ## _ ## f6)), \
+ HW_ ## reg ## _SET(n, (BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5) | \
+ BF_ ## reg ## _ ## f6(v6))))
+
+#define BF_CS7n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
+ (HW_ ## reg ## _CLR(n, (BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5 | \
+ BM_ ## reg ## _ ## f6 | \
+ BM_ ## reg ## _ ## f7)), \
+ HW_ ## reg ## _SET(n, (BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5) | \
+ BF_ ## reg ## _ ## f6(v6) | \
+ BF_ ## reg ## _ ## f7(v7))))
+
+#define BF_CS8n(reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
+ (HW_ ## reg ## _CLR(n, (BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5 | \
+ BM_ ## reg ## _ ## f6 | \
+ BM_ ## reg ## _ ## f7 | \
+ BM_ ## reg ## _ ## f8)), \
+ HW_ ## reg ## _SET(n, (BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5) | \
+ BF_ ## reg ## _ ## f6(v6) | \
+ BF_ ## reg ## _ ## f7(v7) | \
+ BF_ ## reg ## _ ## f8(v8))))
+
+///////
+
+//
+// macros for single instance registers
+//
+
+#define BFi_SET(i, reg, field) HWi_ ## reg ## _SET(i, BM_ ## reg ## _ ## field)
+#define BFi_CLR(i, reg, field) HWi_ ## reg ## _CLR(i, BM_ ## reg ## _ ## field)
+#define BFi_TOG(i, reg, field) HWi_ ## reg ## _TOG(i, BM_ ## reg ## _ ## field)
+
+#define BFi_SETV(i, reg, field, v) HWi_ ## reg ## _SET(i, BF_ ## reg ## _ ## field(v))
+#define BFi_CLRV(i, reg, field, v) HWi_ ## reg ## _CLR(i, BF_ ## reg ## _ ## field(v))
+#define BFi_TOGV(i, reg, field, v) HWi_ ## reg ## _TOG(i, BF_ ## reg ## _ ## field(v))
+
+#define BFi_RD(i, reg, field) HWi_ ## reg(i).B.field
+#define BFi_WR(i, reg, field, v) BWi_ ## reg ## _ ## field(i, v)
+
+#define BFi_CS1(i, reg, f1, v1) \
+ (HWi_ ## reg ## _CLR(i, BM_ ## reg ## _ ## f1), \
+ HWi_ ## reg ## _SET(i, BF_ ## reg ## _ ## f1(v1)))
+
+#define BFi_CS2(i, reg, f1, v1, f2, v2) \
+ (HWi_ ## reg ## _CLR(i, BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2), \
+ HWi_ ## reg ## _SET(i, BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2)))
+
+#define BFi_CS3(i, reg, f1, v1, f2, v2, f3, v3) \
+ (HWi_ ## reg ## _CLR(i, BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3), \
+ HWi_ ## reg ## _SET(i, BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3)))
+
+#define BFi_CS4(i, reg, f1, v1, f2, v2, f3, v3, f4, v4) \
+ (HWi_ ## reg ## _CLR(i, BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4), \
+ HWi_ ## reg ## _SET(i, BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4)))
+
+#define BFi_CS5(i, reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
+ (HWi_ ## reg ## _CLR(i, BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5), \
+ HWi_ ## reg ## _SET(i, BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5)))
+
+#define BFi_CS6(i, reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
+ (HWi_ ## reg ## _CLR(i, BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5 | \
+ BM_ ## reg ## _ ## f6), \
+ HWi_ ## reg ## _SET(i, BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5) | \
+ BF_ ## reg ## _ ## f6(v6)))
+
+#define BFi_CS7(i, reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
+ (HWi_ ## reg ## _CLR(i, BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5 | \
+ BM_ ## reg ## _ ## f6 | \
+ BM_ ## reg ## _ ## f7), \
+ HWi_ ## reg ## _SET(i, BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5) | \
+ BF_ ## reg ## _ ## f6(v6) | \
+ BF_ ## reg ## _ ## f7(v7)))
+
+#define BFi_CS8(i, reg, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
+ (HWi_ ## reg ## _CLR(i, BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5 | \
+ BM_ ## reg ## _ ## f6 | \
+ BM_ ## reg ## _ ## f7 | \
+ BM_ ## reg ## _ ## f8), \
+ HWi_ ## reg ## _SET(i, BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5) | \
+ BF_ ## reg ## _ ## f6(v6) | \
+ BF_ ## reg ## _ ## f7(v7) | \
+ BF_ ## reg ## _ ## f8(v8)))
+
+
+//
+// macros for multiple instance registers
+//
+
+#define BFi_SETn(i, reg, n, field) HWi_ ## reg ## _SET(i, n, BM_ ## reg ## _ ## field)
+#define BFi_CLRn(i, reg, n, field) HWi_ ## reg ## _CLR(i, n, BM_ ## reg ## _ ## field)
+#define BFi_TOGn(i, reg, n, field) HWi_ ## reg ## _TOG(i, n, BM_ ## reg ## _ ## field)
+
+#define BFi_SETVn(i, reg, n, field, v) HWi_ ## reg ## _SET(i, n, BF_ ## reg ## _ ## field(v))
+#define BFi_CLRVn(i, reg, n, field, v) HWi_ ## reg ## _CLR(i, n, BF_ ## reg ## _ ## field(v))
+#define BFi_TOGVn(i, reg, n, field, v) HWi_ ## reg ## _TOG(i, n, BF_ ## reg ## _ ## field(v))
+
+#define BFi_RDn(i, reg, n, field) HWi_ ## reg(i, n).B.field
+#define BFi_WRn(i, reg, n, field, v) BWi_ ## reg ## _ ## field(i, n, v)
+
+#define BFi_CS1n(i, reg, n, f1, v1) \
+ (HWi_ ## reg ## _CLR(i, n, (BM_ ## reg ## _ ## f1)), \
+ HWi_ ## reg ## _SET(i, n, (BF_ ## reg ## _ ## f1(v1))))
+
+#define BFi_CS2n(i, reg, n, f1, v1, f2, v2) \
+ (HWi_ ## reg ## _CLR(i, n, (BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2)), \
+ HWi_ ## reg ## _SET(i, n, (BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2))))
+
+#define BFi_CS3n(i, reg, n, f1, v1, f2, v2, f3, v3) \
+ (HWi_ ## reg ## _CLR(i, n, (BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3)), \
+ HWi_ ## reg ## _SET(i, n, (BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3))))
+
+#define BFi_CS4n(i, reg, n, f1, v1, f2, v2, f3, v3, f4, v4) \
+ (HWi_ ## reg ## _CLR(i, n, (BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4)), \
+ HWi_ ## reg ## _SET(i, n, (BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4))))
+
+#define BFi_CS5n(i, reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5) \
+ (HWi_ ## reg ## _CLR(i, n, (BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5)), \
+ HWi_ ## reg ## _SET(i, n, (BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5))))
+
+#define BFi_CS6n(i, reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6) \
+ (HWi_ ## reg ## _CLR(i, n, (BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5 | \
+ BM_ ## reg ## _ ## f6)), \
+ HWi_ ## reg ## _SET(i, n, (BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5) | \
+ BF_ ## reg ## _ ## f6(v6))))
+
+#define BFi_CS7n(i, reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7) \
+ (HWi_ ## reg ## _CLR(i, n, (BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5 | \
+ BM_ ## reg ## _ ## f6 | \
+ BM_ ## reg ## _ ## f7)), \
+ HWi_ ## reg ## _SET(i, n, (BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5) | \
+ BF_ ## reg ## _ ## f6(v6) | \
+ BF_ ## reg ## _ ## f7(v7))))
+
+#define BFi_CS8n(i, reg, n, f1, v1, f2, v2, f3, v3, f4, v4, f5, v5, f6, v6, f7, v7, f8, v8) \
+ (HWi_ ## reg ## _CLR(i, n, (BM_ ## reg ## _ ## f1 | \
+ BM_ ## reg ## _ ## f2 | \
+ BM_ ## reg ## _ ## f3 | \
+ BM_ ## reg ## _ ## f4 | \
+ BM_ ## reg ## _ ## f5 | \
+ BM_ ## reg ## _ ## f6 | \
+ BM_ ## reg ## _ ## f7 | \
+ BM_ ## reg ## _ ## f8)), \
+ HWi_ ## reg ## _SET(i, n, (BF_ ## reg ## _ ## f1(v1) | \
+ BF_ ## reg ## _ ## f2(v2) | \
+ BF_ ## reg ## _ ## f3(v3) | \
+ BF_ ## reg ## _ ## f4(v4) | \
+ BF_ ## reg ## _ ## f5(v5) | \
+ BF_ ## reg ## _ ## f6(v6) | \
+ BF_ ## reg ## _ ## f7(v7) | \
+ BF_ ## reg ## _ ## f8(v8))))
+// Macros to create Unicode function name
+#define WIDEN2(x) L ## x
+#define WIDEN(x) WIDEN2(x)
+#define __WFUNCTION__ WIDEN(__FUNCTION__)
+
+
+#endif // __SOCARM_MACROS_H__
diff --git a/Silicon/NXP/iMXPlatformPkg/Include/iMXIoMux.h b/Silicon/NXP/iMXPlatformPkg/Include/iMXIoMux.h
new file mode 100644
index 000000000000..b7ff96926639
--- /dev/null
+++ b/Silicon/NXP/iMXPlatformPkg/Include/iMXIoMux.h
@@ -0,0 +1,24 @@
+/** @file
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _IMX_IO_MUX_H_
+#define _IMX_IO_MUX_H_
+
+#define _IMX_PAD(CtlRegOffset, MuxRegOffset) \
+ ((((CtlRegOffset) & 0xffff) << 16) | ((MuxRegOffset) & 0xffff))
+
+#define _IMX_PAD_CTL_OFFSET(ImxPadVal) ((ImxPadVal) >> 16)
+#define _IMX_PAD_MUX_OFFSET(ImxPadVal) ((ImxPadVal) & 0xffff)
+
+#endif // _IMX_IO_MUX_H_
--
2.16.2.gvfs.1.33.gf5370f1
prev parent reply other threads:[~2018-07-19 4:11 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-19 4:11 [PATCH edk2-platforms 0/7] Silicon/NXP: Import NXP i.MX platform package Chris Co
2018-07-19 4:11 ` [PATCH edk2-platforms 1/7] Silicon/NXP: Add support for iMX SDHC Chris Co
2018-08-01 16:15 ` Leif Lindholm
2018-08-01 23:59 ` Chris Co
2018-07-19 4:11 ` [PATCH edk2-platforms 2/7] Silicon/NXP: Add iMX display library support Chris Co
2018-07-19 4:11 ` [PATCH edk2-platforms 3/7] Silicon/NXP: Add I2C library support for iMX platforms Chris Co
2018-07-19 4:11 ` [PATCH edk2-platforms 4/7] Silicon/NXP: Add UART " Chris Co
2018-07-19 4:11 ` [PATCH edk2-platforms 5/7] Silicon/NXP: Add Virtual RTC support for IMX platform Chris Co
2018-07-19 4:11 ` [PATCH edk2-platforms 6/7] Silicon/NXP: Add iMXPlatformPkg dec Chris Co
2018-07-19 4:11 ` Chris Co [this message]
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