From: Chris Co <Christopher.Co@microsoft.com>
To: "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>,
Leif Lindholm <leif.lindholm@linaro.org>,
Michael D Kinney <michael.d.kinney@intel.com>
Subject: [PATCH edk2-platforms 01/13] Silicon/NXP: Add i.MX6 SoC header files
Date: Fri, 20 Jul 2018 06:33:44 +0000 [thread overview]
Message-ID: <20180720063328.26856-2-christopher.co@microsoft.com> (raw)
In-Reply-To: <20180720063328.26856-1-christopher.co@microsoft.com>
This adds includes for NXP i.MX6 SoC family, specifically Dual/Quad,
Solo/DualLite, and SoloX families.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Christopher Co <christopher.co@microsoft.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
---
Silicon/NXP/iMX6Pkg/Include/iMX6.h | 39 +
Silicon/NXP/iMX6Pkg/Include/iMX6BoardLib.h | 36 +
Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr.h | 574 +++++
Silicon/NXP/iMX6Pkg/Include/iMX6IoMux.h | 202 ++
Silicon/NXP/iMX6Pkg/Include/iMX6IoMux_DQ.h | 2464 +++++++++++++++++++
Silicon/NXP/iMX6Pkg/Include/iMX6IoMux_SDL.h | 2482 ++++++++++++++++++++
Silicon/NXP/iMX6Pkg/Include/iMX6IoMux_SX.h | 2275 ++++++++++++++++++
Silicon/NXP/iMX6Pkg/Include/iMX6UsbPhy.h | 20 +
Silicon/NXP/iMX6Pkg/Include/iMX6_DQ.h | 1686 +++++++++++++
Silicon/NXP/iMX6Pkg/Include/iMX6_SDL.h | 1657 +++++++++++++
Silicon/NXP/iMX6Pkg/Include/iMX6_SX.h | 1762 ++++++++++++++
11 files changed, 13197 insertions(+)
diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6.h b/Silicon/NXP/iMX6Pkg/Include/iMX6.h
new file mode 100644
index 000000000000..0d94e5209f4d
--- /dev/null
+++ b/Silicon/NXP/iMX6Pkg/Include/iMX6.h
@@ -0,0 +1,39 @@
+/** @file
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __IMX6_H__
+#define __IMX6_H__
+
+//
+// Platform specific definition
+//
+#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('I','M','X','6','E','D','K','2') // OEM table id 8 bytes long
+#define EFI_ACPI_OEM_REVISION 0x01000101
+#define EFI_ACPI_CREATOR_ID SIGNATURE_32('I','M','X','6')
+#define EFI_ACPI_CREATOR_REVISION 0x00000001
+
+#if defined(CPU_IMX6DQ)
+#include "iMX6_DQ.h"
+#elif defined(CPU_IMX6SDL)
+#include "iMX6_SDL.h"
+#elif defined(CPU_IMX6SX)
+#include "iMX6_SX.h"
+#else
+#error iMX6 CPU Type Not Defined! (Preprocessor Flag)
+#endif
+
+#define SERIAL_DEBUG_PORT_INIT_MSG "\r\nDebug Serial Port Init\r\n"
+#define SERIAL_PORT_INIT_MSG "UART"
+
+#endif // __IMX6_H__
diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6BoardLib.h b/Silicon/NXP/iMX6Pkg/Include/iMX6BoardLib.h
new file mode 100644
index 000000000000..821d87ed94a4
--- /dev/null
+++ b/Silicon/NXP/iMX6Pkg/Include/iMX6BoardLib.h
@@ -0,0 +1,36 @@
+/** @file
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _IMX6_BOARD_LIB_H_
+#define _IMX6_BOARD_LIB_H_
+
+/*
+ Mandatory functions to implement by the board library.
+*/
+
+VOID ImxClkPwrInit ();
+
+/*
+ Optional functions to implement by the board library.
+ The default implementation of these functions if not overridden is NOOP.
+*/
+
+VOID SdhcInit ();
+VOID EhciInit ();
+VOID I2cInit ();
+VOID SpiInit ();
+VOID PcieInit ();
+VOID SetupAudio ();
+
+#endif // _IMX6_BOARD_LIB_H_
diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr.h b/Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr.h
new file mode 100644
index 000000000000..7ae5396d553d
--- /dev/null
+++ b/Silicon/NXP/iMX6Pkg/Include/iMX6ClkPwr.h
@@ -0,0 +1,574 @@
+/** @file
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+* Copyright 2018 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _IMX6_CLK_PWR_H_
+#define _IMX6_CLK_PWR_H_
+
+#ifdef CPU_IMX6DQ
+//
+// Clock signal definitions
+//
+typedef enum {
+ IMX_CLK_NONE,
+ IMX_OSC_CLK,
+ IMX_PLL1_MAIN_CLK,
+ IMX_PLL2_MAIN_CLK,
+ IMX_PLL2_PFD0,
+ IMX_PLL2_PFD1,
+ IMX_PLL2_PFD2,
+ IMX_PLL3_MAIN_CLK,
+ IMX_PLL3_PFD0,
+ IMX_PLL3_PFD1,
+ IMX_PLL3_PFD2,
+ IMX_PLL3_PFD3,
+ IMX_PLL4_MAIN_CLK,
+ IMX_PLL5_MAIN_CLK,
+ IMX_CLK1,
+ IMX_CLK2,
+ IMX_PLL1_SW_CLK,
+ IMX_STEP_CLK,
+ IMX_PLL3_SW_CLK,
+ IMX_AXI_ALT,
+ IMX_AXI_CLK_ROOT,
+ IMX_PERIPH_CLK2,
+ IMX_PERIPH_CLK,
+ IMX_PRE_PERIPH_CLK,
+ IMX_PRE_PERIPH2_CLK,
+ IMX_PERIPH2_CLK,
+ IMX_ARM_CLK_ROOT,
+ IMX_MMDC_CH0_CLK_ROOT,
+ IMX_MMDC_CH1_CLK_ROOT,
+ IMX_AHB_CLK_ROOT,
+ IMX_IPG_CLK_ROOT,
+ IMX_PERCLK_CLK_ROOT,
+ IMX_USDHC1_CLK_ROOT,
+ IMX_USDHC2_CLK_ROOT,
+ IMX_USDHC3_CLK_ROOT,
+ IMX_USDHC4_CLK_ROOT,
+ IMX_SSI1_CLK_ROOT,
+ IMX_SSI2_CLK_ROOT,
+ IMX_SSI3_CLK_ROOT,
+ IMX_GPU2D_AXI_CLK_ROOT,
+ IMX_GPU3D_AXI_CLK_ROOT,
+ IMX_PCIE_AXI_CLK_ROOT,
+ IMX_VDO_AXI_CLK_ROOT,
+ IMX_IPU1_HSP_CLK_ROOT,
+ IMX_IPU2_HSP_CLK_ROOT,
+ IMX_GPU2D_CORE_CLK_ROOT,
+ IMX_ACLK_EIM_SLOW_CLK_ROOT,
+ IMX_ACLK_CLK_ROOT,
+ IMX_ENFC_CLK_ROOT,
+ IMX_GPU3D_CORE_CLK_ROOT,
+ IMX_GPU3D_SHADER_CLK_ROOT,
+ IMX_VPU_AXI_CLK_ROOT,
+ IMX_IPU1_DI0_CLK_ROOT,
+ IMX_IPU1_DI1_CLK_ROOT,
+ IMX_IPU2_DI0_CLK_ROOT,
+ IMX_IPU2_DI1_CLK_ROOT,
+ IMX_LDB_DI0_SERIAL_CLK_ROOT,
+ IMX_LDB_DI0_IPU,
+ IMX_LDB_DI1_SERIAL_CLK_ROOT,
+ IMX_LDB_DI1_IPU,
+ IMX_SPDIF0_CLK_ROOT,
+ IMX_SPDIF1_CLK_ROOT,
+ IMX_ESAI_CLK_ROOT,
+ IMX_HSI_TX_CLK_ROOT,
+ IMX_CAN_CLK_ROOT,
+ IMX_ECSPI_CLK_ROOT,
+ IMX_UART_CLK_ROOT,
+ IMX_VIDEO_27M_CLK_ROOT,
+ IMX_CLK_MAX,
+} IMX_CLK;
+
+//
+// Clock gate definitions
+//
+typedef enum {
+ IMX_AIPS_TZ1_CLK_ENABLE,
+ IMX_AIPS_TZ2_CLK_ENABLE,
+ IMX_APBHDMA_HCLK_ENABLE,
+ IMX_ASRC_CLK_ENABLE,
+ IMX_CAAM_SECURE_MEM_CLK_ENABLE,
+ IMX_CAAM_WRAPPER_ACLK_ENABLE,
+ IMX_CAAM_WRAPPER_IPG_ENABLE,
+ IMX_CAN1_CLK_ENABLE,
+ IMX_CAN1_SERIAL_CLK_ENABLE,
+ IMX_CAN2_CLK_ENABLE,
+ IMX_CAN2_SERIAL_CLK_ENABLE,
+ IMX_ARM_DBG_CLK_ENABLE,
+ IMX_DCIC1_CLK_ENABLE,
+ IMX_DCIC2_CLK_ENABLE,
+ IMX_DTCP_CLK_ENABLE,
+ IMX_ECSPI1_CLK_ENABLE,
+ IMX_ECSPI2_CLK_ENABLE,
+ IMX_ECSPI3_CLK_ENABLE,
+ IMX_ECSPI4_CLK_ENABLE,
+ IMX_ECSPI5_CLK_ENABLE,
+ IMX_ENET_CLK_ENABLE,
+ IMX_EPIT1_CLK_ENABLE,
+ IMX_EPIT2_CLK_ENABLE,
+ IMX_ESAI_CLK_ENABLE,
+ IMX_GPT_CLK_ENABLE,
+ IMX_GPT_SERIAL_CLK_ENABLE,
+ IMX_GPU2D_CLK_ENABLE,
+ IMX_GPU3D_CLK_ENABLE,
+ IMX_HDMI_TX_ENABLE,
+ IMX_HDMI_TX_ISFRCLK_ENABLE,
+ IMX_I2C1_SERIAL_CLK_ENABLE,
+ IMX_I2C2_SERIAL_CLK_ENABLE,
+ IMX_I2C3_SERIAL_CLK_ENABLE,
+ IMX_IIM_CLK_ENABLE,
+ IMX_IOMUX_IPT_CLK_IO_ENABLE,
+ IMX_IPMUX1_CLK_ENABLE,
+ IMX_IPMUX2_CLK_ENABLE,
+ IMX_IPMUX3_CLK_ENABLE,
+ IMX_IPSYNC_IP2APB_TZASC1_IPG_MASTER_CLK_ENABLE,
+ IMX_IPSYNC_IP2APB_TZASC2_IPG_MASTER_CLK_ENABLE,
+ IMX_IPSYNC_VDOA_IPG_MASTER_CLK_ENABLE,
+ IMX_IPU1_CLK_ENABLE,
+ IMX_IPU1_DI0_CLK_ENABLE,
+ IMX_IPU1_DI1_CLK_ENABLE,
+ IMX_IPU2_CLK_ENABLE,
+ IMX_IPU2_DI0_CLK_ENABLE,
+ IMX_IPU2_DI1_CLK_ENABLE,
+ IMX_LDB_DI0_CLK_ENABLE,
+ IMX_LDB_DI1_CLK_ENABLE,
+ IMX_MIPI_CORE_CFG_CLK_ENABLE,
+ IMX_MLB_CLK_ENABLE,
+ IMX_MMDC_CORE_ACLK_FAST_CORE_P0_ENABLE,
+ IMX_MMDC_CORE_IPG_CLK_P0_ENABLE,
+ IMX_OCRAM_CLK_ENABLE,
+ IMX_OPENVGAXICLK_CLK_ROOT_ENABLE,
+ IMX_PCIE_ROOT_ENABLE,
+ IMX_PL301_MX6QFAST1_S133CLK_ENABLE,
+ IMX_PL301_MX6QPER1_BCHCLK_ENABLE,
+ IMX_PL301_MX6QPER2_MAINCLK_ENABLE,
+ IMX_PWM1_CLK_ENABLE,
+ IMX_PWM2_CLK_ENABLE,
+ IMX_PWM3_CLK_ENABLE,
+ IMX_PWM4_CLK_ENABLE,
+ IMX_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE,
+ IMX_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE,
+ IMX_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE,
+ IMX_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE,
+ IMX_ROM_CLK_ENABLE,
+ IMX_SATA_CLK_ENABLE,
+ IMX_SDMA_CLK_ENABLE,
+ IMX_SPBA_CLK_ENABLE,
+ IMX_SPDIF_CLK_ENABLE,
+ IMX_SSI1_CLK_ENABLE,
+ IMX_SSI2_CLK_ENABLE,
+ IMX_SSI3_CLK_ENABLE,
+ IMX_UART_CLK_ENABLE,
+ IMX_UART_SERIAL_CLK_ENABLE,
+ IMX_USBOH3_CLK_ENABLE,
+ IMX_USDHC1_CLK_ENABLE,
+ IMX_USDHC2_CLK_ENABLE,
+ IMX_USDHC3_CLK_ENABLE,
+ IMX_USDHC4_CLK_ENABLE,
+ IMX_EIM_SLOW_CLK_ENABLE,
+ IMX_VDOAXICLK_CLK_ENABLE,
+ IMX_VPU_CLK_ENABLE,
+ IMX_CLK_GATE_MAX,
+} IMX_CLK_GATE;
+
+#elif defined(CPU_IMX6SDL)
+//
+// Clock signal definitions for iMX6 Solo and DualLite
+//
+typedef enum {
+ IMX_CLK_NONE,
+ IMX_OSC_CLK,
+ IMX_PLL1_MAIN_CLK,
+ IMX_PLL2_MAIN_CLK,
+ IMX_PLL2_PFD0,
+ IMX_PLL2_PFD1,
+ IMX_PLL2_PFD2,
+ IMX_PLL3_MAIN_CLK,
+ IMX_PLL3_PFD0,
+ IMX_PLL3_PFD1,
+ IMX_PLL3_PFD2,
+ IMX_PLL3_PFD3,
+ IMX_PLL4_MAIN_CLK,
+ IMX_PLL5_MAIN_CLK,
+ IMX_CLK1,
+ IMX_CLK2,
+ IMX_PLL1_SW_CLK,
+ IMX_STEP_CLK,
+ IMX_PLL3_SW_CLK,
+ IMX_AXI_ALT,
+ IMX_AXI_CLK_ROOT,
+ IMX_PERIPH_CLK2,
+ IMX_PERIPH_CLK,
+ IMX_PRE_PERIPH_CLK,
+ IMX_PRE_PERIPH2_CLK,
+ IMX_PERIPH2_CLK,
+ IMX_ARM_CLK_ROOT,
+ IMX_MMDC_CH0_CLK_ROOT,
+ IMX_MMDC_CH1_CLK_ROOT,
+ IMX_AHB_CLK_ROOT,
+ IMX_IPG_CLK_ROOT,
+ IMX_PERCLK_CLK_ROOT,
+ IMX_USDHC1_CLK_ROOT,
+ IMX_USDHC2_CLK_ROOT,
+ IMX_USDHC3_CLK_ROOT,
+ IMX_USDHC4_CLK_ROOT,
+ IMX_SSI1_CLK_ROOT,
+ IMX_SSI2_CLK_ROOT,
+ IMX_SSI3_CLK_ROOT,
+ IMX_GPU2D_AXI_CLK_ROOT,
+ IMX_GPU3D_AXI_CLK_ROOT,
+ IMX_PCIE_AXI_CLK_ROOT,
+ IMX_VDO_AXI_CLK_ROOT,
+ IMX_IPU1_HSP_CLK_ROOT,
+ IMX_GPU2D_CORE_CLK_ROOT,
+ IMX_ACLK_EIM_SLOW_CLK_ROOT,
+ IMX_ACLK_CLK_ROOT,
+ IMX_ENFC_CLK_ROOT,
+ IMX_GPU3D_CORE_CLK_ROOT,
+ IMX_GPU3D_SHADER_CLK_ROOT,
+ IMX_VPU_AXI_CLK_ROOT,
+ IMX_IPU1_DI0_CLK_ROOT,
+ IMX_IPU1_DI1_CLK_ROOT,
+ IMX_LDB_DI0_SERIAL_CLK_ROOT,
+ IMX_LDB_DI0_IPU,
+ IMX_LDB_DI1_SERIAL_CLK_ROOT,
+ IMX_LDB_DI1_IPU,
+ IMX_SPDIF0_CLK_ROOT,
+ IMX_SPDIF1_CLK_ROOT,
+ IMX_ESAI_CLK_ROOT,
+ IMX_HSI_TX_CLK_ROOT,
+ IMX_CAN_CLK_ROOT,
+ IMX_ECSPI_CLK_ROOT,
+ IMX_UART_CLK_ROOT,
+ IMX_VIDEO_27M_CLK_ROOT,
+ IMX_CLK_MAX,
+} IMX_CLK;
+
+//
+// Clock gate definitions
+//
+typedef enum {
+ IMX_AIPS_TZ1_CLK_ENABLE,
+ IMX_AIPS_TZ2_CLK_ENABLE,
+ IMX_APBHDMA_HCLK_ENABLE,
+ IMX_ASRC_CLK_ENABLE,
+ IMX_CAAM_SECURE_MEM_CLK_ENABLE,
+ IMX_CAAM_WRAPPER_ACLK_ENABLE,
+ IMX_CAAM_WRAPPER_IPG_ENABLE,
+ IMX_CAN1_CLK_ENABLE,
+ IMX_CAN1_SERIAL_CLK_ENABLE,
+ IMX_CAN2_CLK_ENABLE,
+ IMX_CAN2_SERIAL_CLK_ENABLE,
+ IMX_ARM_DBG_CLK_ENABLE,
+ IMX_DCIC1_CLK_ENABLE,
+ IMX_DCIC2_CLK_ENABLE,
+ IMX_DTCP_CLK_ENABLE,
+ IMX_ECSPI1_CLK_ENABLE,
+ IMX_ECSPI2_CLK_ENABLE,
+ IMX_ECSPI3_CLK_ENABLE,
+ IMX_ECSPI4_CLK_ENABLE,
+ IMX_ECSPI5_CLK_ENABLE,
+ IMX_ENET_CLK_ENABLE,
+ IMX_EPIT1_CLK_ENABLE,
+ IMX_EPIT2_CLK_ENABLE,
+ IMX_ESAI_CLK_ENABLE,
+ IMX_GPT_CLK_ENABLE,
+ IMX_GPT_SERIAL_CLK_ENABLE,
+ IMX_GPU2D_CLK_ENABLE,
+ IMX_GPU3D_CLK_ENABLE,
+ IMX_HDMI_TX_ENABLE,
+ IMX_HDMI_TX_ISFRCLK_ENABLE,
+ IMX_I2C1_SERIAL_CLK_ENABLE,
+ IMX_I2C2_SERIAL_CLK_ENABLE,
+ IMX_I2C3_SERIAL_CLK_ENABLE,
+ IMX_I2C4_SERIAL_CLK_ENABLE,
+ IMX_IIM_CLK_ENABLE,
+ IMX_IOMUX_IPT_CLK_IO_ENABLE,
+ IMX_IPMUX1_CLK_ENABLE,
+ IMX_IPMUX2_CLK_ENABLE,
+ IMX_IPMUX3_CLK_ENABLE,
+ IMX_IPSYNC_IP2APB_TZASC1_IPG_MASTER_CLK_ENABLE,
+ IMX_IPSYNC_IP2APB_TZASC2_IPG_MASTER_CLK_ENABLE,
+ IMX_IPSYNC_VDOA_IPG_MASTER_CLK_ENABLE,
+ IMX_IPU1_CLK_ENABLE,
+ IMX_IPU1_DI0_CLK_ENABLE,
+ IMX_IPU1_DI1_CLK_ENABLE,
+ IMX_LDB_DI0_CLK_ENABLE,
+ IMX_LDB_DI1_CLK_ENABLE,
+ IMX_MIPI_CORE_CFG_CLK_ENABLE,
+ IMX_MLB_CLK_ENABLE,
+ IMX_MMDC_CORE_ACLK_FAST_CORE_P0_ENABLE,
+ IMX_MMDC_CORE_IPG_CLK_P0_ENABLE,
+ IMX_OCRAM_CLK_ENABLE,
+ IMX_OPENVGAXICLK_CLK_ROOT_ENABLE,
+ IMX_PCIE_ROOT_ENABLE,
+ IMX_PL301_MX6QFAST1_S133CLK_ENABLE,
+ IMX_PL301_MX6QPER1_BCHCLK_ENABLE,
+ IMX_PL301_MX6QPER2_MAINCLK_ENABLE,
+ IMX_PWM1_CLK_ENABLE,
+ IMX_PWM2_CLK_ENABLE,
+ IMX_PWM3_CLK_ENABLE,
+ IMX_PWM4_CLK_ENABLE,
+ IMX_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE,
+ IMX_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE,
+ IMX_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE,
+ IMX_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE,
+ IMX_ROM_CLK_ENABLE,
+ IMX_SATA_CLK_ENABLE,
+ IMX_SDMA_CLK_ENABLE,
+ IMX_SPBA_CLK_ENABLE,
+ IMX_SPDIF_CLK_ENABLE,
+ IMX_SSI1_CLK_ENABLE,
+ IMX_SSI2_CLK_ENABLE,
+ IMX_SSI3_CLK_ENABLE,
+ IMX_UART_CLK_ENABLE,
+ IMX_UART_SERIAL_CLK_ENABLE,
+ IMX_USBOH3_CLK_ENABLE,
+ IMX_USDHC1_CLK_ENABLE,
+ IMX_USDHC2_CLK_ENABLE,
+ IMX_USDHC3_CLK_ENABLE,
+ IMX_USDHC4_CLK_ENABLE,
+ IMX_EIM_SLOW_CLK_ENABLE,
+ IMX_VDOAXICLK_CLK_ENABLE,
+ IMX_VPU_CLK_ENABLE,
+ IMX_CLK_GATE_MAX,
+} IMX_CLK_GATE;
+
+#elif defined(CPU_IMX6SX)
+//
+// Clock signal definitions
+//
+typedef enum {
+ IMX_CLK_NONE,
+ IMX_OSC_CLK,
+ IMX_PLL1_MAIN_CLK,
+ IMX_PLL2_MAIN_CLK,
+ IMX_PLL2_PFD0,
+ IMX_PLL2_PFD1,
+ IMX_PLL2_PFD2,
+ IMX_PLL2_PFD3,
+ IMX_PLL3_MAIN_CLK,
+ IMX_PLL3_PFD0,
+ IMX_PLL3_PFD1,
+ IMX_PLL3_PFD2,
+ IMX_PLL3_PFD3,
+ IMX_PLL4_MAIN_CLK,
+ IMX_PLL5_MAIN_CLK,
+ IMX_CLK1, // SX RM.p512
+ IMX_CLK2, // SX RM.p512
+ IMX_PLL1_SW_CLK, // SX RM.p795
+ IMX_STEP_CLK, // SX RM.p795
+ IMX_PLL3_SW_CLK, // SX RM.p795
+ IMX_PERIPH_CLK2, // SX RM.p797
+ IMX_PERIPH_CLK, // SX RM.p797
+ IMX_PRE_PERIPH_CLK, // SX RM.p797
+ IMX_ARM_CLK_ROOT,
+ IMX_MMDC_CLK_ROOT,
+ IMX_FABRIC_CLK_ROOT,
+ IMX_OCRAM_CLK_ROOT,
+ IMX_PCIE_CLK_ROOT,
+ IMX_AHB_CLK_ROOT,
+ IMX_PERCLK_CLK_ROOT,
+ IMX_IPG_CLK_ROOT,
+ IMX_USDHC1_CLK_ROOT,
+ IMX_USDHC2_CLK_ROOT,
+ IMX_USDHC3_CLK_ROOT,
+ IMX_USDHC4_CLK_ROOT,
+ IMX_ACLK_EIM_SLOW_CLK_ROOT,
+ IMX_GPU_AXI_CLK_ROOT,
+ IMX_GPU_CORE_CLK_ROOT,
+ IMX_VID_CLK_ROOT,
+ IMX_ESAI_CLK_ROOT,
+ IMX_AUDIO_CLK_ROOT,
+ IMX_SPDIF0_CLK_ROOT,
+ IMX_SSI1_CLK_ROOT,
+ IMX_SSI2_CLK_ROOT,
+ IMX_SSI3_CLK_ROOT,
+ IMX_LCDIF2_PIX_CLK_ROOT,
+ IMX_LCDIF1_PIX_CLK_ROOT,
+ IMX_LVDS_CLK_ROOT,
+ IMX_M4_CLK_ROOT,
+ IMX_ENET_CLK_ROOT,
+ IMX_QSPI1_CLK_ROOT,
+ IMX_QSPI2_CLK_ROOT,
+ IMX_DISPLAY_CLK_ROOT,
+ IMX_CSI_CLK_ROOT,
+ IMX_CAN_CLK_ROOT,
+ IMX_ECSPI_CLK_ROOT,
+ IMX_UART_CLK_ROOT,
+ IMX_CLK_MAX,
+} IMX_CLK; // SX RM.p777 Figure 19-2 Clock Tree
+
+//
+// Clock gate definitions
+//
+typedef enum {
+ IMX_AIPS_TZ1_CLK_ENABLE,
+ IMX_AIPS_TZ2_CLK_ENABLE,
+ IMX_APBHDMA_HCLK_ENABLE,
+ IMX_ASRC_CLK_ENABLE,
+ IMX_CAAM_SECURE_MEM_CLK_ENABLE,
+ IMX_CAAM_WRAPPER_ACLK_ENABLE,
+ IMX_CAAM_WRAPPER_IPG_ENABLE,
+ IMX_CAN1_CLK_ENABLE,
+ IMX_CAN1_SERIAL_CLK_ENABLE,
+ IMX_CAN2_CLK_ENABLE,
+ IMX_CAN2_SERIAL_CLK_ENABLE,
+ IMX_ARM_DBG_CLK_ENABLE,
+ IMX_DCIC1_CLK_ENABLE,
+ IMX_DCIC2_CLK_ENABLE,
+ IMX_AIPS_TZ3_CLK_ENABLE,
+ IMX_ECSPI1_CLK_ENABLE,
+ IMX_ECSPI2_CLK_ENABLE,
+ IMX_ECSPI3_CLK_ENABLE,
+ IMX_ECSPI4_CLK_ENABLE,
+ IMX_ECSPI5_CLK_ENABLE,
+ IMX_EPIT1_CLK_ENABLE,
+ IMX_EPIT2_CLK_ENABLE,
+ IMX_ESAI_CLK_ENABLE,
+ IMX_WAKEUP_CLK_ENABLE,
+ IMX_GPT_CLK_ENABLE,
+ IMX_GPT_SERIAL_CLK_ENABLE,
+ IMX_GPU_CLK_ENABLE,
+ IMX_OCRAM_S_CLK_ENABLE,
+ IMX_CANFD_CLK_ENABLE,
+ IMX_CSI_CLK_ENABLE,
+ IMX_I2C1_SERIAL_CLK_ENABLE,
+ IMX_I2C2_SERIAL_CLK_ENABLE,
+ IMX_I2C3_SERIAL_CLK_ENABLE,
+ IMX_IIM_CLK_ENABLE,
+ IMX_IOMUX_IPT_CLK_IO_ENABLE,
+ IMX_IPMUX1_CLK_ENABLE,
+ IMX_IPMUX2_CLK_ENABLE,
+ IMX_IPMUX3_CLK_ENABLE,
+ IMX_IPSYNC_IP2APB_TZASC1_IPG_MASTER_CLK_ENABLE,
+ IMX_LCD_CLK_ENABLE,
+ IMX_PXP_CLK_ENABLE,
+ IMX_M4_CLK_ENABLE,
+ IMX_ENET_CLK_ENABLE,
+ IMX_DISP_AXI_CLK_ENABLE,
+ IMX_LCDIF2_PIX_CLK_ENABLE,
+ IMX_LCDIF1_PIX_CLK_ENABLE,
+ IMX_LDB_DI0_CLK_ENABLE,
+ IMX_QSPI1_CLK_ENABLE,
+ IMX_MLB_CLK_ENABLE,
+ IMX_MMDC_CORE_ACLK_FAST_CORE_P0_ENABLE,
+ IMX_MMDC_CORE_IPG_CLK_P0_ENABLE,
+ IMX_MMDC_CORE_IPG_CLK_P1_ENABLE,
+ IMX_OCRAM_CLK_ENABLE,
+ IMX_PCIE_ROOT_ENABLE,
+ IMX_QSPI2_CLK_ENABLE,
+ IMX_PL301_MX6QPER1_BCHCLK_ENABLE,
+ IMX_PL301_MX6QPER2_MAINCLK_ENABLE,
+ IMX_PWM1_CLK_ENABLE,
+ IMX_PWM2_CLK_ENABLE,
+ IMX_PWM3_CLK_ENABLE,
+ IMX_PWM4_CLK_ENABLE,
+ IMX_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE,
+ IMX_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE,
+ IMX_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE,
+ IMX_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE,
+ IMX_ROM_CLK_ENABLE,
+ IMX_SDMA_CLK_ENABLE,
+ IMX_SPBA_CLK_ENABLE,
+ IMX_SPDIF_AND_AUDIO_CLK_ENABLE,
+ IMX_SSI1_CLK_ENABLE,
+ IMX_SSI2_CLK_ENABLE,
+ IMX_SSI3_CLK_ENABLE,
+ IMX_UART_CLK_ENABLE,
+ IMX_UART_SERIAL_CLK_ENABLE,
+ IMX_SAI1_CLK_ENABLE,
+ IMX_SAI2_CLK_ENABLE,
+ IMX_USBOH3_CLK_ENABLE,
+ IMX_USDHC1_CLK_ENABLE,
+ IMX_USDHC2_CLK_ENABLE,
+ IMX_USDHC3_CLK_ENABLE,
+ IMX_USDHC4_CLK_ENABLE,
+ IMX_EIM_SLOW_CLK_ENABLE,
+ IMX_PWM8_CLK_ENABLE,
+ IMX_VADC_CLK_ENABLE,
+ IMX_GIS_CLK_ENABLE,
+ IMX_I2C4_SERIAL_CLK_ENABLE,
+ IMX_PWM5_CLK_ENABLE,
+ IMX_PWM6_CLK_ENABLE,
+ IMX_PWM7_CLK_ENABLE,
+ IMX_CLK_GATE_MAX,
+} IMX_CLK_GATE;
+#else
+#error iMX6 CPU Type Not Defined!
+#endif
+
+typedef enum {
+ IMX_CLOCK_GATE_STATE_OFF = 0x0,
+ IMX_CLOCK_GATE_STATE_ON_RUN = 0x1,
+ IMX_CLOCK_GATE_STATE_ON = 0x3,
+} IMX_CLOCK_GATE_STATE;
+
+VOID ImxClkPwrSetClockGate (IMX_CLK_GATE ClockGate, IMX_CLOCK_GATE_STATE State);
+
+// Set multiple clock gates to a given state
+VOID
+ImxClkPwrSetClockGates (
+ const IMX_CLK_GATE *ClockGateList,
+ UINTN ClockGateCount,
+ IMX_CLOCK_GATE_STATE State
+ );
+
+IMX_CLOCK_GATE_STATE ImxClkPwrGetClockGate (IMX_CLK_GATE ClockGate);
+
+typedef struct {
+ UINT32 Frequency;
+ IMX_CLK Parent;
+} IMX_CLOCK_INFO;
+
+EFI_STATUS
+ImxClkPwrGetClockInfo (
+ IMX_CLK ClockId,
+ OUT IMX_CLOCK_INFO *ClockInfo
+ );
+
+EFI_STATUS ImxClkPwrGpuEnable ();
+
+EFI_STATUS ImxClkPwrIpuDIxEnable ();
+
+EFI_STATUS ImxClkPwrIpuLDBxEnable ();
+
+// The valid value for PLL loop divider is 27-54 so define the range of valid
+// frequency for PLL5 below before divider is applied.
+#define PLL5_MIN_FREQ 648000000
+#define PLL5_MAX_FREQ 1296000000
+EFI_STATUS ImxSetPll5ReferenceRate (UINT32 ClockRate);
+
+EFI_STATUS ImxClkPwrClkOut1Enable (IMX_CLK Clock, UINT32 Divider);
+
+VOID ImxClkPwrClkOut1Disable ();
+
+EFI_STATUS ImxClkPwrValidateClocks ();
+
+CONST CHAR16 *StringFromImxClk (IMX_CLK Value);
+
+#ifdef CPU_IMX6SX
+VOID ImxClkPwrLcdClockDisable ();
+VOID ImxClkPwrLcdClockEnable ();
+
+EFI_STATUS
+ImxSetLcdIfClockRate (
+ UINT32 ClockRate
+ ); // CPU_IMX6SX
+#else
+#endif
+
+#endif // _IMX6_CLK_PWR_H_
diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6IoMux.h b/Silicon/NXP/iMX6Pkg/Include/iMX6IoMux.h
new file mode 100644
index 000000000000..c585ec3dbdb1
--- /dev/null
+++ b/Silicon/NXP/iMX6Pkg/Include/iMX6IoMux.h
@@ -0,0 +1,202 @@
+/** @file
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _IMX6_IOMUX_H_
+#define _IMX6_IOMUX_H_
+
+//
+// IOMux common definition
+//
+#include <iMXIoMux.h>
+
+//
+// GPIO common definition
+//
+#include <iMXGpio.h>
+
+#if defined(CPU_IMX6DQ)
+#include "iMX6IoMux_DQ.h"
+#elif defined(CPU_IMX6SX)
+#include "iMX6IoMux_SX.h"
+#elif defined(CPU_IMX6SDL)
+#include "iMX6IoMux_SDL.h"
+#else
+#error CPU Preprocessor Flag Not Defined
+#endif
+
+typedef UINT64 IMX_PADCFG;
+
+//
+// Pad control settings
+//
+typedef enum {
+ IMX_HYS_DISABLED,
+ IMX_HYS_ENABLED,
+} IMX_HYS;
+
+typedef enum {
+ IMX_PUS_100K_OHM_PD,
+ IMX_PUS_47K_OHM_PU,
+ IMX_PUS_100K_OHM_PU,
+ IMX_PUS_22K_OHM_PU,
+} IMX_PUS;
+
+typedef enum {
+ IMX_PUE_KEEP,
+ IMX_PUE_PULL,
+} IMX_PUE;
+
+typedef enum {
+ IMX_PKE_DISABLE,
+ IMX_PKE_ENABLE,
+} IMX_PKE;
+
+typedef enum {
+ IMX_ODE_DISABLE,
+ IMX_ODE_ENABLE,
+} IMX_ODE;
+
+typedef enum {
+ IMX_SPEED_LOW,
+ IMX_SPEED_MEDIUM = 2,
+ IMX_SPEED_MAXIMUM,
+} IMX_SPEED;
+
+typedef enum {
+ IMX_DSE_HIZ,
+ IMX_DSE_260_OHM,
+ IMX_DSE_130_OHM,
+ IMX_DSE_90_OHM,
+ IMX_DSE_60_OHM,
+ IMX_DSE_50_OHM,
+ IMX_DSE_40_OHM,
+ IMX_DSE_33_OHM,
+} IMX_DSE;
+
+typedef enum {
+ IMX_SRE_SLOW,
+ IMX_SRE_FAST,
+} IMX_SRE;
+
+typedef enum {
+ IMX_SION_DISABLED,
+ IMX_SION_ENABLED,
+} IMX_IOMUXC_CTL_SION;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ UINT32 SRE : 1;
+ UINT32 reserved0 : 2;
+ UINT32 DSE : 3;
+ UINT32 SPEED : 2;
+ UINT32 reserved1 : 3;
+ UINT32 ODE : 1 ;
+ UINT32 PKE : 1;
+ UINT32 PUE : 1;
+ UINT32 PUS : 2;
+ UINT32 HYS : 1;
+ UINT32 reserved2 : 15;
+ } Fields;
+} IMX_IOMUXC_PAD_CTL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ UINT32 MUX_MODE : 3;
+ UINT32 reserved0 : 1;
+ UINT32 SION : 1;
+ UINT32 reserved1 : 27;
+ } Fields;
+} IMX_IOMUXC_MUX_CTL;
+
+typedef struct {
+ UINT32 DAISY : 3;
+ UINT32 reserved : 29;
+} IMX_IOMUXC_SEL_INP_CTL;
+
+#define _IMX_SEL_INP_VALUE(InpSel) \
+ (((InpSel) >> 8) & 0x07)
+
+#define _IMX_SEL_INP_REGISTER(InpSel) \
+ ((((InpSel) & 0xFF) * 4) + IOMUXC_SELECT_INPUT_BASE_ADDRESS)
+
+#define _IMX_MAKE_INP_SEL(InpSelReg, InpSelVal) \
+ (((((InpSelReg) - IOMUXC_SELECT_INPUT_BASE_ADDRESS) / 4) & 0xFF) | \
+ (((InpSelVal) & 0x7) << 8))
+
+#define _IMX_MAKE_MUX_CTL(Sion, MuxAlt) \
+ (((MuxAlt) & 0x7) | \
+ (((Sion) & 0x1) << 4))
+
+#define _IMX_MAKE_PAD_CTL(Sre, Dse, Speed, Ode, Pke, Pue, Pus, Hys) \
+ (((Sre) & 0x1) | \
+ (((Dse) & 0x7) << 3) | \
+ (((Speed) & 0x3) << 6) | \
+ (((Ode) & 0x1) << 11) | \
+ (((Pke) & 0x1) << 12) | \
+ (((Pue) & 0x1) << 13) | \
+ (((Pus) & 0x3) << 14) | \
+ (((Hys) & 0x1) << 16))
+
+/**
+ Define a configuration for a pad, including drive settings,
+ MUX setting and Select Input setting and offset.
+
+ Sre - IMX_SRE - Slew Rate setting
+ Dse - IMX_DSE - Drive strength
+ Speed - IMX_SPEED - Pad speed setting
+ Ode - IMX_ODE - Open drain enable
+ Pke - IMX_PKE - Pull/Keeper enable
+ Pue - IMX_PUE - Pull/Keep mode select
+ Pus - IMX_PUS - Pull strength
+ Hys - IMX_HYS - Hysteresis enable/disable
+ Sion - Software Input on Field
+ MuxAlt- Alternate function number
+ SelInpReg - select input register offset div 4
+ SelInpVal - select input value
+
+**/
+#define _IMX_MAKE_PADCFG_INPSEL(Sre, Dse, Speed, Ode, Pke, Pue, Pus, Hys, Sion, MuxAlt, SelInpReg, SelInpValue) \
+ (_IMX_MAKE_PAD_CTL(Sre, Dse, Speed, Ode, Pke, Pue, Pus, Hys) | \
+ (_IMX_MAKE_MUX_CTL(Sion, MuxAlt) << 17) | \
+ (_IMX_MAKE_INP_SEL(SelInpReg, SelInpValue) << 22))
+
+#define _IMX_MAKE_PADCFG(Sre, Dse, Speed, Ode, Pke, Pue, Pus, Hys, Sion, MuxAlt) \
+ (_IMX_MAKE_PAD_CTL(Sre, Dse, Speed, Ode, Pke, Pue, Pus, Hys) | \
+ _IMX_MAKE_MUX_CTL(Sion, MuxAlt) << 17)
+
+#define _IMX_MAKE_PADCFG2(PadCtl, Sion, MuxAlt) \
+ ((PadCtl) | \
+ _IMX_MAKE_MUX_CTL(Sion, MuxAlt) << 17)
+
+#define _IMX_PADCFG_PAD_CTL(PadCfg) ((PadCfg) & 0x0001F8F9)
+#define _IMX_PADCFG_MUX_CTL(PadCfg) (((PadCfg) >> 17) & 0x00000017)
+#define _IMX_PADCFG_SEL_INP(PadCfg) (((PadCfg) >> 22) & 0x000007FF)
+
+/**
+ Put a pad in the specified configuration.
+
+ For example, to configure GPIO0 as CCM_CLK01 output:
+ ImxPadConfig (IMX_PAD_GPIO_0, IMX_PAD_GPIO_0_CCM_CLKO1);
+
+**/
+VOID ImxPadConfig (IMX_PAD Pad, IMX_PADCFG PadConfig);
+
+/**
+ Dumps to console the specified PAD mux/control configuration.
+**/
+VOID ImxPadDumpConfig (char *PadName, IMX_PAD Pad);
+
+#endif // _IMX6_IOMUX_H_
diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6IoMux_DQ.h b/Silicon/NXP/iMX6Pkg/Include/iMX6IoMux_DQ.h
new file mode 100644
index 000000000000..33b79926fbba
--- /dev/null
+++ b/Silicon/NXP/iMX6Pkg/Include/iMX6IoMux_DQ.h
@@ -0,0 +1,2464 @@
+/** @file
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _IMX6_IOMUX_DQ_H_
+#define _IMX6_IOMUX_DQ_H_
+
+//
+// SELECT INPUT defines
+
+#define EIM_DATA21_ALT6 0x0 // Selecting ALT6 mode of pad EIM_D21 for I2C1_SCL
+#define CSI0_DAT9_ALT4 0x1 // Selecting ALT4 mode of pad CSI0_DAT9 for I2C1_SCL
+
+#define EIM_DATA28_ALT1 0x0 // Selecting ALT1 mode of pad EIM_D28 for I2C1_SDA
+#define CSI0_DAT8_ALT4 0x1 // Selecting ALT4 mode of pad CSI0_DAT8 for I2C1_SDA
+
+#define EIM_EB2_B_ALT6 0x0 // Selecting ALT6 mode of pad EIM_EB2 for I2C2_SCL
+#define KEY_COL3_ALT4 0x1 // Selecting ALT4 mode of pad KEY_COL3 for I2C2_SCL
+
+#define EIM_DATA16_ALT6 0x0 // Selecting ALT6 mode of pad EIM_D16 for I2C2_SDA
+#define KEY_ROW3_ALT4 0x1 // Selecting ALT4 mode of pad KEY_ROW3 for I2C2_SDA
+
+#define EIM_DATA17_ALT6 0x0 // Selecting ALT6 mode of pad EIM_D17 for I2C3_SCL
+#define GPIO03_ALT2 0x1 // Selecting ALT2 mode of pad GPIO_3 for I2C3_SCL
+#define GPIO05_ALT6 0x2 // Selecting ALT6 mode of pad GPIO_5 for I2C3_SCL
+
+#define EIM_DATA18_ALT6 0x0 // Selecting ALT6 mode of pad EIM_D18 for I2C3_SDA
+#define GPIO06_ALT2 0x1 // Selecting ALT2 mode of pad GPIO_6 for I2C3_SDA
+#define GPIO16_ALT6 0x2 // Selecting ALT6 mode of pad GPIO_16 for I2C3_SDA
+
+#define DISP0_DATA19_ALT3 0
+#define KEY_ROW1_ALT2 1
+
+#define DISP0_DATA17_ALT3 0
+#define KEY_ROW0_ALT2 1
+
+#define DISP0_DATA16_ALT3 0
+#define KEY_COL0_ALT2 1
+
+#define DISP0_DATA18_ALT3 0
+#define KEY_COL1_ALT2 1
+
+#define EIM_DATA21_ALT4 0
+#define KEY_COL4_ALT2 1
+
+#define EIM_DATA30_ALT6 0
+#define GPIO03_ALT6 1
+
+#define RGMII_TX_CTL_ALT7 0
+#define GPIO16_ALT2 1
+
+#define CSI0_DATA10_ALT3 0 // Selecting ALT3 mode of pad CSI0_DAT10 for UART1_TX_DATA.
+#define CSI0_DATA11_ALT3 1 // Selecting ALT3 mode of pad CSI0_DAT11 for UART1_RX_DATA.
+#define SD3_DATA7_ALT1 2 // Selecting ALT1 mode of pad SD3_DAT7 for UART1_TX_DATA.
+#define SD3_DATA6_ALT1 3 // Selecting ALT1 mode of pad SD3_DAT6 for UART1_RX_DATA.
+
+#define EIM_DATA26_ALT4 0 // Selecting ALT4 mode of pad EIM_D26 for UART2_TX_DATA.
+#define EIM_DATA27_ALT4 1 // Selecting ALT4 mode of pad EIM_D27 for UART2_RX_DATA.
+#define GPIO07_ALT4 2 // Selecting ALT4 mode of pad GPIO_7 for UART2_TX_DATA.
+#define GPIO08_ALT4 3 // Selecting ALT4 mode of pad GPIO_8 for UART2_RX_DATA.
+#define SD3_DATA5_ALT1 4 // Selecting ALT1 mode of pad SD3_DAT5 for UART2_TX_DATA.
+#define SD3_DATA4_ALT1 5 // Selecting ALT1 mode of pad SD3_DAT4 for UART2_RX_DATA.
+#define SD4_DATA4_ALT2 6 // Selecting ALT2 mode of pad SD4_DAT4 for UART2_RX_DATA.
+#define SD4_DATA7_ALT2 7 // Selecting ALT2 mode of pad SD4_DAT7 for UART2_TX_DATA.
+
+#define EIM_DATA24_ALT2 0 // Selecting ALT2 mode of pad EIM_D24 for UART3_TX_DATA.
+#define EIM_DATA25_ALT2 1 // Selecting ALT2 mode of pad EIM_D25 for UART3_RX_DATA.
+#define SD4_CMD_ALT2 2 // Selecting ALT2 mode of pad SD4_CMD for UART3_TX_DATA.
+#define SD4_CLK_ALT2 3 // Selecting ALT2 mode of pad SD4_CLK for UART3_RX_DATA.
+
+
+//
+// AUD5 select input register defines.
+//
+typedef enum {
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO00)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO00)
+ IMX_PAD_GPIO_0 = _IMX_PAD(0x5F0, 0x220), // CCM_CLKO1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO01)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO01)
+ IMX_PAD_GPIO_1 = _IMX_PAD(0x5F4, 0x224), // ESAI_RX_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO02)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO02)
+ IMX_PAD_GPIO_2 = _IMX_PAD(0x604, 0x234), // ESAI_TX_FS
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO03)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO03)
+ IMX_PAD_GPIO_3 = _IMX_PAD(0x5FC, 0x22C), // ESAI_RX_HF_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO04)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO04)
+ IMX_PAD_GPIO_4 = _IMX_PAD(0x608, 0x238), // ESAI_TX_HF_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO05)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO05)
+ IMX_PAD_GPIO_5 = _IMX_PAD(0x60C, 0x23C), // ESAI_TX2_RX3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO06)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO06)
+ IMX_PAD_GPIO_6 = _IMX_PAD(0x600, 0x230), // ESAI_TX_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO07)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO07)
+ IMX_PAD_GPIO_7 = _IMX_PAD(0x610, 0x240), // ESAI_TX4_RX1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO08)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO08)
+ IMX_PAD_GPIO_8 = _IMX_PAD(0x614, 0x244), // ESAI_TX5_RX0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO09)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO09)
+ IMX_PAD_GPIO_9 = _IMX_PAD(0x5F8, 0x228), // ESAI_RX_FS
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_CLK)
+ IMX_PAD_SD2_CLK = _IMX_PAD(0x73C, 0x354), // SD2_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_CMD)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_CMD)
+ IMX_PAD_SD2_CMD = _IMX_PAD(0x740, 0x358), // SD2_CMD
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3)
+ IMX_PAD_SD2_DAT3 = _IMX_PAD(0x744, 0x35C), // SD2_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2)
+ IMX_PAD_SD2_DAT2 = _IMX_PAD(0x364, 0x50), // SD2_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1)
+ IMX_PAD_SD2_DAT1 = _IMX_PAD(0x360, 0x4C), // SD2_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0)
+ IMX_PAD_SD2_DAT0 = _IMX_PAD(0x368, 0x54), // SD2_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0)
+ IMX_PAD_SD1_DAT0 = _IMX_PAD(0x728, 0x340), // SD1_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1)
+ IMX_PAD_SD1_DAT1 = _IMX_PAD(0x724, 0x33C), // SD1_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_CMD)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_CMD)
+ IMX_PAD_SD1_CMD = _IMX_PAD(0x730, 0x348), // SD1_CMD
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2)
+ IMX_PAD_SD1_DAT2 = _IMX_PAD(0x734, 0x34C), // SD1_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_CLK)
+ IMX_PAD_SD1_CLK = _IMX_PAD(0x738, 0x350), // SD1_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3)
+ IMX_PAD_SD1_DAT3 = _IMX_PAD(0x72C, 0x344), // SD1_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO)
+ IMX_PAD_ENET_MDIO = _IMX_PAD(0x4E4, 0x1D0), // ENET_MDIO
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK)
+ IMX_PAD_ENET_REF_CLK = _IMX_PAD(0x4E8, 0x1D4), // ENET_TX_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER)
+ IMX_PAD_ENET_RX_ER = _IMX_PAD(0x4EC, 0x1D8), // USB_OTG_ID
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV)
+ IMX_PAD_ENET_CRS_DV = _IMX_PAD(0x4F0, 0x1DC), // ENET_RX_EN
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1)
+ IMX_PAD_ENET_RXD1 = _IMX_PAD(0x4F4, 0x1E0), // MLB_SIG
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0)
+ IMX_PAD_ENET_RXD0 = _IMX_PAD(0x4F8, 0x1E4), // XTALOSC_OSC32K_32K_OUT
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN)
+ IMX_PAD_ENET_TX_EN = _IMX_PAD(0x4FC, 0x1E8), // ENET_TX_EN
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1)
+ IMX_PAD_ENET_TXD1 = _IMX_PAD(0x500, 0x1EC), // MLB_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0)
+ IMX_PAD_ENET_TXD0 = _IMX_PAD(0x504, 0x1F0), // ENET_TX_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_MDC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_MDC)
+ IMX_PAD_ENET_MDC = _IMX_PAD(0x508, 0x1F4), // MLB_DATA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00)
+ IMX_PAD_NANDF_D0 = _IMX_PAD(0x6E4, 0x2FC), // NAND_DATA00
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01)
+ IMX_PAD_NANDF_D1 = _IMX_PAD(0x6E8, 0x300), // NAND_DATA01
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02)
+ IMX_PAD_NANDF_D2 = _IMX_PAD(0x6EC, 0x304), // NAND_DATA02
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03)
+ IMX_PAD_NANDF_D3 = _IMX_PAD(0x6F0, 0x308), // NAND_DATA03
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04)
+ IMX_PAD_NANDF_D4 = _IMX_PAD(0x6F4, 0x30C), // NAND_DATA04
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05)
+ IMX_PAD_NANDF_D5 = _IMX_PAD(0x6F8, 0x310), // NAND_DATA05
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06)
+ IMX_PAD_NANDF_D6 = _IMX_PAD(0x6FC, 0x314), // NAND_DATA06
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07)
+ IMX_PAD_NANDF_D7 = _IMX_PAD(0x700, 0x318), // NAND_DATA07
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0)
+ IMX_PAD_SD4_DAT0 = _IMX_PAD(0x704, 0x31C), // SD4_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1)
+ IMX_PAD_SD4_DAT1 = _IMX_PAD(0x708, 0x320), // SD4_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2)
+ IMX_PAD_SD4_DAT2 = _IMX_PAD(0x70C, 0x324), // SD4_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3)
+ IMX_PAD_SD4_DAT3 = _IMX_PAD(0x710, 0x328), // SD4_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4)
+ IMX_PAD_SD4_DAT4 = _IMX_PAD(0x714, 0x32C), // SD4_DATA4
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5)
+ IMX_PAD_SD4_DAT5 = _IMX_PAD(0x718, 0x330), // SD4_DATA5
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6)
+ IMX_PAD_SD4_DAT6 = _IMX_PAD(0x71C, 0x334), // SD4_DATA6
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7)
+ IMX_PAD_SD4_DAT7 = _IMX_PAD(0x720, 0x338), // SD4_DATA7
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22)
+ IMX_PAD_EIM_A22 = _IMX_PAD(0x3F0, 0xDC), // EIM_ADDR22
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21)
+ IMX_PAD_EIM_A21 = _IMX_PAD(0x3F4, 0xE0), // EIM_ADDR21
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20)
+ IMX_PAD_EIM_A20 = _IMX_PAD(0x3F8, 0xE4), // EIM_ADDR20
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19)
+ IMX_PAD_EIM_A19 = _IMX_PAD(0x3FC, 0xE8), // EIM_ADDR19
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18)
+ IMX_PAD_EIM_A18 = _IMX_PAD(0x400, 0xEC), // EIM_ADDR18
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17)
+ IMX_PAD_EIM_A17 = _IMX_PAD(0x404, 0xF0), // EIM_ADDR17
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16)
+ IMX_PAD_EIM_A16 = _IMX_PAD(0x408, 0xF4), // EIM_ADDR16
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B)
+ IMX_PAD_EIM_CS0 = _IMX_PAD(0x40C, 0xF8), // EIM_CS0_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B)
+ IMX_PAD_EIM_CS1 = _IMX_PAD(0x410, 0xFC), // EIM_CS1_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B)
+ IMX_PAD_EIM_OE = _IMX_PAD(0x414, 0x100), // EIM_OE_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_RW)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_RW)
+ IMX_PAD_EIM_RW = _IMX_PAD(0x418, 0x104), // EIM_RW
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B)
+ IMX_PAD_EIM_LBA = _IMX_PAD(0x41C, 0x108), // EIM_LBA_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_B)
+ IMX_PAD_EIM_EB0 = _IMX_PAD(0x420, 0x10C), // EIM_EB0_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_B)
+ IMX_PAD_EIM_EB1 = _IMX_PAD(0x424, 0x110), // EIM_EB1_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_B)
+ IMX_PAD_EIM_EB2 = _IMX_PAD(0x3A0, 0x8C), // EIM_EB2_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_B)
+ IMX_PAD_EIM_EB3 = _IMX_PAD(0x3C4, 0xB0), // EIM_EB3_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD00)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD00)
+ IMX_PAD_EIM_DA0 = _IMX_PAD(0x428, 0x114), // EIM_AD00
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD01)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD01)
+ IMX_PAD_EIM_DA1 = _IMX_PAD(0x42C, 0x118), // EIM_AD01
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD02)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD02)
+ IMX_PAD_EIM_DA2 = _IMX_PAD(0x430, 0x11C), // EIM_AD02
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD03)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD03)
+ IMX_PAD_EIM_DA3 = _IMX_PAD(0x434, 0x120), // EIM_AD03
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD04)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD04)
+ IMX_PAD_EIM_DA4 = _IMX_PAD(0x438, 0x124), // EIM_AD04
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD05)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD05)
+ IMX_PAD_EIM_DA5 = _IMX_PAD(0x43C, 0x128), // EIM_AD05
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD06)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD06)
+ IMX_PAD_EIM_DA6 = _IMX_PAD(0x440, 0x12C), // EIM_AD06
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD07)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD07)
+ IMX_PAD_EIM_DA7 = _IMX_PAD(0x444, 0x130), // EIM_AD07
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD08)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD08)
+ IMX_PAD_EIM_DA8 = _IMX_PAD(0x448, 0x134), // EIM_AD08
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD09)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD09)
+ IMX_PAD_EIM_DA9 = _IMX_PAD(0x44C, 0x138), // EIM_AD09
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD10)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD10)
+ IMX_PAD_EIM_DA10 = _IMX_PAD(0x450, 0x13C), // EIM_AD10
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD11)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD11)
+ IMX_PAD_EIM_DA11 = _IMX_PAD(0x454, 0x140), // EIM_AD11
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD12)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD12)
+ IMX_PAD_EIM_DA12 = _IMX_PAD(0x458, 0x144), // EIM_AD12
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD13)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD13)
+ IMX_PAD_EIM_DA13 = _IMX_PAD(0x45C, 0x148), // EIM_AD13
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD14)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD14)
+ IMX_PAD_EIM_DA14 = _IMX_PAD(0x460, 0x14C), // EIM_AD14
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD15)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD15)
+ IMX_PAD_EIM_DA15 = _IMX_PAD(0x464, 0x150), // EIM_AD15
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16)
+ IMX_PAD_EIM_D16 = _IMX_PAD(0x3A4, 0x90), // EIM_DATA16
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17)
+ IMX_PAD_EIM_D17 = _IMX_PAD(0x3A8, 0x94), // EIM_DATA17
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18)
+ IMX_PAD_EIM_D18 = _IMX_PAD(0x3AC, 0x98), // EIM_DATA18
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19)
+ IMX_PAD_EIM_D19 = _IMX_PAD(0x3B0, 0x9C), // EIM_DATA19
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20)
+ IMX_PAD_EIM_D20 = _IMX_PAD(0x3B4, 0xA0), // EIM_DATA20
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21)
+ IMX_PAD_EIM_D21 = _IMX_PAD(0x3B8, 0xA4), // EIM_DATA21
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22)
+ IMX_PAD_EIM_D22 = _IMX_PAD(0x3BC, 0xA8), // EIM_DATA22
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23)
+ IMX_PAD_EIM_D23 = _IMX_PAD(0x3C0, 0xAC), // EIM_DATA23
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24)
+ IMX_PAD_EIM_D24 = _IMX_PAD(0x3C8, 0xB4), // EIM_DATA24
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25)
+ IMX_PAD_EIM_D25 = _IMX_PAD(0x3CC, 0xB8), // EIM_DATA25
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26)
+ IMX_PAD_EIM_D26 = _IMX_PAD(0x3D0, 0xBC), // EIM_DATA26
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27)
+ IMX_PAD_EIM_D27 = _IMX_PAD(0x3D4, 0xC0), // EIM_DATA27
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28)
+ IMX_PAD_EIM_D28 = _IMX_PAD(0x3D8, 0xC4), // EIM_DATA28
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29)
+ IMX_PAD_EIM_D29 = _IMX_PAD(0x3DC, 0xC8), // EIM_DATA29
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30)
+ IMX_PAD_EIM_D30 = _IMX_PAD(0x3E0, 0xCC), // EIM_DATA30
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31)
+ IMX_PAD_EIM_D31 = _IMX_PAD(0x3E4, 0xD0), // EIM_DATA31
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO19)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO19)
+ IMX_PAD_GPIO_19 = _IMX_PAD(0x624, 0x254), // KEY_COL5
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL0)
+ IMX_PAD_KEY_COL0 = _IMX_PAD(0x5C8, 0x1F8), // ECSPI1_SCLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0)
+ IMX_PAD_KEY_ROW0 = _IMX_PAD(0x5CC, 0x1FC), // ECSPI1_MOSI
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL1)
+ IMX_PAD_KEY_COL1 = _IMX_PAD(0x5D0, 0x200), // ECSPI1_MISO
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1)
+ IMX_PAD_KEY_ROW1 = _IMX_PAD(0x5D4, 0x204), // ECSPI1_SS0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL2)
+ IMX_PAD_KEY_COL2 = _IMX_PAD(0x5D8, 0x208), // ECSPI1_SS1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2)
+ IMX_PAD_KEY_ROW2 = _IMX_PAD(0x5DC, 0x20C), // ECSPI1_SS2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL3)
+ IMX_PAD_KEY_COL3 = _IMX_PAD(0x5E0, 0x210), // ECSPI1_SS3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3)
+ IMX_PAD_KEY_ROW3 = _IMX_PAD(0x5E4, 0x214), // XTALOSC_OSC32K_32K_OUT
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL4)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL4)
+ IMX_PAD_KEY_COL4 = _IMX_PAD(0x5E8, 0x218), // FLEXCAN2_TX
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4)
+ IMX_PAD_KEY_ROW4 = _IMX_PAD(0x5EC, 0x21C), // FLEXCAN2_RX
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK)
+ IMX_PAD_DI0_DISP_CLK = _IMX_PAD(0x470, 0x15C), // IPU1_DI0_DISP_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15)
+ IMX_PAD_DI0_PIN15 = _IMX_PAD(0x474, 0x160), // IPU1_DI0_PIN15
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02)
+ IMX_PAD_DI0_PIN2 = _IMX_PAD(0x478, 0x164), // IPU1_DI0_PIN02
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03)
+ IMX_PAD_DI0_PIN3 = _IMX_PAD(0x47C, 0x168), // IPU1_DI0_PIN03
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04)
+ IMX_PAD_DI0_PIN4 = _IMX_PAD(0x480, 0x16C), // IPU1_DI0_PIN04
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00)
+ IMX_PAD_DISP0_DAT0 = _IMX_PAD(0x484, 0x170), // IPU1_DISP0_DATA00
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01)
+ IMX_PAD_DISP0_DAT1 = _IMX_PAD(0x488, 0x174), // IPU1_DISP0_DATA01
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02)
+ IMX_PAD_DISP0_DAT2 = _IMX_PAD(0x48C, 0x178), // IPU1_DISP0_DATA02
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03)
+ IMX_PAD_DISP0_DAT3 = _IMX_PAD(0x490, 0x17C), // IPU1_DISP0_DATA03
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04)
+ IMX_PAD_DISP0_DAT4 = _IMX_PAD(0x494, 0x180), // IPU1_DISP0_DATA04
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05)
+ IMX_PAD_DISP0_DAT5 = _IMX_PAD(0x498, 0x184), // IPU1_DISP0_DATA05
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06)
+ IMX_PAD_DISP0_DAT6 = _IMX_PAD(0x49C, 0x188), // IPU1_DISP0_DATA06
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07)
+ IMX_PAD_DISP0_DAT7 = _IMX_PAD(0x4A0, 0x18C), // IPU1_DISP0_DATA07
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08)
+ IMX_PAD_DISP0_DAT8 = _IMX_PAD(0x4A4, 0x190), // IPU1_DISP0_DATA08
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09)
+ IMX_PAD_DISP0_DAT9 = _IMX_PAD(0x4A8, 0x194), // IPU1_DISP0_DATA09
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10)
+ IMX_PAD_DISP0_DAT10 = _IMX_PAD(0x4AC, 0x198), // IPU1_DISP0_DATA10
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B)
+ IMX_PAD_EIM_WAIT = _IMX_PAD(0x468, 0x154), // EIM_WAIT_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25)
+ IMX_PAD_EIM_A25 = _IMX_PAD(0x39C, 0x88), // EIM_ADDR25
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24)
+ IMX_PAD_EIM_A24 = _IMX_PAD(0x3E8, 0xD4), // EIM_ADDR24
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11)
+ IMX_PAD_DISP0_DAT11 = _IMX_PAD(0x4B0, 0x19C), // IPU1_DISP0_DATA11
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12)
+ IMX_PAD_DISP0_DAT12 = _IMX_PAD(0x4B4, 0x1A0), // IPU1_DISP0_DATA12
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13)
+ IMX_PAD_DISP0_DAT13 = _IMX_PAD(0x4B8, 0x1A4), // IPU1_DISP0_DATA13
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14)
+ IMX_PAD_DISP0_DAT14 = _IMX_PAD(0x4BC, 0x1A8), // IPU1_DISP0_DATA14
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15)
+ IMX_PAD_DISP0_DAT15 = _IMX_PAD(0x4C0, 0x1AC), // IPU1_DISP0_DATA15
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16)
+ IMX_PAD_DISP0_DAT16 = _IMX_PAD(0x4C4, 0x1B0), // IPU1_DISP0_DATA16
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17)
+ IMX_PAD_DISP0_DAT17 = _IMX_PAD(0x4C8, 0x1B4), // IPU1_DISP0_DATA17
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18)
+ IMX_PAD_DISP0_DAT18 = _IMX_PAD(0x4CC, 0x1B8), // IPU1_DISP0_DATA18
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19)
+ IMX_PAD_DISP0_DAT19 = _IMX_PAD(0x4D0, 0x1BC), // IPU1_DISP0_DATA19
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20)
+ IMX_PAD_DISP0_DAT20 = _IMX_PAD(0x4D4, 0x1C0), // IPU1_DISP0_DATA20
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21)
+ IMX_PAD_DISP0_DAT21 = _IMX_PAD(0x4D8, 0x1C4), // IPU1_DISP0_DATA21
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22)
+ IMX_PAD_DISP0_DAT22 = _IMX_PAD(0x4DC, 0x1C8), // IPU1_DISP0_DATA22
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23)
+ IMX_PAD_DISP0_DAT23 = _IMX_PAD(0x4E0, 0x1CC), // IPU1_DISP0_DATA23
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK)
+ IMX_PAD_CSI0_PIXCLK = _IMX_PAD(0x628, 0x258), // IPU1_CSI0_PIXCLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC)
+ IMX_PAD_CSI0_MCLK = _IMX_PAD(0x62C, 0x25C), // IPU1_CSI0_HSYNC
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN)
+ IMX_PAD_CSI0_DATA_EN = _IMX_PAD(0x630, 0x260), // IPU1_CSI0_DATA_EN
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC)
+ IMX_PAD_CSI0_VSYNC = _IMX_PAD(0x634, 0x264), // IPU1_CSI0_VSYNC
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04)
+ IMX_PAD_CSI0_DAT4 = _IMX_PAD(0x638, 0x268), // IPU1_CSI0_DATA04
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05)
+ IMX_PAD_CSI0_DAT5 = _IMX_PAD(0x63C, 0x26C), // IPU1_CSI0_DATA05
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06)
+ IMX_PAD_CSI0_DAT6 = _IMX_PAD(0x640, 0x270), // IPU1_CSI0_DATA06
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07)
+ IMX_PAD_CSI0_DAT7 = _IMX_PAD(0x644, 0x274), // IPU1_CSI0_DATA07
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08)
+ IMX_PAD_CSI0_DAT8 = _IMX_PAD(0x648, 0x278), // IPU1_CSI0_DATA08
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09)
+ IMX_PAD_CSI0_DAT9 = _IMX_PAD(0x64C, 0x27C), // IPU1_CSI0_DATA09
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10)
+ IMX_PAD_CSI0_DAT10 = _IMX_PAD(0x650, 0x280), // IPU1_CSI0_DATA10
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11)
+ IMX_PAD_CSI0_DAT11 = _IMX_PAD(0x654, 0x284), // IPU1_CSI0_DATA11
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12)
+ IMX_PAD_CSI0_DAT12 = _IMX_PAD(0x658, 0x288), // IPU1_CSI0_DATA12
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13)
+ IMX_PAD_CSI0_DAT13 = _IMX_PAD(0x65C, 0x28C), // IPU1_CSI0_DATA13
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14)
+ IMX_PAD_CSI0_DAT14 = _IMX_PAD(0x660, 0x290), // IPU1_CSI0_DATA14
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15)
+ IMX_PAD_CSI0_DAT15 = _IMX_PAD(0x664, 0x294), // IPU1_CSI0_DATA15
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16)
+ IMX_PAD_CSI0_DAT16 = _IMX_PAD(0x668, 0x298), // IPU1_CSI0_DATA16
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17)
+ IMX_PAD_CSI0_DAT17 = _IMX_PAD(0x66C, 0x29C), // IPU1_CSI0_DATA17
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18)
+ IMX_PAD_CSI0_DAT18 = _IMX_PAD(0x670, 0x2A0), // IPU1_CSI0_DATA18
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19)
+ IMX_PAD_CSI0_DAT19 = _IMX_PAD(0x674, 0x2A4), // IPU1_CSI0_DATA19
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23)
+ IMX_PAD_EIM_A23 = _IMX_PAD(0x3EC, 0xD8), // EIM_ADDR23
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CLE)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CLE)
+ IMX_PAD_NANDF_CLE = _IMX_PAD(0x6BC, 0x2D4), // NAND_CLE
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_ALE)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_ALE)
+ IMX_PAD_NANDF_ALE = _IMX_PAD(0x6C0, 0x2D8), // NAND_ALE
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B)
+ IMX_PAD_NANDF_WP_B = _IMX_PAD(0x6C4, 0x2DC), // NAND_WP_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B)
+ IMX_PAD_NANDF_RB0 = _IMX_PAD(0x6C8, 0x2E0), // NAND_READY_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B)
+ IMX_PAD_NANDF_CS0 = _IMX_PAD(0x6CC, 0x2E4), // NAND_CE0_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B)
+ IMX_PAD_NANDF_CS1 = _IMX_PAD(0x6D0, 0x2E8), // NAND_CE1_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B)
+ IMX_PAD_NANDF_CS2 = _IMX_PAD(0x6D4, 0x2EC), // NAND_CE2_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B)
+ IMX_PAD_NANDF_CS3 = _IMX_PAD(0x6D8, 0x2F0), // NAND_CE3_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7)
+ IMX_PAD_SD3_DAT7 = _IMX_PAD(0x690, 0x2A8), // SD3_DATA7
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6)
+ IMX_PAD_SD3_DAT6 = _IMX_PAD(0x694, 0x2AC), // SD3_DATA6
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC)
+ IMX_PAD_RGMII_TXC = _IMX_PAD(0x36C, 0x58), // USB_H2_DATA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0)
+ IMX_PAD_RGMII_TD0 = _IMX_PAD(0x370, 0x5C), // HSI_TX_READY
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1)
+ IMX_PAD_RGMII_TD1 = _IMX_PAD(0x374, 0x60), // HSI_RX_FLAG
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2)
+ IMX_PAD_RGMII_TD2 = _IMX_PAD(0x378, 0x64), // HSI_RX_DATA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3)
+ IMX_PAD_RGMII_TD3 = _IMX_PAD(0x37C, 0x68), // HSI_RX_WAKE
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL)
+ IMX_PAD_RGMII_RX_CTL = _IMX_PAD(0x380, 0x6C), // USB_H3_DATA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0)
+ IMX_PAD_RGMII_RD0 = _IMX_PAD(0x384, 0x70), // HSI_RX_READY
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL)
+ IMX_PAD_RGMII_TX_CTL = _IMX_PAD(0x388, 0x74), // USB_H2_STROBE
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1)
+ IMX_PAD_RGMII_RD1 = _IMX_PAD(0x38C, 0x78), // HSI_TX_FLAG
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2)
+ IMX_PAD_RGMII_RD2 = _IMX_PAD(0x390, 0x7C), // HSI_TX_DATA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3)
+ IMX_PAD_RGMII_RD3 = _IMX_PAD(0x394, 0x80), // HSI_TX_WAKE
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC)
+ IMX_PAD_RGMII_RXC = _IMX_PAD(0x398, 0x84), // USB_H3_STROBE
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK)
+ IMX_PAD_EIM_BCLK = _IMX_PAD(0x46C, 0x158), // EIM_BCLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5)
+ IMX_PAD_SD3_DAT5 = _IMX_PAD(0x698, 0x2B0), // SD3_DATA5
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4)
+ IMX_PAD_SD3_DAT4 = _IMX_PAD(0x69C, 0x2B4), // SD3_DATA4
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_CMD)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_CMD)
+ IMX_PAD_SD3_CMD = _IMX_PAD(0x6A0, 0x2B8), // SD3_CMD
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_CLK)
+ IMX_PAD_SD3_CLK = _IMX_PAD(0x6A4, 0x2BC), // SD3_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0)
+ IMX_PAD_SD3_DAT0 = _IMX_PAD(0x6A8, 0x2C0), // SD3_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1)
+ IMX_PAD_SD3_DAT1 = _IMX_PAD(0x6AC, 0x2C4), // SD3_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2)
+ IMX_PAD_SD3_DAT2 = _IMX_PAD(0x6B0, 0x2C8), // SD3_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3)
+ IMX_PAD_SD3_DAT3 = _IMX_PAD(0x6B4, 0x2CC), // SD3_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_RESET)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_RESET)
+ IMX_PAD_SD3_RST = _IMX_PAD(0x6B8, 0x2D0), // SD3_RESET
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_CMD)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_CMD)
+ IMX_PAD_SD4_CMD = _IMX_PAD(0x6DC, 0x2F4), // SD4_CMD
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_CLK)
+ IMX_PAD_SD4_CLK = _IMX_PAD(0x6E0, 0x2F8), // SD4_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO16)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO16)
+ IMX_PAD_GPIO_16 = _IMX_PAD(0x618, 0x248), // ESAI_TX3_RX2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO17)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO17)
+ IMX_PAD_GPIO_17 = _IMX_PAD(0x61C, 0x24C), // ESAI_TX0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO18)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO18)
+ IMX_PAD_GPIO_18 = _IMX_PAD(0x620, 0x250), // ESAI_TX1
+} IMX_PAD;
+
+//
+// Alternate function numbers
+//
+
+typedef enum {
+ IMX_IOMUXC_GPIO_0_ALT0_CCM_CLKO1 = 0,
+ IMX_IOMUXC_GPIO_0_ALT2_KEY_COL5 = 2,
+ IMX_IOMUXC_GPIO_0_ALT3_ASRC_EXT_CLK = 3,
+ IMX_IOMUXC_GPIO_0_ALT4_EPIT1_OUT = 4,
+ IMX_IOMUXC_GPIO_0_ALT5_GPIO1_IO00 = 5,
+ IMX_IOMUXC_GPIO_0_ALT6_USB_H1_PWR = 6,
+ IMX_IOMUXC_GPIO_0_ALT7_SNVS_VIO_5 = 7,
+} IMX_IOMUXC_GPIO_0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_1_ALT0_ESAI_RX_CLK = 0,
+ IMX_IOMUXC_GPIO_1_ALT1_WDOG2_B = 1,
+ IMX_IOMUXC_GPIO_1_ALT2_KEY_ROW5 = 2,
+ IMX_IOMUXC_GPIO_1_ALT3_USB_OTG_ID = 3,
+ IMX_IOMUXC_GPIO_1_ALT4_PWM2_OUT = 4,
+ IMX_IOMUXC_GPIO_1_ALT5_GPIO1_IO01 = 5,
+ IMX_IOMUXC_GPIO_1_ALT6_SD1_CD_B = 6,
+} IMX_IOMUXC_GPIO_1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_2_ALT0_ESAI_TX_FS = 0,
+ IMX_IOMUXC_GPIO_2_ALT2_KEY_ROW6 = 2,
+ IMX_IOMUXC_GPIO_2_ALT5_GPIO1_IO02 = 5,
+ IMX_IOMUXC_GPIO_2_ALT6_SD2_WP = 6,
+ IMX_IOMUXC_GPIO_2_ALT7_MLB_DATA = 7,
+} IMX_IOMUXC_GPIO_2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_3_ALT0_ESAI_RX_HF_CLK = 0,
+ IMX_IOMUXC_GPIO_3_ALT2_I2C3_SCL = 2,
+ IMX_IOMUXC_GPIO_3_ALT3_XTALOSC_REF_CLK_24M = 3,
+ IMX_IOMUXC_GPIO_3_ALT4_CCM_CLKO2 = 4,
+ IMX_IOMUXC_GPIO_3_ALT5_GPIO1_IO03 = 5,
+ IMX_IOMUXC_GPIO_3_ALT6_USB_H1_OC = 6,
+ IMX_IOMUXC_GPIO_3_ALT7_MLB_CLK = 7,
+} IMX_IOMUXC_GPIO_3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_4_ALT0_ESAI_TX_HF_CLK = 0,
+ IMX_IOMUXC_GPIO_4_ALT2_KEY_COL7 = 2,
+ IMX_IOMUXC_GPIO_4_ALT5_GPIO1_IO04 = 5,
+ IMX_IOMUXC_GPIO_4_ALT6_SD2_CD_B = 6,
+} IMX_IOMUXC_GPIO_4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_5_ALT0_ESAI_TX2_RX3 = 0,
+ IMX_IOMUXC_GPIO_5_ALT2_KEY_ROW7 = 2,
+ IMX_IOMUXC_GPIO_5_ALT3_CCM_CLKO1 = 3,
+ IMX_IOMUXC_GPIO_5_ALT5_GPIO1_IO05 = 5,
+ IMX_IOMUXC_GPIO_5_ALT6_I2C3_SCL = 6,
+ IMX_IOMUXC_GPIO_5_ALT7_ARM_EVENTI = 7,
+} IMX_IOMUXC_GPIO_5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_6_ALT0_ESAI_TX_CLK = 0,
+ IMX_IOMUXC_GPIO_6_ALT1 = 1,
+ IMX_IOMUXC_GPIO_6_ALT2_I2C3_SDA = 2,
+ IMX_IOMUXC_GPIO_6_ALT5_GPIO1_IO06 = 5,
+ IMX_IOMUXC_GPIO_6_ALT6_SD2_LCTL = 6,
+ IMX_IOMUXC_GPIO_6_ALT7_MLB_SIG = 7,
+} IMX_IOMUXC_GPIO_6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_7_ALT0_ESAI_TX4_RX1 = 0,
+ IMX_IOMUXC_GPIO_7_ALT1_ECSPI5_RDY = 1,
+ IMX_IOMUXC_GPIO_7_ALT2_EPIT1_OUT = 2,
+ IMX_IOMUXC_GPIO_7_ALT3_FLEXCAN1_TX = 3,
+ IMX_IOMUXC_GPIO_7_ALT4_UART2_TX_DATA = 4,
+ IMX_IOMUXC_GPIO_7_ALT5_GPIO1_IO07 = 5,
+ IMX_IOMUXC_GPIO_7_ALT6_SPDIF_LOCK = 6,
+ IMX_IOMUXC_GPIO_7_ALT7_USB_OTG_HOST_MODE = 7,
+} IMX_IOMUXC_GPIO_7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_8_ALT0_ESAI_TX5_RX0 = 0,
+ IMX_IOMUXC_GPIO_8_ALT1_XTALOSC_REF_CLK_32K = 1,
+ IMX_IOMUXC_GPIO_8_ALT2_EPIT2_OUT = 2,
+ IMX_IOMUXC_GPIO_8_ALT3_FLEXCAN1_RX = 3,
+ IMX_IOMUXC_GPIO_8_ALT4_UART2_RX_DATA = 4,
+ IMX_IOMUXC_GPIO_8_ALT5_GPIO1_IO08 = 5,
+ IMX_IOMUXC_GPIO_8_ALT6_SPDIF_SR_CLK = 6,
+ IMX_IOMUXC_GPIO_8_ALT7_USB_OTG_PWR_CTL_WAKE = 7,
+} IMX_IOMUXC_GPIO_8_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_9_ALT0_ESAI_RX_FS = 0,
+ IMX_IOMUXC_GPIO_9_ALT1_WDOG1_B = 1,
+ IMX_IOMUXC_GPIO_9_ALT2_KEY_COL6 = 2,
+ IMX_IOMUXC_GPIO_9_ALT3_CCM_REF_EN_B = 3,
+ IMX_IOMUXC_GPIO_9_ALT4_PWM1_OUT = 4,
+ IMX_IOMUXC_GPIO_9_ALT5_GPIO1_IO09 = 5,
+ IMX_IOMUXC_GPIO_9_ALT6_SD1_WP = 6,
+} IMX_IOMUXC_GPIO_9_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_CLK_ALT0_SD2_CLK = 0,
+ IMX_IOMUXC_SD2_CLK_ALT1_ECSPI5_SCLK = 1,
+ IMX_IOMUXC_SD2_CLK_ALT2_KEY_COL5 = 2,
+ IMX_IOMUXC_SD2_CLK_ALT3_AUD4_RXFS = 3,
+ IMX_IOMUXC_SD2_CLK_ALT5_GPIO1_IO10 = 5,
+} IMX_IOMUXC_SD2_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_CMD_ALT0_SD2_CMD = 0,
+ IMX_IOMUXC_SD2_CMD_ALT1_ECSPI5_MOSI = 1,
+ IMX_IOMUXC_SD2_CMD_ALT2_KEY_ROW5 = 2,
+ IMX_IOMUXC_SD2_CMD_ALT3_AUD4_RXC = 3,
+ IMX_IOMUXC_SD2_CMD_ALT5_GPIO1_IO11 = 5,
+} IMX_IOMUXC_SD2_CMD_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_DAT3_ALT0_SD2_DATA3 = 0,
+ IMX_IOMUXC_SD2_DAT3_ALT1_ECSPI5_SS3 = 1,
+ IMX_IOMUXC_SD2_DAT3_ALT2_KEY_COL6 = 2,
+ IMX_IOMUXC_SD2_DAT3_ALT3_AUD4_TXC = 3,
+ IMX_IOMUXC_SD2_DAT3_ALT5_GPIO1_IO12 = 5,
+} IMX_IOMUXC_SD2_DAT3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_DAT2_ALT0_SD2_DATA2 = 0,
+ IMX_IOMUXC_SD2_DAT2_ALT1_ECSPI5_SS1 = 1,
+ IMX_IOMUXC_SD2_DAT2_ALT2_EIM_CS3_B = 2,
+ IMX_IOMUXC_SD2_DAT2_ALT3_AUD4_TXD = 3,
+ IMX_IOMUXC_SD2_DAT2_ALT4_KEY_ROW6 = 4,
+ IMX_IOMUXC_SD2_DAT2_ALT5_GPIO1_IO13 = 5,
+} IMX_IOMUXC_SD2_DAT2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_DAT1_ALT0_SD2_DATA1 = 0,
+ IMX_IOMUXC_SD2_DAT1_ALT1_ECSPI5_SS0 = 1,
+ IMX_IOMUXC_SD2_DAT1_ALT2_EIM_CS2_B = 2,
+ IMX_IOMUXC_SD2_DAT1_ALT3_AUD4_TXFS = 3,
+ IMX_IOMUXC_SD2_DAT1_ALT4_KEY_COL7 = 4,
+ IMX_IOMUXC_SD2_DAT1_ALT5_GPIO1_IO14 = 5,
+} IMX_IOMUXC_SD2_DAT1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_DAT0_ALT0_SD2_DATA0 = 0,
+ IMX_IOMUXC_SD2_DAT0_ALT1_ECSPI5_MISO = 1,
+ IMX_IOMUXC_SD2_DAT0_ALT3_AUD4_RXD = 3,
+ IMX_IOMUXC_SD2_DAT0_ALT4_KEY_ROW7 = 4,
+ IMX_IOMUXC_SD2_DAT0_ALT5_GPIO1_IO15 = 5,
+ IMX_IOMUXC_SD2_DAT0_ALT6_DCIC2_OUT = 6,
+} IMX_IOMUXC_SD2_DAT0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_DAT0_ALT0_SD1_DATA0 = 0,
+ IMX_IOMUXC_SD1_DAT0_ALT1_ECSPI5_MISO = 1,
+ IMX_IOMUXC_SD1_DAT0_ALT3_GPT_CAPTURE1 = 3,
+ IMX_IOMUXC_SD1_DAT0_ALT5_GPIO1_IO16 = 5,
+} IMX_IOMUXC_SD1_DAT0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_DAT1_ALT0_SD1_DATA1 = 0,
+ IMX_IOMUXC_SD1_DAT1_ALT1_ECSPI5_SS0 = 1,
+ IMX_IOMUXC_SD1_DAT1_ALT2_PWM3_OUT = 2,
+ IMX_IOMUXC_SD1_DAT1_ALT3_GPT_CAPTURE2 = 3,
+ IMX_IOMUXC_SD1_DAT1_ALT5_GPIO1_IO17 = 5,
+} IMX_IOMUXC_SD1_DAT1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_CMD_ALT0_SD1_CMD = 0,
+ IMX_IOMUXC_SD1_CMD_ALT1_ECSPI5_MOSI = 1,
+ IMX_IOMUXC_SD1_CMD_ALT2_PWM4_OUT = 2,
+ IMX_IOMUXC_SD1_CMD_ALT3_GPT_COMPARE1 = 3,
+ IMX_IOMUXC_SD1_CMD_ALT5_GPIO1_IO18 = 5,
+} IMX_IOMUXC_SD1_CMD_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_DAT2_ALT0_SD1_DATA2 = 0,
+ IMX_IOMUXC_SD1_DAT2_ALT1_ECSPI5_SS1 = 1,
+ IMX_IOMUXC_SD1_DAT2_ALT2_GPT_COMPARE2 = 2,
+ IMX_IOMUXC_SD1_DAT2_ALT3_PWM2_OUT = 3,
+ IMX_IOMUXC_SD1_DAT2_ALT4_WDOG1_B = 4,
+ IMX_IOMUXC_SD1_DAT2_ALT5_GPIO1_IO19 = 5,
+ IMX_IOMUXC_SD1_DAT2_ALT6_WDOG1_RESET_B_DEB = 6,
+} IMX_IOMUXC_SD1_DAT2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_CLK_ALT0_SD1_CLK = 0,
+ IMX_IOMUXC_SD1_CLK_ALT1_ECSPI5_SCLK = 1,
+ IMX_IOMUXC_SD1_CLK_ALT2_XTALOSC_OSC32K_32K_OUT = 2,
+ IMX_IOMUXC_SD1_CLK_ALT3_GPT_CLKIN = 3,
+ IMX_IOMUXC_SD1_CLK_ALT5_GPIO1_IO20 = 5,
+} IMX_IOMUXC_SD1_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_DAT3_ALT0_SD1_DATA3 = 0,
+ IMX_IOMUXC_SD1_DAT3_ALT1_ECSPI5_SS2 = 1,
+ IMX_IOMUXC_SD1_DAT3_ALT2_GPT_COMPARE3 = 2,
+ IMX_IOMUXC_SD1_DAT3_ALT3_PWM1_OUT = 3,
+ IMX_IOMUXC_SD1_DAT3_ALT4_WDOG2_B = 4,
+ IMX_IOMUXC_SD1_DAT3_ALT5_GPIO1_IO21 = 5,
+ IMX_IOMUXC_SD1_DAT3_ALT6_WDOG2_RESET_B_DEB = 6,
+} IMX_IOMUXC_SD1_DAT3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_MDIO_ALT1_ENET_MDIO = 1,
+ IMX_IOMUXC_ENET_MDIO_ALT2_ESAI_RX_CLK = 2,
+ IMX_IOMUXC_ENET_MDIO_ALT4_ENET_1588_EVENT1_OUT = 4,
+ IMX_IOMUXC_ENET_MDIO_ALT5_GPIO1_IO22 = 5,
+ IMX_IOMUXC_ENET_MDIO_ALT6_SPDIF_LOCK = 6,
+} IMX_IOMUXC_ENET_MDIO_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_REF_CLK_ALT1_ENET_TX_CLK = 1,
+ IMX_IOMUXC_ENET_REF_CLK_ALT2_ESAI_RX_FS = 2,
+ IMX_IOMUXC_ENET_REF_CLK_ALT5_GPIO1_IO23 = 5,
+ IMX_IOMUXC_ENET_REF_CLK_ALT6_SPDIF_SR_CLK = 6,
+} IMX_IOMUXC_ENET_REF_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_RX_ER_ALT0_USB_OTG_ID = 0,
+ IMX_IOMUXC_ENET_RX_ER_ALT1_ENET_RX_ER = 1,
+ IMX_IOMUXC_ENET_RX_ER_ALT2_ESAI_RX_HF_CLK = 2,
+ IMX_IOMUXC_ENET_RX_ER_ALT3_SPDIF_IN = 3,
+ IMX_IOMUXC_ENET_RX_ER_ALT4_ENET_1588_EVENT2_OUT = 4,
+ IMX_IOMUXC_ENET_RX_ER_ALT5_GPIO1_IO24 = 5,
+} IMX_IOMUXC_ENET_RX_ER_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_CRS_DV_ALT1_ENET_RX_EN = 1,
+ IMX_IOMUXC_ENET_CRS_DV_ALT2_ESAI_TX_CLK = 2,
+ IMX_IOMUXC_ENET_CRS_DV_ALT3_SPDIF_EXT_CLK = 3,
+ IMX_IOMUXC_ENET_CRS_DV_ALT5_GPIO1_IO25 = 5,
+} IMX_IOMUXC_ENET_CRS_DV_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_RXD1_ALT0_MLB_SIG = 0,
+ IMX_IOMUXC_ENET_RXD1_ALT1_ENET_RX_DATA1 = 1,
+ IMX_IOMUXC_ENET_RXD1_ALT2_ESAI_TX_FS = 2,
+ IMX_IOMUXC_ENET_RXD1_ALT4_ENET_1588_EVENT3_OUT = 4,
+ IMX_IOMUXC_ENET_RXD1_ALT5_GPIO1_IO26 = 5,
+} IMX_IOMUXC_ENET_RXD1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_RXD0_ALT0_XTALOSC_OSC32K_32K_OUT = 0,
+ IMX_IOMUXC_ENET_RXD0_ALT1_ENET_RX_DATA0 = 1,
+ IMX_IOMUXC_ENET_RXD0_ALT2_ESAI_TX_HF_CLK = 2,
+ IMX_IOMUXC_ENET_RXD0_ALT3_SPDIF_OUT = 3,
+ IMX_IOMUXC_ENET_RXD0_ALT5_GPIO1_IO27 = 5,
+} IMX_IOMUXC_ENET_RXD0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_TX_EN_ALT1_ENET_TX_EN = 1,
+ IMX_IOMUXC_ENET_TX_EN_ALT2_ESAI_TX3_RX2 = 2,
+ IMX_IOMUXC_ENET_TX_EN_ALT5_GPIO1_IO28 = 5,
+} IMX_IOMUXC_ENET_TX_EN_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_TXD1_ALT0_MLB_CLK = 0,
+ IMX_IOMUXC_ENET_TXD1_ALT1_ENET_TX_DATA1 = 1,
+ IMX_IOMUXC_ENET_TXD1_ALT2_ESAI_TX2_RX3 = 2,
+ IMX_IOMUXC_ENET_TXD1_ALT4_ENET_1588_EVENT0_IN = 4,
+ IMX_IOMUXC_ENET_TXD1_ALT5_GPIO1_IO29 = 5,
+} IMX_IOMUXC_ENET_TXD1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_TXD0_ALT1_ENET_TX_DATA0 = 1,
+ IMX_IOMUXC_ENET_TXD0_ALT2_ESAI_TX4_RX1 = 2,
+ IMX_IOMUXC_ENET_TXD0_ALT5_GPIO1_IO30 = 5,
+} IMX_IOMUXC_ENET_TXD0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_MDC_ALT0_MLB_DATA = 0,
+ IMX_IOMUXC_ENET_MDC_ALT1_ENET_MDC = 1,
+ IMX_IOMUXC_ENET_MDC_ALT2_ESAI_TX5_RX0 = 2,
+ IMX_IOMUXC_ENET_MDC_ALT4_ENET_1588_EVENT1_IN = 4,
+ IMX_IOMUXC_ENET_MDC_ALT5_GPIO1_IO31 = 5,
+} IMX_IOMUXC_ENET_MDC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D0_ALT0_NAND_DATA00 = 0,
+ IMX_IOMUXC_NANDF_D0_ALT1_SD1_DATA4 = 1,
+ IMX_IOMUXC_NANDF_D0_ALT5_GPIO2_IO00 = 5,
+} IMX_IOMUXC_NANDF_D0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D1_ALT0_NAND_DATA01 = 0,
+ IMX_IOMUXC_NANDF_D1_ALT1_SD1_DATA5 = 1,
+ IMX_IOMUXC_NANDF_D1_ALT5_GPIO2_IO01 = 5,
+} IMX_IOMUXC_NANDF_D1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D2_ALT0_NAND_DATA02 = 0,
+ IMX_IOMUXC_NANDF_D2_ALT1_SD1_DATA6 = 1,
+ IMX_IOMUXC_NANDF_D2_ALT5_GPIO2_IO02 = 5,
+} IMX_IOMUXC_NANDF_D2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D3_ALT0_NAND_DATA03 = 0,
+ IMX_IOMUXC_NANDF_D3_ALT1_SD1_DATA7 = 1,
+ IMX_IOMUXC_NANDF_D3_ALT5_GPIO2_IO03 = 5,
+} IMX_IOMUXC_NANDF_D3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D4_ALT0_NAND_DATA04 = 0,
+ IMX_IOMUXC_NANDF_D4_ALT1_SD2_DATA4 = 1,
+ IMX_IOMUXC_NANDF_D4_ALT5_GPIO2_IO04 = 5,
+} IMX_IOMUXC_NANDF_D4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D5_ALT0_NAND_DATA05 = 0,
+ IMX_IOMUXC_NANDF_D5_ALT1_SD2_DATA5 = 1,
+ IMX_IOMUXC_NANDF_D5_ALT5_GPIO2_IO05 = 5,
+} IMX_IOMUXC_NANDF_D5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D6_ALT0_NAND_DATA06 = 0,
+ IMX_IOMUXC_NANDF_D6_ALT1_SD2_DATA6 = 1,
+ IMX_IOMUXC_NANDF_D6_ALT5_GPIO2_IO06 = 5,
+} IMX_IOMUXC_NANDF_D6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D7_ALT0_NAND_DATA07 = 0,
+ IMX_IOMUXC_NANDF_D7_ALT1_SD2_DATA7 = 1,
+ IMX_IOMUXC_NANDF_D7_ALT5_GPIO2_IO07 = 5,
+} IMX_IOMUXC_NANDF_D7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT0_ALT1_SD4_DATA0 = 1,
+ IMX_IOMUXC_SD4_DAT0_ALT2_NAND_DQS = 2,
+ IMX_IOMUXC_SD4_DAT0_ALT5_GPIO2_IO08 = 5,
+} IMX_IOMUXC_SD4_DAT0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT1_ALT1_SD4_DATA1 = 1,
+ IMX_IOMUXC_SD4_DAT1_ALT2_PWM3_OUT = 2,
+ IMX_IOMUXC_SD4_DAT1_ALT5_GPIO2_IO09 = 5,
+} IMX_IOMUXC_SD4_DAT1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT2_ALT1_SD4_DATA2 = 1,
+ IMX_IOMUXC_SD4_DAT2_ALT2_PWM4_OUT = 2,
+ IMX_IOMUXC_SD4_DAT2_ALT5_GPIO2_IO10 = 5,
+} IMX_IOMUXC_SD4_DAT2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT3_ALT1_SD4_DATA3 = 1,
+ IMX_IOMUXC_SD4_DAT3_ALT5_GPIO2_IO11 = 5,
+} IMX_IOMUXC_SD4_DAT3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT4_ALT1_SD4_DATA4 = 1,
+ IMX_IOMUXC_SD4_DAT4_ALT2_UART2_RX_DATA = 2,
+ IMX_IOMUXC_SD4_DAT4_ALT5_GPIO2_IO12 = 5,
+} IMX_IOMUXC_SD4_DAT4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT5_ALT1_SD4_DATA5 = 1,
+ IMX_IOMUXC_SD4_DAT5_ALT2_UART2_RTS_B = 2,
+ IMX_IOMUXC_SD4_DAT5_ALT5_GPIO2_IO13 = 5,
+} IMX_IOMUXC_SD4_DAT5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT6_ALT1_SD4_DATA6 = 1,
+ IMX_IOMUXC_SD4_DAT6_ALT2_UART2_CTS_B = 2,
+ IMX_IOMUXC_SD4_DAT6_ALT5_GPIO2_IO14 = 5,
+} IMX_IOMUXC_SD4_DAT6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT7_ALT1_SD4_DATA7 = 1,
+ IMX_IOMUXC_SD4_DAT7_ALT2_UART2_TX_DATA = 2,
+ IMX_IOMUXC_SD4_DAT7_ALT5_GPIO2_IO15 = 5,
+} IMX_IOMUXC_SD4_DAT7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A22_ALT0_EIM_ADDR22 = 0,
+ IMX_IOMUXC_EIM_A22_ALT1_IPU1_DISP1_DATA17 = 1,
+ IMX_IOMUXC_EIM_A22_ALT2_IPU2_CSI1_DATA17 = 2,
+ IMX_IOMUXC_EIM_A22_ALT5_GPIO2_IO16 = 5,
+ IMX_IOMUXC_EIM_A22_ALT7_SRC_BOOT_CFG22 = 7,
+} IMX_IOMUXC_EIM_A22_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A21_ALT0_EIM_ADDR21 = 0,
+ IMX_IOMUXC_EIM_A21_ALT1_IPU1_DISP1_DATA16 = 1,
+ IMX_IOMUXC_EIM_A21_ALT2_IPU2_CSI1_DATA16 = 2,
+ IMX_IOMUXC_EIM_A21_ALT5_GPIO2_IO17 = 5,
+ IMX_IOMUXC_EIM_A21_ALT7_SRC_BOOT_CFG21 = 7,
+} IMX_IOMUXC_EIM_A21_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A20_ALT0_EIM_ADDR20 = 0,
+ IMX_IOMUXC_EIM_A20_ALT1_IPU1_DISP1_DATA15 = 1,
+ IMX_IOMUXC_EIM_A20_ALT2_IPU2_CSI1_DATA15 = 2,
+ IMX_IOMUXC_EIM_A20_ALT5_GPIO2_IO18 = 5,
+ IMX_IOMUXC_EIM_A20_ALT7_SRC_BOOT_CFG20 = 7,
+} IMX_IOMUXC_EIM_A20_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A19_ALT0_EIM_ADDR19 = 0,
+ IMX_IOMUXC_EIM_A19_ALT1_IPU1_DISP1_DATA14 = 1,
+ IMX_IOMUXC_EIM_A19_ALT2_IPU2_CSI1_DATA14 = 2,
+ IMX_IOMUXC_EIM_A19_ALT5_GPIO2_IO19 = 5,
+ IMX_IOMUXC_EIM_A19_ALT7_SRC_BOOT_CFG19 = 7,
+} IMX_IOMUXC_EIM_A19_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A18_ALT0_EIM_ADDR18 = 0,
+ IMX_IOMUXC_EIM_A18_ALT1_IPU1_DISP1_DATA13 = 1,
+ IMX_IOMUXC_EIM_A18_ALT2_IPU2_CSI1_DATA13 = 2,
+ IMX_IOMUXC_EIM_A18_ALT5_GPIO2_IO20 = 5,
+ IMX_IOMUXC_EIM_A18_ALT7_SRC_BOOT_CFG18 = 7,
+} IMX_IOMUXC_EIM_A18_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A17_ALT0_EIM_ADDR17 = 0,
+ IMX_IOMUXC_EIM_A17_ALT1_IPU1_DISP1_DATA12 = 1,
+ IMX_IOMUXC_EIM_A17_ALT2_IPU2_CSI1_DATA12 = 2,
+ IMX_IOMUXC_EIM_A17_ALT5_GPIO2_IO21 = 5,
+ IMX_IOMUXC_EIM_A17_ALT7_SRC_BOOT_CFG17 = 7,
+} IMX_IOMUXC_EIM_A17_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A16_ALT0_EIM_ADDR16 = 0,
+ IMX_IOMUXC_EIM_A16_ALT1_IPU1_DI1_DISP_CLK = 1,
+ IMX_IOMUXC_EIM_A16_ALT2_IPU2_CSI1_PIXCLK = 2,
+ IMX_IOMUXC_EIM_A16_ALT5_GPIO2_IO22 = 5,
+ IMX_IOMUXC_EIM_A16_ALT7_SRC_BOOT_CFG16 = 7,
+} IMX_IOMUXC_EIM_A16_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_CS0_ALT0_EIM_CS0_B = 0,
+ IMX_IOMUXC_EIM_CS0_ALT1_IPU1_DI1_PIN05 = 1,
+ IMX_IOMUXC_EIM_CS0_ALT2_ECSPI2_SCLK = 2,
+ IMX_IOMUXC_EIM_CS0_ALT5_GPIO2_IO23 = 5,
+} IMX_IOMUXC_EIM_CS0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_CS1_ALT0_EIM_CS1_B = 0,
+ IMX_IOMUXC_EIM_CS1_ALT1_IPU1_DI1_PIN06 = 1,
+ IMX_IOMUXC_EIM_CS1_ALT2_ECSPI2_MOSI = 2,
+ IMX_IOMUXC_EIM_CS1_ALT5_GPIO2_IO24 = 5,
+} IMX_IOMUXC_EIM_CS1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_OE_ALT0_EIM_OE_B = 0,
+ IMX_IOMUXC_EIM_OE_ALT1_IPU1_DI1_PIN07 = 1,
+ IMX_IOMUXC_EIM_OE_ALT2_ECSPI2_MISO = 2,
+ IMX_IOMUXC_EIM_OE_ALT5_GPIO2_IO25 = 5,
+} IMX_IOMUXC_EIM_OE_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_RW_ALT0_EIM_RW = 0,
+ IMX_IOMUXC_EIM_RW_ALT1_IPU1_DI1_PIN08 = 1,
+ IMX_IOMUXC_EIM_RW_ALT2_ECSPI2_SS0 = 2,
+ IMX_IOMUXC_EIM_RW_ALT5_GPIO2_IO26 = 5,
+ IMX_IOMUXC_EIM_RW_ALT7_SRC_BOOT_CFG29 = 7,
+} IMX_IOMUXC_EIM_RW_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_LBA_ALT0_EIM_LBA_B = 0,
+ IMX_IOMUXC_EIM_LBA_ALT1_IPU1_DI1_PIN17 = 1,
+ IMX_IOMUXC_EIM_LBA_ALT2_ECSPI2_SS1 = 2,
+ IMX_IOMUXC_EIM_LBA_ALT5_GPIO2_IO27 = 5,
+ IMX_IOMUXC_EIM_LBA_ALT7_SRC_BOOT_CFG26 = 7,
+} IMX_IOMUXC_EIM_LBA_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_EB0_ALT0_EIM_EB0_B = 0,
+ IMX_IOMUXC_EIM_EB0_ALT1_IPU1_DISP1_DATA11 = 1,
+ IMX_IOMUXC_EIM_EB0_ALT2_IPU2_CSI1_DATA11 = 2,
+ IMX_IOMUXC_EIM_EB0_ALT4_CCM_PMIC_READY = 4,
+ IMX_IOMUXC_EIM_EB0_ALT5_GPIO2_IO28 = 5,
+ IMX_IOMUXC_EIM_EB0_ALT7_SRC_BOOT_CFG27 = 7,
+} IMX_IOMUXC_EIM_EB0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_EB1_ALT0_EIM_EB1_B = 0,
+ IMX_IOMUXC_EIM_EB1_ALT1_IPU1_DISP1_DATA10 = 1,
+ IMX_IOMUXC_EIM_EB1_ALT2_IPU2_CSI1_DATA10 = 2,
+ IMX_IOMUXC_EIM_EB1_ALT5_GPIO2_IO29 = 5,
+ IMX_IOMUXC_EIM_EB1_ALT7_SRC_BOOT_CFG28 = 7,
+} IMX_IOMUXC_EIM_EB1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_EB2_ALT0_EIM_EB2_B = 0,
+ IMX_IOMUXC_EIM_EB2_ALT1_ECSPI1_SS0 = 1,
+ IMX_IOMUXC_EIM_EB2_ALT3_IPU2_CSI1_DATA19 = 3,
+ IMX_IOMUXC_EIM_EB2_ALT4_HDMI_TX_DDC_SCL = 4,
+ IMX_IOMUXC_EIM_EB2_ALT5_GPIO2_IO30 = 5,
+ IMX_IOMUXC_EIM_EB2_ALT6_I2C2_SCL = 6,
+ IMX_IOMUXC_EIM_EB2_ALT7_SRC_BOOT_CFG30 = 7,
+} IMX_IOMUXC_EIM_EB2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_EB3_ALT0_EIM_EB3_B = 0,
+ IMX_IOMUXC_EIM_EB3_ALT1_ECSPI4_RDY = 1,
+ IMX_IOMUXC_EIM_EB3_ALT2_UART3_RTS_B = 2,
+ IMX_IOMUXC_EIM_EB3_ALT3_UART1_RI_B = 3,
+ IMX_IOMUXC_EIM_EB3_ALT4_IPU2_CSI1_HSYNC = 4,
+ IMX_IOMUXC_EIM_EB3_ALT5_GPIO2_IO31 = 5,
+ IMX_IOMUXC_EIM_EB3_ALT6_IPU1_DI1_PIN03 = 6,
+ IMX_IOMUXC_EIM_EB3_ALT7_SRC_BOOT_CFG31 = 7,
+} IMX_IOMUXC_EIM_EB3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA0_ALT0_EIM_AD00 = 0,
+ IMX_IOMUXC_EIM_DA0_ALT1_IPU1_DISP1_DATA09 = 1,
+ IMX_IOMUXC_EIM_DA0_ALT2_IPU2_CSI1_DATA09 = 2,
+ IMX_IOMUXC_EIM_DA0_ALT5_GPIO3_IO00 = 5,
+ IMX_IOMUXC_EIM_DA0_ALT7_SRC_BOOT_CFG00 = 7,
+} IMX_IOMUXC_EIM_DA0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA1_ALT0_EIM_AD01 = 0,
+ IMX_IOMUXC_EIM_DA1_ALT1_IPU1_DISP1_DATA08 = 1,
+ IMX_IOMUXC_EIM_DA1_ALT2_IPU2_CSI1_DATA08 = 2,
+ IMX_IOMUXC_EIM_DA1_ALT5_GPIO3_IO01 = 5,
+ IMX_IOMUXC_EIM_DA1_ALT7_SRC_BOOT_CFG01 = 7,
+} IMX_IOMUXC_EIM_DA1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA2_ALT0_EIM_AD02 = 0,
+ IMX_IOMUXC_EIM_DA2_ALT1_IPU1_DISP1_DATA07 = 1,
+ IMX_IOMUXC_EIM_DA2_ALT2_IPU2_CSI1_DATA07 = 2,
+ IMX_IOMUXC_EIM_DA2_ALT5_GPIO3_IO02 = 5,
+ IMX_IOMUXC_EIM_DA2_ALT7_SRC_BOOT_CFG02 = 7,
+} IMX_IOMUXC_EIM_DA2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA3_ALT0_EIM_AD03 = 0,
+ IMX_IOMUXC_EIM_DA3_ALT1_IPU1_DISP1_DATA06 = 1,
+ IMX_IOMUXC_EIM_DA3_ALT2_IPU2_CSI1_DATA06 = 2,
+ IMX_IOMUXC_EIM_DA3_ALT5_GPIO3_IO03 = 5,
+ IMX_IOMUXC_EIM_DA3_ALT7_SRC_BOOT_CFG03 = 7,
+} IMX_IOMUXC_EIM_DA3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA4_ALT0_EIM_AD04 = 0,
+ IMX_IOMUXC_EIM_DA4_ALT1_IPU1_DISP1_DATA05 = 1,
+ IMX_IOMUXC_EIM_DA4_ALT2_IPU2_CSI1_DATA05 = 2,
+ IMX_IOMUXC_EIM_DA4_ALT5_GPIO3_IO04 = 5,
+ IMX_IOMUXC_EIM_DA4_ALT7_SRC_BOOT_CFG04 = 7,
+} IMX_IOMUXC_EIM_DA4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA5_ALT0_EIM_AD05 = 0,
+ IMX_IOMUXC_EIM_DA5_ALT1_IPU1_DISP1_DATA04 = 1,
+ IMX_IOMUXC_EIM_DA5_ALT2_IPU2_CSI1_DATA04 = 2,
+ IMX_IOMUXC_EIM_DA5_ALT5_GPIO3_IO05 = 5,
+ IMX_IOMUXC_EIM_DA5_ALT7_SRC_BOOT_CFG05 = 7,
+} IMX_IOMUXC_EIM_DA5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA6_ALT0_EIM_AD06 = 0,
+ IMX_IOMUXC_EIM_DA6_ALT1_IPU1_DISP1_DATA03 = 1,
+ IMX_IOMUXC_EIM_DA6_ALT2_IPU2_CSI1_DATA03 = 2,
+ IMX_IOMUXC_EIM_DA6_ALT5_GPIO3_IO06 = 5,
+ IMX_IOMUXC_EIM_DA6_ALT7_SRC_BOOT_CFG06 = 7,
+} IMX_IOMUXC_EIM_DA6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA7_ALT0_EIM_AD07 = 0,
+ IMX_IOMUXC_EIM_DA7_ALT1_IPU1_DISP1_DATA02 = 1,
+ IMX_IOMUXC_EIM_DA7_ALT2_IPU2_CSI1_DATA02 = 2,
+ IMX_IOMUXC_EIM_DA7_ALT5_GPIO3_IO07 = 5,
+ IMX_IOMUXC_EIM_DA7_ALT7_SRC_BOOT_CFG07 = 7,
+} IMX_IOMUXC_EIM_DA7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA8_ALT0_EIM_AD08 = 0,
+ IMX_IOMUXC_EIM_DA8_ALT1_IPU1_DISP1_DATA01 = 1,
+ IMX_IOMUXC_EIM_DA8_ALT2_IPU2_CSI1_DATA01 = 2,
+ IMX_IOMUXC_EIM_DA8_ALT5_GPIO3_IO08 = 5,
+ IMX_IOMUXC_EIM_DA8_ALT7_SRC_BOOT_CFG08 = 7,
+} IMX_IOMUXC_EIM_DA8_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA9_ALT0_EIM_AD09 = 0,
+ IMX_IOMUXC_EIM_DA9_ALT1_IPU1_DISP1_DATA00 = 1,
+ IMX_IOMUXC_EIM_DA9_ALT2_IPU2_CSI1_DATA00 = 2,
+ IMX_IOMUXC_EIM_DA9_ALT5_GPIO3_IO09 = 5,
+ IMX_IOMUXC_EIM_DA9_ALT7_SRC_BOOT_CFG09 = 7,
+} IMX_IOMUXC_EIM_DA9_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA10_ALT0_EIM_AD10 = 0,
+ IMX_IOMUXC_EIM_DA10_ALT1_IPU1_DI1_PIN15 = 1,
+ IMX_IOMUXC_EIM_DA10_ALT2_IPU2_CSI1_DATA_EN = 2,
+ IMX_IOMUXC_EIM_DA10_ALT5_GPIO3_IO10 = 5,
+ IMX_IOMUXC_EIM_DA10_ALT7_SRC_BOOT_CFG10 = 7,
+} IMX_IOMUXC_EIM_DA10_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA11_ALT0_EIM_AD11 = 0,
+ IMX_IOMUXC_EIM_DA11_ALT1_IPU1_DI1_PIN02 = 1,
+ IMX_IOMUXC_EIM_DA11_ALT2_IPU2_CSI1_HSYNC = 2,
+ IMX_IOMUXC_EIM_DA11_ALT5_GPIO3_IO11 = 5,
+ IMX_IOMUXC_EIM_DA11_ALT7_SRC_BOOT_CFG11 = 7,
+} IMX_IOMUXC_EIM_DA11_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA12_ALT0_EIM_AD12 = 0,
+ IMX_IOMUXC_EIM_DA12_ALT1_IPU1_DI1_PIN03 = 1,
+ IMX_IOMUXC_EIM_DA12_ALT2_IPU2_CSI1_VSYNC = 2,
+ IMX_IOMUXC_EIM_DA12_ALT5_GPIO3_IO12 = 5,
+ IMX_IOMUXC_EIM_DA12_ALT7_SRC_BOOT_CFG12 = 7,
+} IMX_IOMUXC_EIM_DA12_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA13_ALT0_EIM_AD13 = 0,
+ IMX_IOMUXC_EIM_DA13_ALT1_IPU1_DI1_D0_CS = 1,
+ IMX_IOMUXC_EIM_DA13_ALT5_GPIO3_IO13 = 5,
+ IMX_IOMUXC_EIM_DA13_ALT7_SRC_BOOT_CFG13 = 7,
+} IMX_IOMUXC_EIM_DA13_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA14_ALT0_EIM_AD14 = 0,
+ IMX_IOMUXC_EIM_DA14_ALT1_IPU1_DI1_D1_CS = 1,
+ IMX_IOMUXC_EIM_DA14_ALT5_GPIO3_IO14 = 5,
+ IMX_IOMUXC_EIM_DA14_ALT7_SRC_BOOT_CFG14 = 7,
+} IMX_IOMUXC_EIM_DA14_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA15_ALT0_EIM_AD15 = 0,
+ IMX_IOMUXC_EIM_DA15_ALT1_IPU1_DI1_PIN01 = 1,
+ IMX_IOMUXC_EIM_DA15_ALT2_IPU1_DI1_PIN04 = 2,
+ IMX_IOMUXC_EIM_DA15_ALT5_GPIO3_IO15 = 5,
+ IMX_IOMUXC_EIM_DA15_ALT7_SRC_BOOT_CFG15 = 7,
+} IMX_IOMUXC_EIM_DA15_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D16_ALT0_EIM_DATA16 = 0,
+ IMX_IOMUXC_EIM_D16_ALT1_ECSPI1_SCLK = 1,
+ IMX_IOMUXC_EIM_D16_ALT2_IPU1_DI0_PIN05 = 2,
+ IMX_IOMUXC_EIM_D16_ALT3_IPU2_CSI1_DATA18 = 3,
+ IMX_IOMUXC_EIM_D16_ALT4_HDMI_TX_DDC_SDA = 4,
+ IMX_IOMUXC_EIM_D16_ALT5_GPIO3_IO16 = 5,
+ IMX_IOMUXC_EIM_D16_ALT6_I2C2_SDA = 6,
+} IMX_IOMUXC_EIM_D16_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D17_ALT0_EIM_DATA17 = 0,
+ IMX_IOMUXC_EIM_D17_ALT1_ECSPI1_MISO = 1,
+ IMX_IOMUXC_EIM_D17_ALT2_IPU1_DI0_PIN06 = 2,
+ IMX_IOMUXC_EIM_D17_ALT3_IPU2_CSI1_PIXCLK = 3,
+ IMX_IOMUXC_EIM_D17_ALT4_DCIC1_OUT = 4,
+ IMX_IOMUXC_EIM_D17_ALT5_GPIO3_IO17 = 5,
+ IMX_IOMUXC_EIM_D17_ALT6_I2C3_SCL = 6,
+} IMX_IOMUXC_EIM_D17_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D18_ALT0_EIM_DATA18 = 0,
+ IMX_IOMUXC_EIM_D18_ALT1_ECSPI1_MOSI = 1,
+ IMX_IOMUXC_EIM_D18_ALT2_IPU1_DI0_PIN07 = 2,
+ IMX_IOMUXC_EIM_D18_ALT3_IPU2_CSI1_DATA17 = 3,
+ IMX_IOMUXC_EIM_D18_ALT4_IPU1_DI1_D0_CS = 4,
+ IMX_IOMUXC_EIM_D18_ALT5_GPIO3_IO18 = 5,
+ IMX_IOMUXC_EIM_D18_ALT6_I2C3_SDA = 6,
+} IMX_IOMUXC_EIM_D18_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D19_ALT0_EIM_DATA19 = 0,
+ IMX_IOMUXC_EIM_D19_ALT1_ECSPI1_SS1 = 1,
+ IMX_IOMUXC_EIM_D19_ALT2_IPU1_DI0_PIN08 = 2,
+ IMX_IOMUXC_EIM_D19_ALT3_IPU2_CSI1_DATA16 = 3,
+ IMX_IOMUXC_EIM_D19_ALT4_UART1_CTS_B = 4,
+ IMX_IOMUXC_EIM_D19_ALT5_GPIO3_IO19 = 5,
+ IMX_IOMUXC_EIM_D19_ALT6_EPIT1_OUT = 6,
+} IMX_IOMUXC_EIM_D19_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D20_ALT0_EIM_DATA20 = 0,
+ IMX_IOMUXC_EIM_D20_ALT1_ECSPI4_SS0 = 1,
+ IMX_IOMUXC_EIM_D20_ALT2_IPU1_DI0_PIN16 = 2,
+ IMX_IOMUXC_EIM_D20_ALT3_IPU2_CSI1_DATA15 = 3,
+ IMX_IOMUXC_EIM_D20_ALT4_UART1_RTS_B = 4,
+ IMX_IOMUXC_EIM_D20_ALT5_GPIO3_IO20 = 5,
+ IMX_IOMUXC_EIM_D20_ALT6_EPIT2_OUT = 6,
+} IMX_IOMUXC_EIM_D20_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D21_ALT0_EIM_DATA21 = 0,
+ IMX_IOMUXC_EIM_D21_ALT1_ECSPI4_SCLK = 1,
+ IMX_IOMUXC_EIM_D21_ALT2_IPU1_DI0_PIN17 = 2,
+ IMX_IOMUXC_EIM_D21_ALT3_IPU2_CSI1_DATA11 = 3,
+ IMX_IOMUXC_EIM_D21_ALT4_USB_OTG_OC = 4,
+ IMX_IOMUXC_EIM_D21_ALT5_GPIO3_IO21 = 5,
+ IMX_IOMUXC_EIM_D21_ALT6_I2C1_SCL = 6,
+ IMX_IOMUXC_EIM_D21_ALT7_SPDIF_IN = 7,
+} IMX_IOMUXC_EIM_D21_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D22_ALT0_EIM_DATA22 = 0,
+ IMX_IOMUXC_EIM_D22_ALT1_ECSPI4_MISO = 1,
+ IMX_IOMUXC_EIM_D22_ALT2_IPU1_DI0_PIN01 = 2,
+ IMX_IOMUXC_EIM_D22_ALT3_IPU2_CSI1_DATA10 = 3,
+ IMX_IOMUXC_EIM_D22_ALT4_USB_OTG_PWR = 4,
+ IMX_IOMUXC_EIM_D22_ALT5_GPIO3_IO22 = 5,
+ IMX_IOMUXC_EIM_D22_ALT6_SPDIF_OUT = 6,
+} IMX_IOMUXC_EIM_D22_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D23_ALT0_EIM_DATA23 = 0,
+ IMX_IOMUXC_EIM_D23_ALT1_IPU1_DI0_D0_CS = 1,
+ IMX_IOMUXC_EIM_D23_ALT2_UART3_CTS_B = 2,
+ IMX_IOMUXC_EIM_D23_ALT3_UART1_DCD_B = 3,
+ IMX_IOMUXC_EIM_D23_ALT4_IPU2_CSI1_DATA_EN = 4,
+ IMX_IOMUXC_EIM_D23_ALT5_GPIO3_IO23 = 5,
+ IMX_IOMUXC_EIM_D23_ALT6_IPU1_DI1_PIN02 = 6,
+ IMX_IOMUXC_EIM_D23_ALT7_IPU1_DI1_PIN14 = 7,
+} IMX_IOMUXC_EIM_D23_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D24_ALT0_EIM_DATA24 = 0,
+ IMX_IOMUXC_EIM_D24_ALT1_ECSPI4_SS2 = 1,
+ IMX_IOMUXC_EIM_D24_ALT2_UART3_TX_DATA = 2,
+ IMX_IOMUXC_EIM_D24_ALT3_ECSPI1_SS2 = 3,
+ IMX_IOMUXC_EIM_D24_ALT4_ECSPI2_SS2 = 4,
+ IMX_IOMUXC_EIM_D24_ALT5_GPIO3_IO24 = 5,
+ IMX_IOMUXC_EIM_D24_ALT6_AUD5_RXFS = 6,
+ IMX_IOMUXC_EIM_D24_ALT7_UART1_DTR_B = 7,
+} IMX_IOMUXC_EIM_D24_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D25_ALT0_EIM_DATA25 = 0,
+ IMX_IOMUXC_EIM_D25_ALT1_ECSPI4_SS3 = 1,
+ IMX_IOMUXC_EIM_D25_ALT2_UART3_RX_DATA = 2,
+ IMX_IOMUXC_EIM_D25_ALT3_ECSPI1_SS3 = 3,
+ IMX_IOMUXC_EIM_D25_ALT4_ECSPI2_SS3 = 4,
+ IMX_IOMUXC_EIM_D25_ALT5_GPIO3_IO25 = 5,
+ IMX_IOMUXC_EIM_D25_ALT6_AUD5_RXC = 6,
+ IMX_IOMUXC_EIM_D25_ALT7_UART1_DSR_B = 7,
+} IMX_IOMUXC_EIM_D25_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D26_ALT0_EIM_DATA26 = 0,
+ IMX_IOMUXC_EIM_D26_ALT1_IPU1_DI1_PIN11 = 1,
+ IMX_IOMUXC_EIM_D26_ALT2_IPU1_CSI0_DATA01 = 2,
+ IMX_IOMUXC_EIM_D26_ALT3_IPU2_CSI1_DATA14 = 3,
+ IMX_IOMUXC_EIM_D26_ALT4_UART2_TX_DATA = 4,
+ IMX_IOMUXC_EIM_D26_ALT5_GPIO3_IO26 = 5,
+ IMX_IOMUXC_EIM_D26_ALT6_IPU1_SISG2 = 6,
+ IMX_IOMUXC_EIM_D26_ALT7_IPU1_DISP1_DATA22 = 7,
+} IMX_IOMUXC_EIM_D26_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D27_ALT0_EIM_DATA27 = 0,
+ IMX_IOMUXC_EIM_D27_ALT1_IPU1_DI1_PIN13 = 1,
+ IMX_IOMUXC_EIM_D27_ALT2_IPU1_CSI0_DATA00 = 2,
+ IMX_IOMUXC_EIM_D27_ALT3_IPU2_CSI1_DATA13 = 3,
+ IMX_IOMUXC_EIM_D27_ALT4_UART2_RX_DATA = 4,
+ IMX_IOMUXC_EIM_D27_ALT5_GPIO3_IO27 = 5,
+ IMX_IOMUXC_EIM_D27_ALT6_IPU1_SISG3 = 6,
+ IMX_IOMUXC_EIM_D27_ALT7_IPU1_DISP1_DATA23 = 7,
+} IMX_IOMUXC_EIM_D27_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D28_ALT0_EIM_DATA28 = 0,
+ IMX_IOMUXC_EIM_D28_ALT1_I2C1_SDA = 1,
+ IMX_IOMUXC_EIM_D28_ALT2_ECSPI4_MOSI = 2,
+ IMX_IOMUXC_EIM_D28_ALT3_IPU2_CSI1_DATA12 = 3,
+ IMX_IOMUXC_EIM_D28_ALT4_UART2_CTS_B = 4,
+ IMX_IOMUXC_EIM_D28_ALT5_GPIO3_IO28 = 5,
+ IMX_IOMUXC_EIM_D28_ALT6_IPU1_EXT_TRIG = 6,
+ IMX_IOMUXC_EIM_D28_ALT7_IPU1_DI0_PIN13 = 7,
+} IMX_IOMUXC_EIM_D28_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D29_ALT0_EIM_DATA29 = 0,
+ IMX_IOMUXC_EIM_D29_ALT1_IPU1_DI1_PIN15 = 1,
+ IMX_IOMUXC_EIM_D29_ALT2_ECSPI4_SS0 = 2,
+ IMX_IOMUXC_EIM_D29_ALT4_UART2_RTS_B = 4,
+ IMX_IOMUXC_EIM_D29_ALT5_GPIO3_IO29 = 5,
+ IMX_IOMUXC_EIM_D29_ALT6_IPU2_CSI1_VSYNC = 6,
+ IMX_IOMUXC_EIM_D29_ALT7_IPU1_DI0_PIN14 = 7,
+} IMX_IOMUXC_EIM_D29_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D30_ALT0_EIM_DATA30 = 0,
+ IMX_IOMUXC_EIM_D30_ALT1_IPU1_DISP1_DATA21 = 1,
+ IMX_IOMUXC_EIM_D30_ALT2_IPU1_DI0_PIN11 = 2,
+ IMX_IOMUXC_EIM_D30_ALT3_IPU1_CSI0_DATA03 = 3,
+ IMX_IOMUXC_EIM_D30_ALT4_UART3_CTS_B = 4,
+ IMX_IOMUXC_EIM_D30_ALT5_GPIO3_IO30 = 5,
+ IMX_IOMUXC_EIM_D30_ALT6_USB_H1_OC = 6,
+} IMX_IOMUXC_EIM_D30_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D31_ALT0_EIM_DATA31 = 0,
+ IMX_IOMUXC_EIM_D31_ALT1_IPU1_DISP1_DATA20 = 1,
+ IMX_IOMUXC_EIM_D31_ALT2_IPU1_DI0_PIN12 = 2,
+ IMX_IOMUXC_EIM_D31_ALT3_IPU1_CSI0_DATA02 = 3,
+ IMX_IOMUXC_EIM_D31_ALT4_UART3_RTS_B = 4,
+ IMX_IOMUXC_EIM_D31_ALT5_GPIO3_IO31 = 5,
+ IMX_IOMUXC_EIM_D31_ALT6_USB_H1_PWR = 6,
+} IMX_IOMUXC_EIM_D31_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_19_ALT0_KEY_COL5 = 0,
+ IMX_IOMUXC_GPIO_19_ALT1_ENET_1588_EVENT0_OUT = 1,
+ IMX_IOMUXC_GPIO_19_ALT2_SPDIF_OUT = 2,
+ IMX_IOMUXC_GPIO_19_ALT3_CCM_CLKO1 = 3,
+ IMX_IOMUXC_GPIO_19_ALT4_ECSPI1_RDY = 4,
+ IMX_IOMUXC_GPIO_19_ALT5_GPIO4_IO05 = 5,
+ IMX_IOMUXC_GPIO_19_ALT6_ENET_TX_ER = 6,
+} IMX_IOMUXC_GPIO_19_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_COL0_ALT0_ECSPI1_SCLK = 0,
+ IMX_IOMUXC_KEY_COL0_ALT1_ENET_RX_DATA3 = 1,
+ IMX_IOMUXC_KEY_COL0_ALT2_AUD5_TXC = 2,
+ IMX_IOMUXC_KEY_COL0_ALT3_KEY_COL0 = 3,
+ IMX_IOMUXC_KEY_COL0_ALT4_UART4_TX_DATA = 4,
+ IMX_IOMUXC_KEY_COL0_ALT5_GPIO4_IO06 = 5,
+ IMX_IOMUXC_KEY_COL0_ALT6_DCIC1_OUT = 6,
+} IMX_IOMUXC_KEY_COL0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_ROW0_ALT0_ECSPI1_MOSI = 0,
+ IMX_IOMUXC_KEY_ROW0_ALT1_ENET_TX_DATA3 = 1,
+ IMX_IOMUXC_KEY_ROW0_ALT2_AUD5_TXD = 2,
+ IMX_IOMUXC_KEY_ROW0_ALT3_KEY_ROW0 = 3,
+ IMX_IOMUXC_KEY_ROW0_ALT4_UART4_RX_DATA = 4,
+ IMX_IOMUXC_KEY_ROW0_ALT5_GPIO4_IO07 = 5,
+ IMX_IOMUXC_KEY_ROW0_ALT6_DCIC2_OUT = 6,
+} IMX_IOMUXC_KEY_ROW0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_COL1_ALT0_ECSPI1_MISO = 0,
+ IMX_IOMUXC_KEY_COL1_ALT1_ENET_MDIO = 1,
+ IMX_IOMUXC_KEY_COL1_ALT2_AUD5_TXFS = 2,
+ IMX_IOMUXC_KEY_COL1_ALT3_KEY_COL1 = 3,
+ IMX_IOMUXC_KEY_COL1_ALT4_UART5_TX_DATA = 4,
+ IMX_IOMUXC_KEY_COL1_ALT5_GPIO4_IO08 = 5,
+ IMX_IOMUXC_KEY_COL1_ALT6_SD1_VSELECT = 6,
+} IMX_IOMUXC_KEY_COL1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_ROW1_ALT0_ECSPI1_SS0 = 0,
+ IMX_IOMUXC_KEY_ROW1_ALT1_ENET_COL = 1,
+ IMX_IOMUXC_KEY_ROW1_ALT2_AUD5_RXD = 2,
+ IMX_IOMUXC_KEY_ROW1_ALT3_KEY_ROW1 = 3,
+ IMX_IOMUXC_KEY_ROW1_ALT4_UART5_RX_DATA = 4,
+ IMX_IOMUXC_KEY_ROW1_ALT5_GPIO4_IO09 = 5,
+ IMX_IOMUXC_KEY_ROW1_ALT6_SD2_VSELECT = 6,
+} IMX_IOMUXC_KEY_ROW1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_COL2_ALT0_ECSPI1_SS1 = 0,
+ IMX_IOMUXC_KEY_COL2_ALT1_ENET_RX_DATA2 = 1,
+ IMX_IOMUXC_KEY_COL2_ALT2_FLEXCAN1_TX = 2,
+ IMX_IOMUXC_KEY_COL2_ALT3_KEY_COL2 = 3,
+ IMX_IOMUXC_KEY_COL2_ALT4_ENET_MDC = 4,
+ IMX_IOMUXC_KEY_COL2_ALT5_GPIO4_IO10 = 5,
+ IMX_IOMUXC_KEY_COL2_ALT6_USB_H1_PWR_CTL_WAKE = 6,
+} IMX_IOMUXC_KEY_COL2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_ROW2_ALT0_ECSPI1_SS2 = 0,
+ IMX_IOMUXC_KEY_ROW2_ALT1_ENET_TX_DATA2 = 1,
+ IMX_IOMUXC_KEY_ROW2_ALT2_FLEXCAN1_RX = 2,
+ IMX_IOMUXC_KEY_ROW2_ALT3_KEY_ROW2 = 3,
+ IMX_IOMUXC_KEY_ROW2_ALT4_SD2_VSELECT = 4,
+ IMX_IOMUXC_KEY_ROW2_ALT5_GPIO4_IO11 = 5,
+ IMX_IOMUXC_KEY_ROW2_ALT6_HDMI_TX_CEC_LINE = 6,
+} IMX_IOMUXC_KEY_ROW2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_COL3_ALT0_ECSPI1_SS3 = 0,
+ IMX_IOMUXC_KEY_COL3_ALT1_ENET_CRS = 1,
+ IMX_IOMUXC_KEY_COL3_ALT2_HDMI_TX_DDC_SCL = 2,
+ IMX_IOMUXC_KEY_COL3_ALT3_KEY_COL3 = 3,
+ IMX_IOMUXC_KEY_COL3_ALT4_I2C2_SCL = 4,
+ IMX_IOMUXC_KEY_COL3_ALT5_GPIO4_IO12 = 5,
+ IMX_IOMUXC_KEY_COL3_ALT6_SPDIF_IN = 6,
+} IMX_IOMUXC_KEY_COL3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_ROW3_ALT0_XTALOSC_OSC32K_32K_OUT = 0,
+ IMX_IOMUXC_KEY_ROW3_ALT1_ASRC_EXT_CLK = 1,
+ IMX_IOMUXC_KEY_ROW3_ALT2_HDMI_TX_DDC_SDA = 2,
+ IMX_IOMUXC_KEY_ROW3_ALT3_KEY_ROW3 = 3,
+ IMX_IOMUXC_KEY_ROW3_ALT4_I2C2_SDA = 4,
+ IMX_IOMUXC_KEY_ROW3_ALT5_GPIO4_IO13 = 5,
+ IMX_IOMUXC_KEY_ROW3_ALT6_SD1_VSELECT = 6,
+} IMX_IOMUXC_KEY_ROW3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_COL4_ALT0_FLEXCAN2_TX = 0,
+ IMX_IOMUXC_KEY_COL4_ALT1_IPU1_SISG4 = 1,
+ IMX_IOMUXC_KEY_COL4_ALT2_USB_OTG_OC = 2,
+ IMX_IOMUXC_KEY_COL4_ALT3_KEY_COL4 = 3,
+ IMX_IOMUXC_KEY_COL4_ALT4_UART5_RTS_B = 4,
+ IMX_IOMUXC_KEY_COL4_ALT5_GPIO4_IO14 = 5,
+} IMX_IOMUXC_KEY_COL4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_ROW4_ALT0_FLEXCAN2_RX = 0,
+ IMX_IOMUXC_KEY_ROW4_ALT1_IPU1_SISG5 = 1,
+ IMX_IOMUXC_KEY_ROW4_ALT2_USB_OTG_PWR = 2,
+ IMX_IOMUXC_KEY_ROW4_ALT3_KEY_ROW4 = 3,
+ IMX_IOMUXC_KEY_ROW4_ALT4_UART5_CTS_B = 4,
+ IMX_IOMUXC_KEY_ROW4_ALT5_GPIO4_IO15 = 5,
+} IMX_IOMUXC_KEY_ROW4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DI0_DISP_CLK_ALT0_IPU1_DI0_DISP_CLK = 0,
+ IMX_IOMUXC_DI0_DISP_CLK_ALT1_IPU2_DI0_DISP_CLK = 1,
+ IMX_IOMUXC_DI0_DISP_CLK_ALT5_GPIO4_IO16 = 5,
+} IMX_IOMUXC_DI0_DISP_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DI0_PIN15_ALT0_IPU1_DI0_PIN15 = 0,
+ IMX_IOMUXC_DI0_PIN15_ALT1_IPU2_DI0_PIN15 = 1,
+ IMX_IOMUXC_DI0_PIN15_ALT2_AUD6_TXC = 2,
+ IMX_IOMUXC_DI0_PIN15_ALT5_GPIO4_IO17 = 5,
+} IMX_IOMUXC_DI0_PIN15_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DI0_PIN2_ALT0_IPU1_DI0_PIN02 = 0,
+ IMX_IOMUXC_DI0_PIN2_ALT1_IPU2_DI0_PIN02 = 1,
+ IMX_IOMUXC_DI0_PIN2_ALT2_AUD6_TXD = 2,
+ IMX_IOMUXC_DI0_PIN2_ALT5_GPIO4_IO18 = 5,
+} IMX_IOMUXC_DI0_PIN2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DI0_PIN3_ALT0_IPU1_DI0_PIN03 = 0,
+ IMX_IOMUXC_DI0_PIN3_ALT1_IPU2_DI0_PIN03 = 1,
+ IMX_IOMUXC_DI0_PIN3_ALT2_AUD6_TXFS = 2,
+ IMX_IOMUXC_DI0_PIN3_ALT5_GPIO4_IO19 = 5,
+} IMX_IOMUXC_DI0_PIN3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DI0_PIN4_ALT0_IPU1_DI0_PIN04 = 0,
+ IMX_IOMUXC_DI0_PIN4_ALT1_IPU2_DI0_PIN04 = 1,
+ IMX_IOMUXC_DI0_PIN4_ALT2_AUD6_RXD = 2,
+ IMX_IOMUXC_DI0_PIN4_ALT3_SD1_WP = 3,
+ IMX_IOMUXC_DI0_PIN4_ALT5_GPIO4_IO20 = 5,
+} IMX_IOMUXC_DI0_PIN4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT0_ALT0_IPU1_DISP0_DATA00 = 0,
+ IMX_IOMUXC_DISP0_DAT0_ALT1_IPU2_DISP0_DATA00 = 1,
+ IMX_IOMUXC_DISP0_DAT0_ALT2_ECSPI3_SCLK = 2,
+ IMX_IOMUXC_DISP0_DAT0_ALT5_GPIO4_IO21 = 5,
+} IMX_IOMUXC_DISP0_DAT0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT1_ALT0_IPU1_DISP0_DATA01 = 0,
+ IMX_IOMUXC_DISP0_DAT1_ALT1_IPU2_DISP0_DATA01 = 1,
+ IMX_IOMUXC_DISP0_DAT1_ALT2_ECSPI3_MOSI = 2,
+ IMX_IOMUXC_DISP0_DAT1_ALT5_GPIO4_IO22 = 5,
+} IMX_IOMUXC_DISP0_DAT1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT2_ALT0_IPU1_DISP0_DATA02 = 0,
+ IMX_IOMUXC_DISP0_DAT2_ALT1_IPU2_DISP0_DATA02 = 1,
+ IMX_IOMUXC_DISP0_DAT2_ALT2_ECSPI3_MISO = 2,
+ IMX_IOMUXC_DISP0_DAT2_ALT5_GPIO4_IO23 = 5,
+} IMX_IOMUXC_DISP0_DAT2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT3_ALT0_IPU1_DISP0_DATA03 = 0,
+ IMX_IOMUXC_DISP0_DAT3_ALT1_IPU2_DISP0_DATA03 = 1,
+ IMX_IOMUXC_DISP0_DAT3_ALT2_ECSPI3_SS0 = 2,
+ IMX_IOMUXC_DISP0_DAT3_ALT5_GPIO4_IO24 = 5,
+} IMX_IOMUXC_DISP0_DAT3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT4_ALT0_IPU1_DISP0_DATA04 = 0,
+ IMX_IOMUXC_DISP0_DAT4_ALT1_IPU2_DISP0_DATA04 = 1,
+ IMX_IOMUXC_DISP0_DAT4_ALT2_ECSPI3_SS1 = 2,
+ IMX_IOMUXC_DISP0_DAT4_ALT5_GPIO4_IO25 = 5,
+} IMX_IOMUXC_DISP0_DAT4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT5_ALT0_IPU1_DISP0_DATA05 = 0,
+ IMX_IOMUXC_DISP0_DAT5_ALT1_IPU2_DISP0_DATA05 = 1,
+ IMX_IOMUXC_DISP0_DAT5_ALT2_ECSPI3_SS2 = 2,
+ IMX_IOMUXC_DISP0_DAT5_ALT3_AUD6_RXFS = 3,
+ IMX_IOMUXC_DISP0_DAT5_ALT5_GPIO4_IO26 = 5,
+} IMX_IOMUXC_DISP0_DAT5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT6_ALT0_IPU1_DISP0_DATA06 = 0,
+ IMX_IOMUXC_DISP0_DAT6_ALT1_IPU2_DISP0_DATA06 = 1,
+ IMX_IOMUXC_DISP0_DAT6_ALT2_ECSPI3_SS3 = 2,
+ IMX_IOMUXC_DISP0_DAT6_ALT3_AUD6_RXC = 3,
+ IMX_IOMUXC_DISP0_DAT6_ALT5_GPIO4_IO27 = 5,
+} IMX_IOMUXC_DISP0_DAT6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT7_ALT0_IPU1_DISP0_DATA07 = 0,
+ IMX_IOMUXC_DISP0_DAT7_ALT1_IPU2_DISP0_DATA07 = 1,
+ IMX_IOMUXC_DISP0_DAT7_ALT2_ECSPI3_RDY = 2,
+ IMX_IOMUXC_DISP0_DAT7_ALT5_GPIO4_IO28 = 5,
+} IMX_IOMUXC_DISP0_DAT7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT8_ALT0_IPU1_DISP0_DATA08 = 0,
+ IMX_IOMUXC_DISP0_DAT8_ALT1_IPU2_DISP0_DATA08 = 1,
+ IMX_IOMUXC_DISP0_DAT8_ALT2_PWM1_OUT = 2,
+ IMX_IOMUXC_DISP0_DAT8_ALT3_WDOG1_B = 3,
+ IMX_IOMUXC_DISP0_DAT8_ALT5_GPIO4_IO29 = 5,
+} IMX_IOMUXC_DISP0_DAT8_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT9_ALT0_IPU1_DISP0_DATA09 = 0,
+ IMX_IOMUXC_DISP0_DAT9_ALT1_IPU2_DISP0_DATA09 = 1,
+ IMX_IOMUXC_DISP0_DAT9_ALT2_PWM2_OUT = 2,
+ IMX_IOMUXC_DISP0_DAT9_ALT3_WDOG2_B = 3,
+ IMX_IOMUXC_DISP0_DAT9_ALT5_GPIO4_IO30 = 5,
+} IMX_IOMUXC_DISP0_DAT9_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT10_ALT0_IPU1_DISP0_DATA10 = 0,
+ IMX_IOMUXC_DISP0_DAT10_ALT1_IPU2_DISP0_DATA10 = 1,
+ IMX_IOMUXC_DISP0_DAT10_ALT5_GPIO4_IO31 = 5,
+} IMX_IOMUXC_DISP0_DAT10_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_WAIT_ALT0_EIM_WAIT_B = 0,
+ IMX_IOMUXC_EIM_WAIT_ALT1_EIM_DTACK_B = 1,
+ IMX_IOMUXC_EIM_WAIT_ALT5_GPIO5_IO00 = 5,
+ IMX_IOMUXC_EIM_WAIT_ALT7_SRC_BOOT_CFG25 = 7,
+} IMX_IOMUXC_EIM_WAIT_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A25_ALT0_EIM_ADDR25 = 0,
+ IMX_IOMUXC_EIM_A25_ALT1_ECSPI4_SS1 = 1,
+ IMX_IOMUXC_EIM_A25_ALT2_ECSPI2_RDY = 2,
+ IMX_IOMUXC_EIM_A25_ALT3_IPU1_DI1_PIN12 = 3,
+ IMX_IOMUXC_EIM_A25_ALT4_IPU1_DI0_D1_CS = 4,
+ IMX_IOMUXC_EIM_A25_ALT5_GPIO5_IO02 = 5,
+ IMX_IOMUXC_EIM_A25_ALT6_HDMI_TX_CEC_LINE = 6,
+} IMX_IOMUXC_EIM_A25_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A24_ALT0_EIM_ADDR24 = 0,
+ IMX_IOMUXC_EIM_A24_ALT1_IPU1_DISP1_DATA19 = 1,
+ IMX_IOMUXC_EIM_A24_ALT2_IPU2_CSI1_DATA19 = 2,
+ IMX_IOMUXC_EIM_A24_ALT3_IPU2_SISG2 = 3,
+ IMX_IOMUXC_EIM_A24_ALT4_IPU1_SISG2 = 4,
+ IMX_IOMUXC_EIM_A24_ALT5_GPIO5_IO04 = 5,
+ IMX_IOMUXC_EIM_A24_ALT7_SRC_BOOT_CFG24 = 7,
+} IMX_IOMUXC_EIM_A24_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT11_ALT0_IPU1_DISP0_DATA11 = 0,
+ IMX_IOMUXC_DISP0_DAT11_ALT1_IPU2_DISP0_DATA11 = 1,
+ IMX_IOMUXC_DISP0_DAT11_ALT5_GPIO5_IO05 = 5,
+} IMX_IOMUXC_DISP0_DAT11_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT12_ALT0_IPU1_DISP0_DATA12 = 0,
+ IMX_IOMUXC_DISP0_DAT12_ALT1_IPU2_DISP0_DATA12 = 1,
+ IMX_IOMUXC_DISP0_DAT12_ALT5_GPIO5_IO06 = 5,
+} IMX_IOMUXC_DISP0_DAT12_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT13_ALT0_IPU1_DISP0_DATA13 = 0,
+ IMX_IOMUXC_DISP0_DAT13_ALT1_IPU2_DISP0_DATA13 = 1,
+ IMX_IOMUXC_DISP0_DAT13_ALT3_AUD5_RXFS = 3,
+ IMX_IOMUXC_DISP0_DAT13_ALT5_GPIO5_IO07 = 5,
+} IMX_IOMUXC_DISP0_DAT13_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT14_ALT0_IPU1_DISP0_DATA14 = 0,
+ IMX_IOMUXC_DISP0_DAT14_ALT1_IPU2_DISP0_DATA14 = 1,
+ IMX_IOMUXC_DISP0_DAT14_ALT3_AUD5_RXC = 3,
+ IMX_IOMUXC_DISP0_DAT14_ALT5_GPIO5_IO08 = 5,
+} IMX_IOMUXC_DISP0_DAT14_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT15_ALT0_IPU1_DISP0_DATA15 = 0,
+ IMX_IOMUXC_DISP0_DAT15_ALT1_IPU2_DISP0_DATA15 = 1,
+ IMX_IOMUXC_DISP0_DAT15_ALT2_ECSPI1_SS1 = 2,
+ IMX_IOMUXC_DISP0_DAT15_ALT3_ECSPI2_SS1 = 3,
+ IMX_IOMUXC_DISP0_DAT15_ALT5_GPIO5_IO09 = 5,
+} IMX_IOMUXC_DISP0_DAT15_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT16_ALT0_IPU1_DISP0_DATA16 = 0,
+ IMX_IOMUXC_DISP0_DAT16_ALT1_IPU2_DISP0_DATA16 = 1,
+ IMX_IOMUXC_DISP0_DAT16_ALT2_ECSPI2_MOSI = 2,
+ IMX_IOMUXC_DISP0_DAT16_ALT3_AUD5_TXC = 3,
+ IMX_IOMUXC_DISP0_DAT16_ALT4_SDMA_EXT_EVENT0 = 4,
+ IMX_IOMUXC_DISP0_DAT16_ALT5_GPIO5_IO10 = 5,
+} IMX_IOMUXC_DISP0_DAT16_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT17_ALT0_IPU1_DISP0_DATA17 = 0,
+ IMX_IOMUXC_DISP0_DAT17_ALT1_IPU2_DISP0_DATA17 = 1,
+ IMX_IOMUXC_DISP0_DAT17_ALT2_ECSPI2_MISO = 2,
+ IMX_IOMUXC_DISP0_DAT17_ALT3_AUD5_TXD = 3,
+ IMX_IOMUXC_DISP0_DAT17_ALT4_SDMA_EXT_EVENT1 = 4,
+ IMX_IOMUXC_DISP0_DAT17_ALT5_GPIO5_IO11 = 5,
+} IMX_IOMUXC_DISP0_DAT17_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT18_ALT0_IPU1_DISP0_DATA18 = 0,
+ IMX_IOMUXC_DISP0_DAT18_ALT1_IPU2_DISP0_DATA18 = 1,
+ IMX_IOMUXC_DISP0_DAT18_ALT2_ECSPI2_SS0 = 2,
+ IMX_IOMUXC_DISP0_DAT18_ALT3_AUD5_TXFS = 3,
+ IMX_IOMUXC_DISP0_DAT18_ALT4_AUD4_RXFS = 4,
+ IMX_IOMUXC_DISP0_DAT18_ALT5_GPIO5_IO12 = 5,
+ IMX_IOMUXC_DISP0_DAT18_ALT7_EIM_CS2_B = 7,
+} IMX_IOMUXC_DISP0_DAT18_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT19_ALT0_IPU1_DISP0_DATA19 = 0,
+ IMX_IOMUXC_DISP0_DAT19_ALT1_IPU2_DISP0_DATA19 = 1,
+ IMX_IOMUXC_DISP0_DAT19_ALT2_ECSPI2_SCLK = 2,
+ IMX_IOMUXC_DISP0_DAT19_ALT3_AUD5_RXD = 3,
+ IMX_IOMUXC_DISP0_DAT19_ALT4_AUD4_RXC = 4,
+ IMX_IOMUXC_DISP0_DAT19_ALT5_GPIO5_IO13 = 5,
+ IMX_IOMUXC_DISP0_DAT19_ALT7_EIM_CS3_B = 7,
+} IMX_IOMUXC_DISP0_DAT19_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT20_ALT0_IPU1_DISP0_DATA20 = 0,
+ IMX_IOMUXC_DISP0_DAT20_ALT1_IPU2_DISP0_DATA20 = 1,
+ IMX_IOMUXC_DISP0_DAT20_ALT2_ECSPI1_SCLK = 2,
+ IMX_IOMUXC_DISP0_DAT20_ALT3_AUD4_TXC = 3,
+ IMX_IOMUXC_DISP0_DAT20_ALT5_GPIO5_IO14 = 5,
+} IMX_IOMUXC_DISP0_DAT20_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT21_ALT0_IPU1_DISP0_DATA21 = 0,
+ IMX_IOMUXC_DISP0_DAT21_ALT1_IPU2_DISP0_DATA21 = 1,
+ IMX_IOMUXC_DISP0_DAT21_ALT2_ECSPI1_MOSI = 2,
+ IMX_IOMUXC_DISP0_DAT21_ALT3_AUD4_TXD = 3,
+ IMX_IOMUXC_DISP0_DAT21_ALT5_GPIO5_IO15 = 5,
+} IMX_IOMUXC_DISP0_DAT21_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT22_ALT0_IPU1_DISP0_DATA22 = 0,
+ IMX_IOMUXC_DISP0_DAT22_ALT1_IPU2_DISP0_DATA22 = 1,
+ IMX_IOMUXC_DISP0_DAT22_ALT2_ECSPI1_MISO = 2,
+ IMX_IOMUXC_DISP0_DAT22_ALT3_AUD4_TXFS = 3,
+ IMX_IOMUXC_DISP0_DAT22_ALT5_GPIO5_IO16 = 5,
+} IMX_IOMUXC_DISP0_DAT22_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT23_ALT0_IPU1_DISP0_DATA23 = 0,
+ IMX_IOMUXC_DISP0_DAT23_ALT1_IPU2_DISP0_DATA23 = 1,
+ IMX_IOMUXC_DISP0_DAT23_ALT2_ECSPI1_SS0 = 2,
+ IMX_IOMUXC_DISP0_DAT23_ALT3_AUD4_RXD = 3,
+ IMX_IOMUXC_DISP0_DAT23_ALT5_GPIO5_IO17 = 5,
+} IMX_IOMUXC_DISP0_DAT23_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_PIXCLK_ALT0_IPU1_CSI0_PIXCLK = 0,
+ IMX_IOMUXC_CSI0_PIXCLK_ALT5_GPIO5_IO18 = 5,
+ IMX_IOMUXC_CSI0_PIXCLK_ALT7_ARM_EVENTO = 7,
+} IMX_IOMUXC_CSI0_PIXCLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_MCLK_ALT0_IPU1_CSI0_HSYNC = 0,
+ IMX_IOMUXC_CSI0_MCLK_ALT3_CCM_CLKO1 = 3,
+ IMX_IOMUXC_CSI0_MCLK_ALT5_GPIO5_IO19 = 5,
+ IMX_IOMUXC_CSI0_MCLK_ALT7_ARM_TRACE_CTL = 7,
+} IMX_IOMUXC_CSI0_MCLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DATA_EN_ALT0_IPU1_CSI0_DATA_EN = 0,
+ IMX_IOMUXC_CSI0_DATA_EN_ALT1_EIM_DATA00 = 1,
+ IMX_IOMUXC_CSI0_DATA_EN_ALT5_GPIO5_IO20 = 5,
+ IMX_IOMUXC_CSI0_DATA_EN_ALT7_ARM_TRACE_CLK = 7,
+} IMX_IOMUXC_CSI0_DATA_EN_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_VSYNC_ALT0_IPU1_CSI0_VSYNC = 0,
+ IMX_IOMUXC_CSI0_VSYNC_ALT1_EIM_DATA01 = 1,
+ IMX_IOMUXC_CSI0_VSYNC_ALT5_GPIO5_IO21 = 5,
+ IMX_IOMUXC_CSI0_VSYNC_ALT7_ARM_TRACE00 = 7,
+} IMX_IOMUXC_CSI0_VSYNC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT4_ALT0_IPU1_CSI0_DATA04 = 0,
+ IMX_IOMUXC_CSI0_DAT4_ALT1_EIM_DATA02 = 1,
+ IMX_IOMUXC_CSI0_DAT4_ALT2_ECSPI1_SCLK = 2,
+ IMX_IOMUXC_CSI0_DAT4_ALT3_KEY_COL5 = 3,
+ IMX_IOMUXC_CSI0_DAT4_ALT4_AUD3_TXC = 4,
+ IMX_IOMUXC_CSI0_DAT4_ALT5_GPIO5_IO22 = 5,
+ IMX_IOMUXC_CSI0_DAT4_ALT7_ARM_TRACE01 = 7,
+} IMX_IOMUXC_CSI0_DAT4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT5_ALT0_IPU1_CSI0_DATA05 = 0,
+ IMX_IOMUXC_CSI0_DAT5_ALT1_EIM_DATA03 = 1,
+ IMX_IOMUXC_CSI0_DAT5_ALT2_ECSPI1_MOSI = 2,
+ IMX_IOMUXC_CSI0_DAT5_ALT3_KEY_ROW5 = 3,
+ IMX_IOMUXC_CSI0_DAT5_ALT4_AUD3_TXD = 4,
+ IMX_IOMUXC_CSI0_DAT5_ALT5_GPIO5_IO23 = 5,
+ IMX_IOMUXC_CSI0_DAT5_ALT7_ARM_TRACE02 = 7,
+} IMX_IOMUXC_CSI0_DAT5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT6_ALT0_IPU1_CSI0_DATA06 = 0,
+ IMX_IOMUXC_CSI0_DAT6_ALT1_EIM_DATA04 = 1,
+ IMX_IOMUXC_CSI0_DAT6_ALT2_ECSPI1_MISO = 2,
+ IMX_IOMUXC_CSI0_DAT6_ALT3_KEY_COL6 = 3,
+ IMX_IOMUXC_CSI0_DAT6_ALT4_AUD3_TXFS = 4,
+ IMX_IOMUXC_CSI0_DAT6_ALT5_GPIO5_IO24 = 5,
+ IMX_IOMUXC_CSI0_DAT6_ALT7_ARM_TRACE03 = 7,
+} IMX_IOMUXC_CSI0_DAT6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT7_ALT0_IPU1_CSI0_DATA07 = 0,
+ IMX_IOMUXC_CSI0_DAT7_ALT1_EIM_DATA05 = 1,
+ IMX_IOMUXC_CSI0_DAT7_ALT2_ECSPI1_SS0 = 2,
+ IMX_IOMUXC_CSI0_DAT7_ALT3_KEY_ROW6 = 3,
+ IMX_IOMUXC_CSI0_DAT7_ALT4_AUD3_RXD = 4,
+ IMX_IOMUXC_CSI0_DAT7_ALT5_GPIO5_IO25 = 5,
+ IMX_IOMUXC_CSI0_DAT7_ALT7_ARM_TRACE04 = 7,
+} IMX_IOMUXC_CSI0_DAT7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT8_ALT0_IPU1_CSI0_DATA08 = 0,
+ IMX_IOMUXC_CSI0_DAT8_ALT1_EIM_DATA06 = 1,
+ IMX_IOMUXC_CSI0_DAT8_ALT2_ECSPI2_SCLK = 2,
+ IMX_IOMUXC_CSI0_DAT8_ALT3_KEY_COL7 = 3,
+ IMX_IOMUXC_CSI0_DAT8_ALT4_I2C1_SDA = 4,
+ IMX_IOMUXC_CSI0_DAT8_ALT5_GPIO5_IO26 = 5,
+ IMX_IOMUXC_CSI0_DAT8_ALT7_ARM_TRACE05 = 7,
+} IMX_IOMUXC_CSI0_DAT8_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT9_ALT0_IPU1_CSI0_DATA09 = 0,
+ IMX_IOMUXC_CSI0_DAT9_ALT1_EIM_DATA07 = 1,
+ IMX_IOMUXC_CSI0_DAT9_ALT2_ECSPI2_MOSI = 2,
+ IMX_IOMUXC_CSI0_DAT9_ALT3_KEY_ROW7 = 3,
+ IMX_IOMUXC_CSI0_DAT9_ALT4_I2C1_SCL = 4,
+ IMX_IOMUXC_CSI0_DAT9_ALT5_GPIO5_IO27 = 5,
+ IMX_IOMUXC_CSI0_DAT9_ALT7_ARM_TRACE06 = 7,
+} IMX_IOMUXC_CSI0_DAT9_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT10_ALT0_IPU1_CSI0_DATA10 = 0,
+ IMX_IOMUXC_CSI0_DAT10_ALT1_AUD3_RXC = 1,
+ IMX_IOMUXC_CSI0_DAT10_ALT2_ECSPI2_MISO = 2,
+ IMX_IOMUXC_CSI0_DAT10_ALT3_UART1_TX_DATA = 3,
+ IMX_IOMUXC_CSI0_DAT10_ALT5_GPIO5_IO28 = 5,
+ IMX_IOMUXC_CSI0_DAT10_ALT7_ARM_TRACE07 = 7,
+} IMX_IOMUXC_CSI0_DAT10_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT11_ALT0_IPU1_CSI0_DATA11 = 0,
+ IMX_IOMUXC_CSI0_DAT11_ALT1_AUD3_RXFS = 1,
+ IMX_IOMUXC_CSI0_DAT11_ALT2_ECSPI2_SS0 = 2,
+ IMX_IOMUXC_CSI0_DAT11_ALT3_UART1_RX_DATA = 3,
+ IMX_IOMUXC_CSI0_DAT11_ALT5_GPIO5_IO29 = 5,
+ IMX_IOMUXC_CSI0_DAT11_ALT7_ARM_TRACE08 = 7,
+} IMX_IOMUXC_CSI0_DAT11_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT12_ALT0_IPU1_CSI0_DATA12 = 0,
+ IMX_IOMUXC_CSI0_DAT12_ALT1_EIM_DATA08 = 1,
+ IMX_IOMUXC_CSI0_DAT12_ALT3_UART4_TX_DATA = 3,
+ IMX_IOMUXC_CSI0_DAT12_ALT5_GPIO5_IO30 = 5,
+ IMX_IOMUXC_CSI0_DAT12_ALT7_ARM_TRACE09 = 7,
+} IMX_IOMUXC_CSI0_DAT12_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT13_ALT0_IPU1_CSI0_DATA13 = 0,
+ IMX_IOMUXC_CSI0_DAT13_ALT1_EIM_DATA09 = 1,
+ IMX_IOMUXC_CSI0_DAT13_ALT3_UART4_RX_DATA = 3,
+ IMX_IOMUXC_CSI0_DAT13_ALT5_GPIO5_IO31 = 5,
+ IMX_IOMUXC_CSI0_DAT13_ALT7_ARM_TRACE10 = 7,
+} IMX_IOMUXC_CSI0_DAT13_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT14_ALT0_IPU1_CSI0_DATA14 = 0,
+ IMX_IOMUXC_CSI0_DAT14_ALT1_EIM_DATA10 = 1,
+ IMX_IOMUXC_CSI0_DAT14_ALT3_UART5_TX_DATA = 3,
+ IMX_IOMUXC_CSI0_DAT14_ALT5_GPIO6_IO00 = 5,
+ IMX_IOMUXC_CSI0_DAT14_ALT7_ARM_TRACE11 = 7,
+} IMX_IOMUXC_CSI0_DAT14_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT15_ALT0_IPU1_CSI0_DATA15 = 0,
+ IMX_IOMUXC_CSI0_DAT15_ALT1_EIM_DATA11 = 1,
+ IMX_IOMUXC_CSI0_DAT15_ALT3_UART5_RX_DATA = 3,
+ IMX_IOMUXC_CSI0_DAT15_ALT5_GPIO6_IO01 = 5,
+ IMX_IOMUXC_CSI0_DAT15_ALT7_ARM_TRACE12 = 7,
+} IMX_IOMUXC_CSI0_DAT15_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT16_ALT0_IPU1_CSI0_DATA16 = 0,
+ IMX_IOMUXC_CSI0_DAT16_ALT1_EIM_DATA12 = 1,
+ IMX_IOMUXC_CSI0_DAT16_ALT3_UART4_RTS_B = 3,
+ IMX_IOMUXC_CSI0_DAT16_ALT5_GPIO6_IO02 = 5,
+ IMX_IOMUXC_CSI0_DAT16_ALT7_ARM_TRACE13 = 7,
+} IMX_IOMUXC_CSI0_DAT16_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT17_ALT0_IPU1_CSI0_DATA17 = 0,
+ IMX_IOMUXC_CSI0_DAT17_ALT1_EIM_DATA13 = 1,
+ IMX_IOMUXC_CSI0_DAT17_ALT3_UART4_CTS_B = 3,
+ IMX_IOMUXC_CSI0_DAT17_ALT5_GPIO6_IO03 = 5,
+ IMX_IOMUXC_CSI0_DAT17_ALT7_ARM_TRACE14 = 7,
+} IMX_IOMUXC_CSI0_DAT17_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT18_ALT0_IPU1_CSI0_DATA18 = 0,
+ IMX_IOMUXC_CSI0_DAT18_ALT1_EIM_DATA14 = 1,
+ IMX_IOMUXC_CSI0_DAT18_ALT3_UART5_RTS_B = 3,
+ IMX_IOMUXC_CSI0_DAT18_ALT5_GPIO6_IO04 = 5,
+ IMX_IOMUXC_CSI0_DAT18_ALT7_ARM_TRACE15 = 7,
+} IMX_IOMUXC_CSI0_DAT18_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT19_ALT0_IPU1_CSI0_DATA19 = 0,
+ IMX_IOMUXC_CSI0_DAT19_ALT1_EIM_DATA15 = 1,
+ IMX_IOMUXC_CSI0_DAT19_ALT3_UART5_CTS_B = 3,
+ IMX_IOMUXC_CSI0_DAT19_ALT5_GPIO6_IO05 = 5,
+} IMX_IOMUXC_CSI0_DAT19_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A23_ALT0_EIM_ADDR23 = 0,
+ IMX_IOMUXC_EIM_A23_ALT1_IPU1_DISP1_DATA18 = 1,
+ IMX_IOMUXC_EIM_A23_ALT2_IPU2_CSI1_DATA18 = 2,
+ IMX_IOMUXC_EIM_A23_ALT3_IPU2_SISG3 = 3,
+ IMX_IOMUXC_EIM_A23_ALT4_IPU1_SISG3 = 4,
+ IMX_IOMUXC_EIM_A23_ALT5_GPIO6_IO06 = 5,
+ IMX_IOMUXC_EIM_A23_ALT7_SRC_BOOT_CFG23 = 7,
+} IMX_IOMUXC_EIM_A23_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_CLE_ALT0_NAND_CLE = 0,
+ IMX_IOMUXC_NANDF_CLE_ALT1_IPU2_SISG4 = 1,
+ IMX_IOMUXC_NANDF_CLE_ALT5_GPIO6_IO07 = 5,
+} IMX_IOMUXC_NANDF_CLE_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_ALE_ALT0_NAND_ALE = 0,
+ IMX_IOMUXC_NANDF_ALE_ALT1_SD4_RESET = 1,
+ IMX_IOMUXC_NANDF_ALE_ALT5_GPIO6_IO08 = 5,
+} IMX_IOMUXC_NANDF_ALE_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_WP_B_ALT0_NAND_WP_B = 0,
+ IMX_IOMUXC_NANDF_WP_B_ALT1_IPU2_SISG5 = 1,
+ IMX_IOMUXC_NANDF_WP_B_ALT5_GPIO6_IO09 = 5,
+} IMX_IOMUXC_NANDF_WP_B_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_RB0_ALT0_NAND_READY_B = 0,
+ IMX_IOMUXC_NANDF_RB0_ALT1_IPU2_DI0_PIN01 = 1,
+ IMX_IOMUXC_NANDF_RB0_ALT5_GPIO6_IO10 = 5,
+} IMX_IOMUXC_NANDF_RB0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_CS0_ALT0_NAND_CE0_B = 0,
+ IMX_IOMUXC_NANDF_CS0_ALT5_GPIO6_IO11 = 5,
+} IMX_IOMUXC_NANDF_CS0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_CS1_ALT0_NAND_CE1_B = 0,
+ IMX_IOMUXC_NANDF_CS1_ALT1_SD4_VSELECT = 1,
+ IMX_IOMUXC_NANDF_CS1_ALT2_SD3_VSELECT = 2,
+ IMX_IOMUXC_NANDF_CS1_ALT5_GPIO6_IO14 = 5,
+} IMX_IOMUXC_NANDF_CS1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_CS2_ALT0_NAND_CE2_B = 0,
+ IMX_IOMUXC_NANDF_CS2_ALT1_IPU1_SISG0 = 1,
+ IMX_IOMUXC_NANDF_CS2_ALT2_ESAI_TX0 = 2,
+ IMX_IOMUXC_NANDF_CS2_ALT3_EIM_CRE = 3,
+ IMX_IOMUXC_NANDF_CS2_ALT4_CCM_CLKO2 = 4,
+ IMX_IOMUXC_NANDF_CS2_ALT5_GPIO6_IO15 = 5,
+ IMX_IOMUXC_NANDF_CS2_ALT6_IPU2_SISG0 = 6,
+} IMX_IOMUXC_NANDF_CS2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_CS3_ALT0_NAND_CE3_B = 0,
+ IMX_IOMUXC_NANDF_CS3_ALT1_IPU1_SISG1 = 1,
+ IMX_IOMUXC_NANDF_CS3_ALT2_ESAI_TX1 = 2,
+ IMX_IOMUXC_NANDF_CS3_ALT3_EIM_ADDR26 = 3,
+ IMX_IOMUXC_NANDF_CS3_ALT5_GPIO6_IO16 = 5,
+ IMX_IOMUXC_NANDF_CS3_ALT6_IPU2_SISG1 = 6,
+} IMX_IOMUXC_NANDF_CS3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT7_ALT0_SD3_DATA7 = 0,
+ IMX_IOMUXC_SD3_DAT7_ALT1_UART1_TX_DATA = 1,
+ IMX_IOMUXC_SD3_DAT7_ALT5_GPIO6_IO17 = 5,
+} IMX_IOMUXC_SD3_DAT7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT6_ALT0_SD3_DATA6 = 0,
+ IMX_IOMUXC_SD3_DAT6_ALT1_UART1_RX_DATA = 1,
+ IMX_IOMUXC_SD3_DAT6_ALT5_GPIO6_IO18 = 5,
+} IMX_IOMUXC_SD3_DAT6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_TXC_ALT0_USB_H2_DATA = 0,
+ IMX_IOMUXC_RGMII_TXC_ALT1_RGMII_TXC = 1,
+ IMX_IOMUXC_RGMII_TXC_ALT2_SPDIF_EXT_CLK = 2,
+ IMX_IOMUXC_RGMII_TXC_ALT5_GPIO6_IO19 = 5,
+ IMX_IOMUXC_RGMII_TXC_ALT7_XTALOSC_REF_CLK_24M = 7,
+} IMX_IOMUXC_RGMII_TXC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_TD0_ALT0_HSI_TX_READY = 0,
+ IMX_IOMUXC_RGMII_TD0_ALT1_RGMII_TD0 = 1,
+ IMX_IOMUXC_RGMII_TD0_ALT5_GPIO6_IO20 = 5,
+} IMX_IOMUXC_RGMII_TD0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_TD1_ALT0_HSI_RX_FLAG = 0,
+ IMX_IOMUXC_RGMII_TD1_ALT1_RGMII_TD1 = 1,
+ IMX_IOMUXC_RGMII_TD1_ALT5_GPIO6_IO21 = 5,
+} IMX_IOMUXC_RGMII_TD1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_TD2_ALT0_HSI_RX_DATA = 0,
+ IMX_IOMUXC_RGMII_TD2_ALT1_RGMII_TD2 = 1,
+ IMX_IOMUXC_RGMII_TD2_ALT5_GPIO6_IO22 = 5,
+} IMX_IOMUXC_RGMII_TD2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_TD3_ALT0_HSI_RX_WAKE = 0,
+ IMX_IOMUXC_RGMII_TD3_ALT1_RGMII_TD3 = 1,
+ IMX_IOMUXC_RGMII_TD3_ALT5_GPIO6_IO23 = 5,
+} IMX_IOMUXC_RGMII_TD3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_RX_CTL_ALT0_USB_H3_DATA = 0,
+ IMX_IOMUXC_RGMII_RX_CTL_ALT1_RGMII_RX_CTL = 1,
+ IMX_IOMUXC_RGMII_RX_CTL_ALT5_GPIO6_IO24 = 5,
+} IMX_IOMUXC_RGMII_RX_CTL_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_RD0_ALT0_HSI_RX_READY = 0,
+ IMX_IOMUXC_RGMII_RD0_ALT1_RGMII_RD0 = 1,
+ IMX_IOMUXC_RGMII_RD0_ALT5_GPIO6_IO25 = 5,
+} IMX_IOMUXC_RGMII_RD0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_TX_CTL_ALT0_USB_H2_STROBE = 0,
+ IMX_IOMUXC_RGMII_TX_CTL_ALT1_RGMII_TX_CTL = 1,
+ IMX_IOMUXC_RGMII_TX_CTL_ALT5_GPIO6_IO26 = 5,
+ IMX_IOMUXC_RGMII_TX_CTL_ALT7_ENET_REF_CLK = 7,
+} IMX_IOMUXC_RGMII_TX_CTL_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_RD1_ALT0_HSI_TX_FLAG = 0,
+ IMX_IOMUXC_RGMII_RD1_ALT1_RGMII_RD1 = 1,
+ IMX_IOMUXC_RGMII_RD1_ALT5_GPIO6_IO27 = 5,
+} IMX_IOMUXC_RGMII_RD1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_RD2_ALT0_HSI_TX_DATA = 0,
+ IMX_IOMUXC_RGMII_RD2_ALT1_RGMII_RD2 = 1,
+ IMX_IOMUXC_RGMII_RD2_ALT5_GPIO6_IO28 = 5,
+} IMX_IOMUXC_RGMII_RD2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_RD3_ALT0_HSI_TX_WAKE = 0,
+ IMX_IOMUXC_RGMII_RD3_ALT1_RGMII_RD3 = 1,
+ IMX_IOMUXC_RGMII_RD3_ALT5_GPIO6_IO29 = 5,
+} IMX_IOMUXC_RGMII_RD3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_RXC_ALT0_USB_H3_STROBE = 0,
+ IMX_IOMUXC_RGMII_RXC_ALT1_RGMII_RXC = 1,
+ IMX_IOMUXC_RGMII_RXC_ALT5_GPIO6_IO30 = 5,
+} IMX_IOMUXC_RGMII_RXC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_BCLK_ALT0_EIM_BCLK = 0,
+ IMX_IOMUXC_EIM_BCLK_ALT1_IPU1_DI1_PIN16 = 1,
+ IMX_IOMUXC_EIM_BCLK_ALT5_GPIO6_IO31 = 5,
+} IMX_IOMUXC_EIM_BCLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT5_ALT0_SD3_DATA5 = 0,
+ IMX_IOMUXC_SD3_DAT5_ALT1_UART2_TX_DATA = 1,
+ IMX_IOMUXC_SD3_DAT5_ALT5_GPIO7_IO00 = 5,
+} IMX_IOMUXC_SD3_DAT5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT4_ALT0_SD3_DATA4 = 0,
+ IMX_IOMUXC_SD3_DAT4_ALT1_UART2_RX_DATA = 1,
+ IMX_IOMUXC_SD3_DAT4_ALT5_GPIO7_IO01 = 5,
+} IMX_IOMUXC_SD3_DAT4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_CMD_ALT0_SD3_CMD = 0,
+ IMX_IOMUXC_SD3_CMD_ALT1_UART2_CTS_B = 1,
+ IMX_IOMUXC_SD3_CMD_ALT2_FLEXCAN1_TX = 2,
+ IMX_IOMUXC_SD3_CMD_ALT5_GPIO7_IO02 = 5,
+} IMX_IOMUXC_SD3_CMD_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_CLK_ALT0_SD3_CLK = 0,
+ IMX_IOMUXC_SD3_CLK_ALT1_UART2_RTS_B = 1,
+ IMX_IOMUXC_SD3_CLK_ALT2_FLEXCAN1_RX = 2,
+ IMX_IOMUXC_SD3_CLK_ALT5_GPIO7_IO03 = 5,
+} IMX_IOMUXC_SD3_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT0_ALT0_SD3_DATA0 = 0,
+ IMX_IOMUXC_SD3_DAT0_ALT1_UART1_CTS_B = 1,
+ IMX_IOMUXC_SD3_DAT0_ALT2_FLEXCAN2_TX = 2,
+ IMX_IOMUXC_SD3_DAT0_ALT5_GPIO7_IO04 = 5,
+} IMX_IOMUXC_SD3_DAT0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT1_ALT0_SD3_DATA1 = 0,
+ IMX_IOMUXC_SD3_DAT1_ALT1_UART1_RTS_B = 1,
+ IMX_IOMUXC_SD3_DAT1_ALT2_FLEXCAN2_RX = 2,
+ IMX_IOMUXC_SD3_DAT1_ALT5_GPIO7_IO05 = 5,
+} IMX_IOMUXC_SD3_DAT1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT2_ALT0_SD3_DATA2 = 0,
+ IMX_IOMUXC_SD3_DAT2_ALT5_GPIO7_IO06 = 5,
+} IMX_IOMUXC_SD3_DAT2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT3_ALT0_SD3_DATA3 = 0,
+ IMX_IOMUXC_SD3_DAT3_ALT1_UART3_CTS_B = 1,
+ IMX_IOMUXC_SD3_DAT3_ALT5_GPIO7_IO07 = 5,
+} IMX_IOMUXC_SD3_DAT3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_RST_ALT0_SD3_RESET = 0,
+ IMX_IOMUXC_SD3_RST_ALT1_UART3_RTS_B = 1,
+ IMX_IOMUXC_SD3_RST_ALT5_GPIO7_IO08 = 5,
+} IMX_IOMUXC_SD3_RST_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_CMD_ALT0_SD4_CMD = 0,
+ IMX_IOMUXC_SD4_CMD_ALT1_NAND_RE_B = 1,
+ IMX_IOMUXC_SD4_CMD_ALT2_UART3_TX_DATA = 2,
+ IMX_IOMUXC_SD4_CMD_ALT5_GPIO7_IO09 = 5,
+} IMX_IOMUXC_SD4_CMD_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_CLK_ALT0_SD4_CLK = 0,
+ IMX_IOMUXC_SD4_CLK_ALT1_NAND_WE_B = 1,
+ IMX_IOMUXC_SD4_CLK_ALT2_UART3_RX_DATA = 2,
+ IMX_IOMUXC_SD4_CLK_ALT5_GPIO7_IO10 = 5,
+} IMX_IOMUXC_SD4_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_16_ALT0_ESAI_TX3_RX2 = 0,
+ IMX_IOMUXC_GPIO_16_ALT1_ENET_1588_EVENT2_IN = 1,
+ IMX_IOMUXC_GPIO_16_ALT2_ENET_REF_CLK = 2,
+ IMX_IOMUXC_GPIO_16_ALT3_SD1_LCTL = 3,
+ IMX_IOMUXC_GPIO_16_ALT4_SPDIF_IN = 4,
+ IMX_IOMUXC_GPIO_16_ALT5_GPIO7_IO11 = 5,
+ IMX_IOMUXC_GPIO_16_ALT6_I2C3_SDA = 6,
+ IMX_IOMUXC_GPIO_16_ALT7_JTAG_DE_B = 7,
+} IMX_IOMUXC_GPIO_16_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_17_ALT0_ESAI_TX0 = 0,
+ IMX_IOMUXC_GPIO_17_ALT1_ENET_1588_EVENT3_IN = 1,
+ IMX_IOMUXC_GPIO_17_ALT2_CCM_PMIC_READY = 2,
+ IMX_IOMUXC_GPIO_17_ALT3_SDMA_EXT_EVENT0 = 3,
+ IMX_IOMUXC_GPIO_17_ALT4_SPDIF_OUT = 4,
+ IMX_IOMUXC_GPIO_17_ALT5_GPIO7_IO12 = 5,
+} IMX_IOMUXC_GPIO_17_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_18_ALT0_ESAI_TX1 = 0,
+ IMX_IOMUXC_GPIO_18_ALT1_ENET_RX_CLK = 1,
+ IMX_IOMUXC_GPIO_18_ALT2_SD3_VSELECT = 2,
+ IMX_IOMUXC_GPIO_18_ALT3_SDMA_EXT_EVENT1 = 3,
+ IMX_IOMUXC_GPIO_18_ALT4_ASRC_EXT_CLK = 4,
+ IMX_IOMUXC_GPIO_18_ALT5_GPIO7_IO13 = 5,
+ IMX_IOMUXC_GPIO_18_ALT6_SNVS_VIO_5_CTL = 6,
+} IMX_IOMUXC_GPIO_18_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ECSPI1_MISO_EIM_DATA17_ALT1 = 0,
+ IMX_IOMUXC_ECSPI1_MISO_DISP0_DATA22_ALT2 = 1,
+ IMX_IOMUXC_ECSPI1_MISO_KEY_COL1_ALT0 = 2,
+ IMX_IOMUXC_ECSPI1_MISO_CSI0_DATA06_ALT2 = 3,
+} IMX_IOMUXC_ECSPI1_MISO_SELECT_INPUT;
+
+typedef enum {
+ IMX_IOMUXC_ECSPI2_MISO_EIM_OE_B_ALT2 = 0,
+ IMX_IOMUXC_ECSPI2_MISO_DISP0_DATA17_ALT2 = 1,
+ IMX_IOMUXC_ECSPI2_MISO_CSI0_DATA10_ALT2 = 2,
+} IMX_IOMUXC_ECSPI2_MISO_SELECT_INPUT;
+
+#endif // _IMX6_IOMUX_DQ_H_
diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6IoMux_SDL.h b/Silicon/NXP/iMX6Pkg/Include/iMX6IoMux_SDL.h
new file mode 100644
index 000000000000..b8a0379ff811
--- /dev/null
+++ b/Silicon/NXP/iMX6Pkg/Include/iMX6IoMux_SDL.h
@@ -0,0 +1,2482 @@
+/** @file
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _IMX6_IOMUX_SDL_H_
+#define _IMX6_IOMUX_SDL_H_
+
+//
+// SELECT INPUT defines
+
+#define EIM_DATA21_ALT6 0x0 // Selecting ALT6 mode of pad EIM_D21 for I2C1_SCL
+#define CSI0_DAT9_ALT4 0x1 // Selecting ALT4 mode of pad CSI0_DAT9 for I2C1_SCL
+
+#define EIM_DATA28_ALT1 0x0 // Selecting ALT1 mode of pad EIM_D28 for I2C1_SDA
+#define CSI0_DAT8_ALT4 0x1 // Selecting ALT4 mode of pad CSI0_DAT8 for I2C1_SDA
+
+#define EIM_EB2_B_ALT6 0x0 // Selecting ALT6 mode of pad EIM_EB2 for I2C2_SCL
+#define KEY_COL3_ALT4 0x1 // Selecting ALT4 mode of pad KEY_COL3 for I2C2_SCL
+
+#define EIM_DATA16_ALT6 0x0 // Selecting ALT6 mode of pad EIM_D16 for I2C2_SDA
+#define KEY_ROW3_ALT4 0x1 // Selecting ALT4 mode of pad KEY_ROW3 for I2C2_SDA
+
+#define EIM_DATA17_ALT6 0x0 // Selecting ALT6 mode of pad EIM_D17 for I2C3_SCL
+#define GPIO03_ALT2 0x1 // Selecting ALT2 mode of pad GPIO_3 for I2C3_SCL
+#define GPIO05_ALT6 0x2 // Selecting ALT6 mode of pad GPIO_5 for I2C3_SCL
+
+#define EIM_DATA18_ALT6 0x0 // Selecting ALT6 mode of pad EIM_D18 for I2C3_SDA
+#define GPIO06_ALT2 0x1 // Selecting ALT2 mode of pad GPIO_6 for I2C3_SDA
+#define GPIO16_ALT6 0x2 // Selecting ALT6 mode of pad GPIO_16 for I2C3_SDA
+
+#define ENET_TX_EN_ALT9 0x0 // Selecting ALT9 mode of pad ENET_TX_EN for I2C4_SCL
+#define GPIO07_ALT8 0x1 // Selecting ALT8 mode of pad GPIO_7 for I2C4_SCL
+#define NAND_WP_B_ALT9 0x2 // Selecting ALT9 mode of pad NANDF_WP_B for I2C4_SCL
+
+#define ENET_TX_DATA1_ALT9 0x0 // Selecting ALT9 mode of pad ENET_TXD1 for I2C4_SDA
+#define GPIO08_ALT8 0x1 // Selecting ALT9 mode of pad GPIO_8 for I2C4_SDA
+#define NAND_CS3_B_ALT9 0x2 // Selecting ALT9 mode of pad NANDF_CS3 for I2C4_SDA
+
+#define DISP0_DATA19_ALT3 0
+#define KEY_ROW1_ALT2 1
+
+#define DISP0_DATA17_ALT3 0
+#define KEY_ROW0_ALT2 1
+
+#define DISP0_DATA16_ALT3 0
+#define KEY_COL0_ALT2 1
+
+#define DISP0_DATA18_ALT3 0
+#define KEY_COL1_ALT2 1
+
+#define EIM_DATA21_ALT4 0
+#define KEY_COL4_ALT2 1
+
+#define EIM_DATA30_ALT6 0
+#define GPIO03_ALT6 1
+
+#define RGMII_TX_CTL_ALT7 0
+#define GPIO16_ALT2 1
+
+#define CSI0_DATA10_ALT3 0 // Selecting ALT3 mode of pad CSI0_DAT10 for UART1_TX_DATA.
+#define CSI0_DATA11_ALT3 1 // Selecting ALT3 mode of pad CSI0_DAT11 for UART1_RX_DATA.
+#define SD3_DATA7_ALT1 2 // Selecting ALT1 mode of pad SD3_DAT7 for UART1_TX_DATA.
+#define SD3_DATA6_ALT1 3 // Selecting ALT1 mode of pad SD3_DAT6 for UART1_RX_DATA.
+
+#define EIM_DATA26_ALT4 0 // Selecting ALT4 mode of pad EIM_D26 for UART2_TX_DATA.
+#define EIM_DATA27_ALT4 1 // Selecting ALT4 mode of pad EIM_D27 for UART2_RX_DATA.
+#define GPIO07_ALT4 2 // Selecting ALT4 mode of pad GPIO_7 for UART2_TX_DATA.
+#define GPIO08_ALT4 3 // Selecting ALT4 mode of pad GPIO_8 for UART2_RX_DATA.
+#define SD3_DATA5_ALT1 4 // Selecting ALT1 mode of pad SD3_DAT5 for UART2_TX_DATA.
+#define SD3_DATA4_ALT1 5 // Selecting ALT1 mode of pad SD3_DAT4 for UART2_RX_DATA.
+#define SD4_DATA4_ALT2 6 // Selecting ALT2 mode of pad SD4_DAT4 for UART2_RX_DATA.
+#define SD4_DATA7_ALT2 7 // Selecting ALT2 mode of pad SD4_DAT7 for UART2_TX_DATA.
+
+#define EIM_DATA24_ALT2 0 // Selecting ALT2 mode of pad EIM_D24 for UART3_TX_DATA.
+#define EIM_DATA25_ALT2 1 // Selecting ALT2 mode of pad EIM_D25 for UART3_RX_DATA.
+#define SD4_CMD_ALT2 2 // Selecting ALT2 mode of pad SD4_CMD for UART3_TX_DATA.
+#define SD4_CLK_ALT2 3 // Selecting ALT2 mode of pad SD4_CLK for UART3_RX_DATA.
+
+
+//
+// AUD5 select input register defines.
+//
+typedef enum {
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO00) IOMUXC_SW_PAD_CTL_PAD_GPIO00 20E05DCh
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO00) IOMUXC_SW_MUX_CTL_PAD_GPIO00 20E020Ch
+ IMX_PAD_GPIO_0 = _IMX_PAD(0x5DC, 0x20C), // CCM_CLKO1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO01) IOMUXC_SW_PAD_CTL_PAD_GPIO01 20E05E0h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO01) IOMUXC_SW_MUX_CTL_PAD_GPIO01 20E0210h
+ IMX_PAD_GPIO_1 = _IMX_PAD(0x5E0, 0x210), // ESAI_RX_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO02)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO02)
+ IMX_PAD_GPIO_2 = _IMX_PAD(0x604, 0x234), // ESAI_TX_FS
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO03)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO03)
+ IMX_PAD_GPIO_3 = _IMX_PAD(0x5FC, 0x22C), // ESAI_RX_HF_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO04) IOMUXC_SW_PAD_CTL_PAD_GPIO04 20E05FCh
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO04) IOMUXC_SW_MUX_CTL_PAD_GPIO04 20E022Ch
+ IMX_PAD_GPIO_4 = _IMX_PAD(0x5FC, 0x22C), // ESAI_TX_HF_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO05)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO05)
+ IMX_PAD_GPIO_5 = _IMX_PAD(0x60C, 0x23C), // ESAI_TX2_RX3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO06)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO06)
+ IMX_PAD_GPIO_6 = _IMX_PAD(0x600, 0x230), // ESAI_TX_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO07)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO07)
+ IMX_PAD_GPIO_7 = _IMX_PAD(0x610, 0x240), // ESAI_TX4_RX1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO08)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO08)
+ IMX_PAD_GPIO_8 = _IMX_PAD(0x614, 0x244), // ESAI_TX5_RX0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO09)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO09)
+ IMX_PAD_GPIO_9 = _IMX_PAD(0x5F8, 0x228), // ESAI_RX_FS
+
+// SD host controller2 on DualLite
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_CLK) IOMUXC_SW_MUX_CTL_PAD_SD2_CLK 20E02F4h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_CLK) IOMUXC_SW_PAD_CTL_PAD_SD2_CLK 20E06DCh
+ IMX_PAD_SD2_CLK = _IMX_PAD(0x6DC, 0x2F4), // SD2_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_CMD) IOMUXC_SW_MUX_CTL_PAD_SD2_CMD 20E02F8h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_CMD) IOMUXC_SW_PAD_CTL_PAD_SD2_CMD 20E06E0h
+ IMX_PAD_SD2_CMD = _IMX_PAD(0x6E0, 0x2F8), // SD2_CMD
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0) IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0 20E02FCh
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0) IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0 20E06E4h
+ IMX_PAD_SD2_DAT0 = _IMX_PAD(0x6E4, 0x2FC), // SD2_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1) IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1 20E0300h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1) IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1 20E06E8h
+ IMX_PAD_SD2_DAT1 = _IMX_PAD(0x6E8, 0x300), // SD2_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2) IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2 20E0304h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2) IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2 20E06ECh
+ IMX_PAD_SD2_DAT2 = _IMX_PAD(0x6EC, 0x304), // SD2_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3) IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3 20E0308h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3) IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3 20E06F0h
+ IMX_PAD_SD2_DAT3 = _IMX_PAD(0x6F0, 0x308), // SD2_DATA3
+
+// SD host controller1 on DualLite
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0)
+ IMX_PAD_SD1_DAT0 = _IMX_PAD(0x728, 0x340), // SD1_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1)
+ IMX_PAD_SD1_DAT1 = _IMX_PAD(0x724, 0x33C), // SD1_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_CMD)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_CMD)
+ IMX_PAD_SD1_CMD = _IMX_PAD(0x730, 0x348), // SD1_CMD
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2)
+ IMX_PAD_SD1_DAT2 = _IMX_PAD(0x734, 0x34C), // SD1_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_CLK)
+ IMX_PAD_SD1_CLK = _IMX_PAD(0x738, 0x350), // SD1_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3)
+ IMX_PAD_SD1_DAT3 = _IMX_PAD(0x72C, 0x344), // SD1_DATA3
+
+// Ethernet controller on DualLite
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_MDIO)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_MDIO)
+ IMX_PAD_ENET_MDIO = _IMX_PAD(0x4E4, 0x1D0), // ENET_MDIO
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_REF_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_REF_CLK)
+ IMX_PAD_ENET_REF_CLK = _IMX_PAD(0x4E8, 0x1D4), // ENET_TX_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_RX_ER)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_RX_ER)
+ IMX_PAD_ENET_RX_ER = _IMX_PAD(0x4EC, 0x1D8), // USB_OTG_ID
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_CRS_DV)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_CRS_DV)
+ IMX_PAD_ENET_CRS_DV = _IMX_PAD(0x4F0, 0x1DC), // ENET_RX_EN
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA1)
+ IMX_PAD_ENET_RXD1 = _IMX_PAD(0x4F4, 0x1E0), // MLB_SIG
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_RX_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_RX_DATA0)
+ IMX_PAD_ENET_RXD0 = _IMX_PAD(0x4F8, 0x1E4), // XTALOSC_OSC32K_32K_OUT
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_TX_EN)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_TX_EN)
+ IMX_PAD_ENET_TX_EN = _IMX_PAD(0x4FC, 0x1E8), // ENET_TX_EN
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA1)
+ IMX_PAD_ENET_TXD1 = _IMX_PAD(0x500, 0x1EC), // MLB_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_TX_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_TX_DATA0)
+ IMX_PAD_ENET_TXD0 = _IMX_PAD(0x504, 0x1F0), // ENET_TX_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET_MDC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET_MDC)
+ IMX_PAD_ENET_MDC = _IMX_PAD(0x508, 0x1F4), // MLB_DATA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00)
+ IMX_PAD_NANDF_D0 = _IMX_PAD(0x6E4, 0x2FC), // NAND_DATA00
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01)
+ IMX_PAD_NANDF_D1 = _IMX_PAD(0x6E8, 0x300), // NAND_DATA01
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02)
+ IMX_PAD_NANDF_D2 = _IMX_PAD(0x6EC, 0x304), // NAND_DATA02
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03)
+ IMX_PAD_NANDF_D3 = _IMX_PAD(0x6F0, 0x308), // NAND_DATA03
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04)
+ IMX_PAD_NANDF_D4 = _IMX_PAD(0x6F4, 0x30C), // NAND_DATA04
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05)
+ IMX_PAD_NANDF_D5 = _IMX_PAD(0x6F8, 0x310), // NAND_DATA05
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06)
+ IMX_PAD_NANDF_D6 = _IMX_PAD(0x6FC, 0x314), // NAND_DATA06
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07)
+ IMX_PAD_NANDF_D7 = _IMX_PAD(0x700, 0x318), // NAND_DATA07
+
+// SD host controller4 on DualLite
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0)
+ IMX_PAD_SD4_DAT0 = _IMX_PAD(0x704, 0x31C), // SD4_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1)
+ IMX_PAD_SD4_DAT1 = _IMX_PAD(0x708, 0x320), // SD4_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2)
+ IMX_PAD_SD4_DAT2 = _IMX_PAD(0x70C, 0x324), // SD4_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3) IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3 20E0734h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3) IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3 20E034Ch
+ IMX_PAD_SD4_DAT3 = _IMX_PAD(0x734, 0x34C), // SD4_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4)
+ IMX_PAD_SD4_DAT4 = _IMX_PAD(0x714, 0x32C), // SD4_DATA4
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5)
+ IMX_PAD_SD4_DAT5 = _IMX_PAD(0x718, 0x330), // SD4_DATA5
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6)
+ IMX_PAD_SD4_DAT6 = _IMX_PAD(0x71C, 0x334), // SD4_DATA6
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7)
+ IMX_PAD_SD4_DAT7 = _IMX_PAD(0x720, 0x338), // SD4_DATA7
+
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR22)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR22)
+ IMX_PAD_EIM_A22 = _IMX_PAD(0x3F0, 0xDC), // EIM_ADDR22
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR21)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR21)
+ IMX_PAD_EIM_A21 = _IMX_PAD(0x3F4, 0xE0), // EIM_ADDR21
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR20)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR20)
+ IMX_PAD_EIM_A20 = _IMX_PAD(0x3F8, 0xE4), // EIM_ADDR20
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR19)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR19)
+ IMX_PAD_EIM_A19 = _IMX_PAD(0x3FC, 0xE8), // EIM_ADDR19
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR18)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR18)
+ IMX_PAD_EIM_A18 = _IMX_PAD(0x400, 0xEC), // EIM_ADDR18
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR17)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR17)
+ IMX_PAD_EIM_A17 = _IMX_PAD(0x404, 0xF0), // EIM_ADDR17
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR16)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR16)
+ IMX_PAD_EIM_A16 = _IMX_PAD(0x408, 0xF4), // EIM_ADDR16
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_CS0_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_CS0_B)
+ IMX_PAD_EIM_CS0 = _IMX_PAD(0x40C, 0xF8), // EIM_CS0_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_CS1_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_CS1_B)
+ IMX_PAD_EIM_CS1 = _IMX_PAD(0x410, 0xFC), // EIM_CS1_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_OE_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_OE_B)
+ IMX_PAD_EIM_OE = _IMX_PAD(0x414, 0x100), // EIM_OE_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_RW)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_RW)
+ IMX_PAD_EIM_RW = _IMX_PAD(0x418, 0x104), // EIM_RW
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_LBA_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_LBA_B)
+ IMX_PAD_EIM_LBA = _IMX_PAD(0x41C, 0x108), // EIM_LBA_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_EB0_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_EB0_B)
+ IMX_PAD_EIM_EB0 = _IMX_PAD(0x420, 0x10C), // EIM_EB0_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_EB1_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_EB1_B)
+ IMX_PAD_EIM_EB1 = _IMX_PAD(0x424, 0x110), // EIM_EB1_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_EB2_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_EB2_B)
+ IMX_PAD_EIM_EB2 = _IMX_PAD(0x3A0, 0x8C), // EIM_EB2_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_B) IOMUXC_SW_PAD_CTL_PAD_EIM_EB3_B 20E05A0h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_B) IOMUXC_SW_MUX_CTL_PAD_EIM_EB3_B 20E01D0h
+ IMX_PAD_EIM_EB3 = _IMX_PAD(0x5A0, 0x1D0), // EIM_EB3_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD00)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD00)
+ IMX_PAD_EIM_DA0 = _IMX_PAD(0x428, 0x114), // EIM_AD00
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD01)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD01)
+ IMX_PAD_EIM_DA1 = _IMX_PAD(0x42C, 0x118), // EIM_AD01
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD02)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD02)
+ IMX_PAD_EIM_DA2 = _IMX_PAD(0x430, 0x11C), // EIM_AD02
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD03)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD03)
+ IMX_PAD_EIM_DA3 = _IMX_PAD(0x434, 0x120), // EIM_AD03
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD04)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD04)
+ IMX_PAD_EIM_DA4 = _IMX_PAD(0x438, 0x124), // EIM_AD04
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD05)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD05)
+ IMX_PAD_EIM_DA5 = _IMX_PAD(0x43C, 0x128), // EIM_AD05
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD06)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD06)
+ IMX_PAD_EIM_DA6 = _IMX_PAD(0x440, 0x12C), // EIM_AD06
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD07)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD07)
+ IMX_PAD_EIM_DA7 = _IMX_PAD(0x444, 0x130), // EIM_AD07
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD08)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD08)
+ IMX_PAD_EIM_DA8 = _IMX_PAD(0x448, 0x134), // EIM_AD08
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD09)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD09)
+ IMX_PAD_EIM_DA9 = _IMX_PAD(0x44C, 0x138), // EIM_AD09
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD10)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD10)
+ IMX_PAD_EIM_DA10 = _IMX_PAD(0x450, 0x13C), // EIM_AD10
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD11)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD11)
+ IMX_PAD_EIM_DA11 = _IMX_PAD(0x454, 0x140), // EIM_AD11
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD12)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD12)
+ IMX_PAD_EIM_DA12 = _IMX_PAD(0x458, 0x144), // EIM_AD12
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD13)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD13)
+ IMX_PAD_EIM_DA13 = _IMX_PAD(0x45C, 0x148), // EIM_AD13
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD14)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD14)
+ IMX_PAD_EIM_DA14 = _IMX_PAD(0x460, 0x14C), // EIM_AD14
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_AD15)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_AD15)
+ IMX_PAD_EIM_DA15 = _IMX_PAD(0x464, 0x150), // EIM_AD15
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA16)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA16)
+ IMX_PAD_EIM_D16 = _IMX_PAD(0x3A4, 0x90), // EIM_DATA16
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17) IOMUXC_SW_PAD_CTL_PAD_EIM_DATA17 20E0518h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA17 20E0148h
+ IMX_PAD_EIM_D17 = _IMX_PAD(0x518, 0x148), // EIM_DATA17
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18) IOMUXC_SW_PAD_CTL_PAD_EIM_DATA18 20E051Ch
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA18 20E014C
+ IMX_PAD_EIM_D18 = _IMX_PAD(0x51C, 0x14C), // EIM_DATA18
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA19)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA19)
+ IMX_PAD_EIM_D19 = _IMX_PAD(0x3B0, 0x9C), // EIM_DATA19
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20)
+ IMX_PAD_EIM_D20 = _IMX_PAD(0x3B4, 0xA0), // EIM_DATA20
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21) IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21 20E0528h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21 20E0158h
+ IMX_PAD_EIM_D21 = _IMX_PAD(0x528, 0x158), // EIM_DATA21
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22) IOMUXC_SW_PAD_CTL_PAD_EIM_DATA22 20E052Ch
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA22 20E015Ch
+ IMX_PAD_EIM_D22 = _IMX_PAD(0x52C, 0x15C), // EIM_DATA22
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA23)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA23)
+ IMX_PAD_EIM_D23 = _IMX_PAD(0x3C0, 0xAC), // EIM_DATA23
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24) IOMUXC_SW_PAD_CTL_PAD_EIM_DATA24 20E0534h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA24 20E0164h
+ IMX_PAD_EIM_D24 = _IMX_PAD(0x534, 0x164), // EIM_DATA24
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25) IOMUXC_SW_PAD_CTL_PAD_EIM_DATA25 20E0538h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA25 20E0168h
+ IMX_PAD_EIM_D25 = _IMX_PAD(0x538, 0x168), // EIM_DATA25
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA26)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA26)
+ IMX_PAD_EIM_D26 = _IMX_PAD(0x3D0, 0xBC), // EIM_DATA26
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA27)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA27)
+ IMX_PAD_EIM_D27 = _IMX_PAD(0x3D4, 0xC0), // EIM_DATA27
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28) IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28 20E0544h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28) IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28 20E0174h
+ IMX_PAD_EIM_D28 = _IMX_PAD(0x5448, 0x174), // EIM_DATA28
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA29)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA29)
+ IMX_PAD_EIM_D29 = _IMX_PAD(0x3DC, 0xC8), // EIM_DATA29
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA30)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA30)
+ IMX_PAD_EIM_D30 = _IMX_PAD(0x3E0, 0xCC), // EIM_DATA30
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_DATA31)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_DATA31)
+ IMX_PAD_EIM_D31 = _IMX_PAD(0x3E4, 0xD0), // EIM_DATA31
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO19)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO19)
+ IMX_PAD_GPIO_19 = _IMX_PAD(0x624, 0x254), // KEY_COL5
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL0)
+ IMX_PAD_KEY_COL0 = _IMX_PAD(0x5C8, 0x1F8), // ECSPI1_SCLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0)
+ IMX_PAD_KEY_ROW0 = _IMX_PAD(0x5CC, 0x1FC), // ECSPI1_MOSI
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL1)
+ IMX_PAD_KEY_COL1 = _IMX_PAD(0x5D0, 0x200), // ECSPI1_MISO
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1) IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 20E0644h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1) IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 20E025Ch
+ IMX_PAD_KEY_ROW1 = _IMX_PAD(0x644, 0x25C), // ECSPI1_SS0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL2)
+ IMX_PAD_KEY_COL2 = _IMX_PAD(0x5D8, 0x208), // ECSPI1_SS1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2)
+ IMX_PAD_KEY_ROW2 = _IMX_PAD(0x5DC, 0x20C), // ECSPI1_SS2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL3)
+ IMX_PAD_KEY_COL3 = _IMX_PAD(0x5E0, 0x210), // ECSPI1_SS3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3)
+ IMX_PAD_KEY_ROW3 = _IMX_PAD(0x5E4, 0x214), // XTALOSC_OSC32K_32K_OUT
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL4) IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 20E063Ch
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL4) IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 20E0254h
+ IMX_PAD_KEY_COL4 = _IMX_PAD(0x63C, 0x254), // FLEXCAN2_TX
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4)
+ IMX_PAD_KEY_ROW4 = _IMX_PAD(0x5EC, 0x21C), // FLEXCAN2_RX
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DI0_DISP_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DI0_DISP_CLK)
+ IMX_PAD_DI0_DISP_CLK = _IMX_PAD(0x470, 0x15C), // IPU1_DI0_DISP_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DI0_PIN15)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DI0_PIN15)
+ IMX_PAD_DI0_PIN15 = _IMX_PAD(0x474, 0x160), // IPU1_DI0_PIN15
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DI0_PIN02)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DI0_PIN02)
+ IMX_PAD_DI0_PIN2 = _IMX_PAD(0x478, 0x164), // IPU1_DI0_PIN02
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DI0_PIN03)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DI0_PIN03)
+ IMX_PAD_DI0_PIN3 = _IMX_PAD(0x47C, 0x168), // IPU1_DI0_PIN03
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DI0_PIN04)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DI0_PIN04)
+ IMX_PAD_DI0_PIN4 = _IMX_PAD(0x480, 0x16C), // IPU1_DI0_PIN04
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00) IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA00 20E03C4h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA00 20E00B0h
+ IMX_PAD_DISP0_DAT0 = _IMX_PAD(0x3C4, 0xB0), // IPU1_DISP0_DATA00
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA01)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA01)
+ IMX_PAD_DISP0_DAT1 = _IMX_PAD(0x488, 0x174), // IPU1_DISP0_DATA01
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA02)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA02)
+ IMX_PAD_DISP0_DAT2 = _IMX_PAD(0x48C, 0x178), // IPU1_DISP0_DATA02
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA03)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA03)
+ IMX_PAD_DISP0_DAT3 = _IMX_PAD(0x490, 0x17C), // IPU1_DISP0_DATA03
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA04)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA04)
+ IMX_PAD_DISP0_DAT4 = _IMX_PAD(0x494, 0x180), // IPU1_DISP0_DATA04
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA05)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA05)
+ IMX_PAD_DISP0_DAT5 = _IMX_PAD(0x498, 0x184), // IPU1_DISP0_DATA05
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA06)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA06)
+ IMX_PAD_DISP0_DAT6 = _IMX_PAD(0x49C, 0x188), // IPU1_DISP0_DATA06
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA07)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA07)
+ IMX_PAD_DISP0_DAT7 = _IMX_PAD(0x4A0, 0x18C), // IPU1_DISP0_DATA07
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA08)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA08)
+ IMX_PAD_DISP0_DAT8 = _IMX_PAD(0x4A4, 0x190), // IPU1_DISP0_DATA08
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09) IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA09 20E0420h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09) IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA09 20E010Ch
+ IMX_PAD_DISP0_DAT9 = _IMX_PAD(0x420, 0x10C), // IPU1_DISP0_DATA09
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA10)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA10)
+ IMX_PAD_DISP0_DAT10 = _IMX_PAD(0x4AC, 0x198), // IPU1_DISP0_DATA10
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_WAIT_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_WAIT_B)
+ IMX_PAD_EIM_WAIT = _IMX_PAD(0x468, 0x154), // EIM_WAIT_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR25)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR25)
+ IMX_PAD_EIM_A25 = _IMX_PAD(0x39C, 0x88), // EIM_ADDR25
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR24)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR24)
+ IMX_PAD_EIM_A24 = _IMX_PAD(0x3E8, 0xD4), // EIM_ADDR24
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA11)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA11)
+ IMX_PAD_DISP0_DAT11 = _IMX_PAD(0x4B0, 0x19C), // IPU1_DISP0_DATA11
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA12)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA12)
+ IMX_PAD_DISP0_DAT12 = _IMX_PAD(0x4B4, 0x1A0), // IPU1_DISP0_DATA12
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA13)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA13)
+ IMX_PAD_DISP0_DAT13 = _IMX_PAD(0x4B8, 0x1A4), // IPU1_DISP0_DATA13
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA14)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA14)
+ IMX_PAD_DISP0_DAT14 = _IMX_PAD(0x4BC, 0x1A8), // IPU1_DISP0_DATA14
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA15)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA15)
+ IMX_PAD_DISP0_DAT15 = _IMX_PAD(0x4C0, 0x1AC), // IPU1_DISP0_DATA15
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA16)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA16)
+ IMX_PAD_DISP0_DAT16 = _IMX_PAD(0x4C4, 0x1B0), // IPU1_DISP0_DATA16
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA17)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA17)
+ IMX_PAD_DISP0_DAT17 = _IMX_PAD(0x4C8, 0x1B4), // IPU1_DISP0_DATA17
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA18)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA18)
+ IMX_PAD_DISP0_DAT18 = _IMX_PAD(0x4CC, 0x1B8), // IPU1_DISP0_DATA18
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA19)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA19)
+ IMX_PAD_DISP0_DAT19 = _IMX_PAD(0x4D0, 0x1BC), // IPU1_DISP0_DATA19
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA20)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA20)
+ IMX_PAD_DISP0_DAT20 = _IMX_PAD(0x4D4, 0x1C0), // IPU1_DISP0_DATA20
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA21)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA21)
+ IMX_PAD_DISP0_DAT21 = _IMX_PAD(0x4D8, 0x1C4), // IPU1_DISP0_DATA21
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA22)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA22)
+ IMX_PAD_DISP0_DAT22 = _IMX_PAD(0x4DC, 0x1C8), // IPU1_DISP0_DATA22
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_DISP0_DATA23)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_DISP0_DATA23)
+ IMX_PAD_DISP0_DAT23 = _IMX_PAD(0x4E0, 0x1CC), // IPU1_DISP0_DATA23
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_PIXCLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_PIXCLK)
+ IMX_PAD_CSI0_PIXCLK = _IMX_PAD(0x628, 0x258), // IPU1_CSI0_PIXCLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_HSYNC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_HSYNC)
+ IMX_PAD_CSI0_MCLK = _IMX_PAD(0x62C, 0x25C), // IPU1_CSI0_HSYNC
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA_EN)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA_EN)
+ IMX_PAD_CSI0_DATA_EN = _IMX_PAD(0x630, 0x260), // IPU1_CSI0_DATA_EN
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_VSYNC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_VSYNC)
+ IMX_PAD_CSI0_VSYNC = _IMX_PAD(0x634, 0x264), // IPU1_CSI0_VSYNC
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA04)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA04)
+ IMX_PAD_CSI0_DAT4 = _IMX_PAD(0x638, 0x268), // IPU1_CSI0_DATA04
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA05)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA05)
+ IMX_PAD_CSI0_DAT5 = _IMX_PAD(0x63C, 0x26C), // IPU1_CSI0_DATA05
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA06)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA06)
+ IMX_PAD_CSI0_DAT6 = _IMX_PAD(0x640, 0x270), // IPU1_CSI0_DATA06
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA07)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA07)
+ IMX_PAD_CSI0_DAT7 = _IMX_PAD(0x644, 0x274), // IPU1_CSI0_DATA07
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA08)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA08)
+ IMX_PAD_CSI0_DAT8 = _IMX_PAD(0x648, 0x278), // IPU1_CSI0_DATA08
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA09)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA09)
+ IMX_PAD_CSI0_DAT9 = _IMX_PAD(0x64C, 0x27C), // IPU1_CSI0_DATA09
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10) IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA10 20E0360h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA10 20E004Ch
+ IMX_PAD_CSI0_DAT10 = _IMX_PAD(0x360, 0x4C), // IPU1_CSI0_DATA10
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11) IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA11 20E0364h
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11) IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA11 20E0050h
+ IMX_PAD_CSI0_DAT11 = _IMX_PAD(0x364, 0x50), // IPU1_CSI0_DATA11
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA12)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA12)
+ IMX_PAD_CSI0_DAT12 = _IMX_PAD(0x658, 0x288), // IPU1_CSI0_DATA12
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA13)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA13)
+ IMX_PAD_CSI0_DAT13 = _IMX_PAD(0x65C, 0x28C), // IPU1_CSI0_DATA13
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA14)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA14)
+ IMX_PAD_CSI0_DAT14 = _IMX_PAD(0x660, 0x290), // IPU1_CSI0_DATA14
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA15)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA15)
+ IMX_PAD_CSI0_DAT15 = _IMX_PAD(0x664, 0x294), // IPU1_CSI0_DATA15
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA16)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA16)
+ IMX_PAD_CSI0_DAT16 = _IMX_PAD(0x668, 0x298), // IPU1_CSI0_DATA16
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA17)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA17)
+ IMX_PAD_CSI0_DAT17 = _IMX_PAD(0x66C, 0x29C), // IPU1_CSI0_DATA17
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA18)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA18)
+ IMX_PAD_CSI0_DAT18 = _IMX_PAD(0x670, 0x2A0), // IPU1_CSI0_DATA18
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI0_DATA19)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI0_DATA19)
+ IMX_PAD_CSI0_DAT19 = _IMX_PAD(0x674, 0x2A4), // IPU1_CSI0_DATA19
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_ADDR23)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_ADDR23)
+ IMX_PAD_EIM_A23 = _IMX_PAD(0x3EC, 0xD8), // EIM_ADDR23
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CLE)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CLE)
+ IMX_PAD_NANDF_CLE = _IMX_PAD(0x6BC, 0x2D4), // NAND_CLE
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_ALE)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_ALE)
+ IMX_PAD_NANDF_ALE = _IMX_PAD(0x6C0, 0x2D8), // NAND_ALE
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B)
+ IMX_PAD_NANDF_WP_B = _IMX_PAD(0x6C4, 0x2DC), // NAND_WP_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B)
+ IMX_PAD_NANDF_RB0 = _IMX_PAD(0x6C8, 0x2E0), // NAND_READY_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CS0_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B)
+ IMX_PAD_NANDF_CS0 = _IMX_PAD(0x6CC, 0x2E4), // NAND_CE0_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CS1_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CS1_B)
+ IMX_PAD_NANDF_CS1 = _IMX_PAD(0x6D0, 0x2E8), // NAND_CE1_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CS2_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B)
+ IMX_PAD_NANDF_CS2 = _IMX_PAD(0x6D4, 0x2EC), // NAND_CE2_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CS3_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CS3_B)
+ IMX_PAD_NANDF_CS3 = _IMX_PAD(0x6D8, 0x2F0), // NAND_CE3_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7)
+ IMX_PAD_SD3_DAT7 = _IMX_PAD(0x690, 0x2A8), // SD3_DATA7
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6)
+ IMX_PAD_SD3_DAT6 = _IMX_PAD(0x694, 0x2AC), // SD3_DATA6
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_TXC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_TXC)
+ IMX_PAD_RGMII_TXC = _IMX_PAD(0x36C, 0x58), // USB_H2_DATA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_TD0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_TD0)
+ IMX_PAD_RGMII_TD0 = _IMX_PAD(0x370, 0x5C), // HSI_TX_READY
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_TD1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_TD1)
+ IMX_PAD_RGMII_TD1 = _IMX_PAD(0x374, 0x60), // HSI_RX_FLAG
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_TD2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_TD2)
+ IMX_PAD_RGMII_TD2 = _IMX_PAD(0x378, 0x64), // HSI_RX_DATA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_TD3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_TD3)
+ IMX_PAD_RGMII_TD3 = _IMX_PAD(0x37C, 0x68), // HSI_RX_WAKE
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_RX_CTL)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_RX_CTL)
+ IMX_PAD_RGMII_RX_CTL = _IMX_PAD(0x380, 0x6C), // USB_H3_DATA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_RD0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_RD0)
+ IMX_PAD_RGMII_RD0 = _IMX_PAD(0x384, 0x70), // HSI_RX_READY
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_TX_CTL)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_TX_CTL)
+ IMX_PAD_RGMII_TX_CTL = _IMX_PAD(0x388, 0x74), // USB_H2_STROBE
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_RD1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_RD1)
+ IMX_PAD_RGMII_RD1 = _IMX_PAD(0x38C, 0x78), // HSI_TX_FLAG
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_RD2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_RD2)
+ IMX_PAD_RGMII_RD2 = _IMX_PAD(0x390, 0x7C), // HSI_TX_DATA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_RD3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_RD3)
+ IMX_PAD_RGMII_RD3 = _IMX_PAD(0x394, 0x80), // HSI_TX_WAKE
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII_RXC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII_RXC)
+ IMX_PAD_RGMII_RXC = _IMX_PAD(0x398, 0x84), // USB_H3_STROBE
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK)
+ IMX_PAD_EIM_BCLK = _IMX_PAD(0x46C, 0x158), // EIM_BCLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5)
+ IMX_PAD_SD3_DAT5 = _IMX_PAD(0x698, 0x2B0), // SD3_DATA5
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4)
+ IMX_PAD_SD3_DAT4 = _IMX_PAD(0x69C, 0x2B4), // SD3_DATA4
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_CMD)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_CMD)
+ IMX_PAD_SD3_CMD = _IMX_PAD(0x6A0, 0x2B8), // SD3_CMD
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_CLK)
+ IMX_PAD_SD3_CLK = _IMX_PAD(0x6A4, 0x2BC), // SD3_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0)
+ IMX_PAD_SD3_DAT0 = _IMX_PAD(0x6A8, 0x2C0), // SD3_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1)
+ IMX_PAD_SD3_DAT1 = _IMX_PAD(0x6AC, 0x2C4), // SD3_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2)
+ IMX_PAD_SD3_DAT2 = _IMX_PAD(0x6B0, 0x2C8), // SD3_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3)
+ IMX_PAD_SD3_DAT3 = _IMX_PAD(0x6B4, 0x2CC), // SD3_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_RESET)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_RESET)
+ IMX_PAD_SD3_RST = _IMX_PAD(0x6B8, 0x2D0), // SD3_RESET
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_CMD)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_CMD)
+ IMX_PAD_SD4_CMD = _IMX_PAD(0x6DC, 0x2F4), // SD4_CMD
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_CLK)
+ IMX_PAD_SD4_CLK = _IMX_PAD(0x6E0, 0x2F8), // SD4_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO16)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO16)
+ IMX_PAD_GPIO_16 = _IMX_PAD(0x618, 0x248), // ESAI_TX3_RX2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO17)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO17)
+ IMX_PAD_GPIO_17 = _IMX_PAD(0x61C, 0x24C), // ESAI_TX0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO18)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO18)
+ IMX_PAD_GPIO_18 = _IMX_PAD(0x620, 0x250), // ESAI_TX1
+} IMX_PAD;
+
+//
+// Alternate function numbers
+//
+
+typedef enum {
+ IMX_IOMUXC_GPIO_0_ALT0_CCM_CLKO1 = 0,
+ IMX_IOMUXC_GPIO_0_ALT2_KEY_COL5 = 2,
+ IMX_IOMUXC_GPIO_0_ALT3_ASRC_EXT_CLK = 3,
+ IMX_IOMUXC_GPIO_0_ALT4_EPIT1_OUT = 4,
+ IMX_IOMUXC_GPIO_0_ALT5_GPIO1_IO00 = 5,
+ IMX_IOMUXC_GPIO_0_ALT6_USB_H1_PWR = 6,
+ IMX_IOMUXC_GPIO_0_ALT7_SNVS_VIO_5 = 7,
+} IMX_IOMUXC_GPIO_0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_1_ALT0_ESAI_RX_CLK = 0,
+ IMX_IOMUXC_GPIO_1_ALT1_WDOG2_B = 1,
+ IMX_IOMUXC_GPIO_1_ALT2_KEY_ROW5 = 2,
+ IMX_IOMUXC_GPIO_1_ALT3_USB_OTG_ID = 3,
+ IMX_IOMUXC_GPIO_1_ALT4_PWM2_OUT = 4,
+ IMX_IOMUXC_GPIO_1_ALT5_GPIO1_IO01 = 5,
+ IMX_IOMUXC_GPIO_1_ALT6_SD1_CD_B = 6, // in
+} IMX_IOMUXC_GPIO_1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_2_ALT0_ESAI_TX_FS = 0,
+ IMX_IOMUXC_GPIO_2_ALT2_KEY_ROW6 = 2,
+ IMX_IOMUXC_GPIO_2_ALT5_GPIO1_IO02 = 5,
+ IMX_IOMUXC_GPIO_2_ALT6_SD2_WP = 6,
+ IMX_IOMUXC_GPIO_2_ALT7_MLB_DATA = 7,
+} IMX_IOMUXC_GPIO_2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_3_ALT0_ESAI_RX_HF_CLK = 0,
+ IMX_IOMUXC_GPIO_3_ALT2_I2C3_SCL = 2,
+ IMX_IOMUXC_GPIO_3_ALT3_XTALOSC_REF_CLK_24M = 3,
+ IMX_IOMUXC_GPIO_3_ALT4_CCM_CLKO2 = 4,
+ IMX_IOMUXC_GPIO_3_ALT5_GPIO1_IO03 = 5,
+ IMX_IOMUXC_GPIO_3_ALT6_USB_H1_OC = 6,
+ IMX_IOMUXC_GPIO_3_ALT7_MLB_CLK = 7,
+} IMX_IOMUXC_GPIO_3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_4_ALT0_ESAI_TX_HF_CLK = 0,
+ IMX_IOMUXC_GPIO_4_ALT2_KEY_COL7 = 2,
+ IMX_IOMUXC_GPIO_4_ALT5_GPIO1_IO04 = 5,
+ IMX_IOMUXC_GPIO_4_ALT6_SD2_CD_B = 6,
+} IMX_IOMUXC_GPIO_4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_5_ALT0_ESAI_TX2_RX3 = 0,
+ IMX_IOMUXC_GPIO_5_ALT2_KEY_ROW7 = 2,
+ IMX_IOMUXC_GPIO_5_ALT3_CCM_CLKO1 = 3,
+ IMX_IOMUXC_GPIO_5_ALT5_GPIO1_IO05 = 5,
+ IMX_IOMUXC_GPIO_5_ALT6_I2C3_SCL = 6,
+ IMX_IOMUXC_GPIO_5_ALT7_ARM_EVENTI = 7,
+} IMX_IOMUXC_GPIO_5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_6_ALT0_ESAI_TX_CLK = 0,
+ IMX_IOMUXC_GPIO_6_ALT2_I2C3_SDA = 2,
+ IMX_IOMUXC_GPIO_6_ALT5_GPIO1_IO06 = 5,
+ IMX_IOMUXC_GPIO_6_ALT6_SD2_LCTL = 6,
+ IMX_IOMUXC_GPIO_6_ALT7_MLB_SIG = 7,
+} IMX_IOMUXC_GPIO_6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_7_ALT0_ESAI_TX4_RX1 = 0,
+ IMX_IOMUXC_GPIO_7_ALT1_ECSPI5_RDY = 1,
+ IMX_IOMUXC_GPIO_7_ALT2_EPIT1_OUT = 2,
+ IMX_IOMUXC_GPIO_7_ALT3_FLEXCAN1_TX = 3,
+ IMX_IOMUXC_GPIO_7_ALT4_UART2_TX_DATA = 4,
+ IMX_IOMUXC_GPIO_7_ALT5_GPIO1_IO07 = 5,
+ IMX_IOMUXC_GPIO_7_ALT6_SPDIF_LOCK = 6,
+ IMX_IOMUXC_GPIO_7_ALT7_USB_OTG_HOST_MODE = 7,
+} IMX_IOMUXC_GPIO_7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_8_ALT0_ESAI_TX5_RX0 = 0,
+ IMX_IOMUXC_GPIO_8_ALT1_XTALOSC_REF_CLK_32K = 1,
+ IMX_IOMUXC_GPIO_8_ALT2_EPIT2_OUT = 2,
+ IMX_IOMUXC_GPIO_8_ALT3_FLEXCAN1_RX = 3,
+ IMX_IOMUXC_GPIO_8_ALT4_UART2_RX_DATA = 4,
+ IMX_IOMUXC_GPIO_8_ALT5_GPIO1_IO08 = 5,
+ IMX_IOMUXC_GPIO_8_ALT6_SPDIF_SR_CLK = 6,
+ IMX_IOMUXC_GPIO_8_ALT7_USB_OTG_PWR_CTL_WAKE = 7,
+} IMX_IOMUXC_GPIO_8_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_9_ALT0_ESAI_RX_FS = 0,
+ IMX_IOMUXC_GPIO_9_ALT1_WDOG1_B = 1,
+ IMX_IOMUXC_GPIO_9_ALT2_KEY_COL6 = 2,
+ IMX_IOMUXC_GPIO_9_ALT3_CCM_REF_EN_B = 3,
+ IMX_IOMUXC_GPIO_9_ALT4_PWM1_OUT = 4,
+ IMX_IOMUXC_GPIO_9_ALT5_GPIO1_IO09 = 5,
+ IMX_IOMUXC_GPIO_9_ALT6_SD1_WP = 6,
+} IMX_IOMUXC_GPIO_9_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_CLK_ALT0_SD2_CLK = 0,
+ IMX_IOMUXC_SD2_CLK_ALT1_ECSPI5_SCLK = 1,
+ IMX_IOMUXC_SD2_CLK_ALT2_KEY_COL5 = 2,
+ IMX_IOMUXC_SD2_CLK_ALT3_AUD4_RXFS = 3,
+ IMX_IOMUXC_SD2_CLK_ALT5_GPIO1_IO10 = 5,
+} IMX_IOMUXC_SD2_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_CMD_ALT0_SD2_CMD = 0,
+ IMX_IOMUXC_SD2_CMD_ALT1_ECSPI5_MOSI = 1,
+ IMX_IOMUXC_SD2_CMD_ALT2_KEY_ROW5 = 2,
+ IMX_IOMUXC_SD2_CMD_ALT3_AUD4_RXC = 3,
+ IMX_IOMUXC_SD2_CMD_ALT5_GPIO1_IO11 = 5,
+} IMX_IOMUXC_SD2_CMD_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_DAT3_ALT0_SD2_DATA3 = 0,
+ IMX_IOMUXC_SD2_DAT3_ALT1_ECSPI5_SS3 = 1,
+ IMX_IOMUXC_SD2_DAT3_ALT2_KEY_COL6 = 2,
+ IMX_IOMUXC_SD2_DAT3_ALT3_AUD4_TXC = 3,
+ IMX_IOMUXC_SD2_DAT3_ALT5_GPIO1_IO12 = 5,
+} IMX_IOMUXC_SD2_DAT3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_DAT2_ALT0_SD2_DATA2 = 0,
+ IMX_IOMUXC_SD2_DAT2_ALT1_ECSPI5_SS1 = 1,
+ IMX_IOMUXC_SD2_DAT2_ALT2_EIM_CS3_B = 2,
+ IMX_IOMUXC_SD2_DAT2_ALT3_AUD4_TXD = 3,
+ IMX_IOMUXC_SD2_DAT2_ALT4_KEY_ROW6 = 4,
+ IMX_IOMUXC_SD2_DAT2_ALT5_GPIO1_IO13 = 5,
+} IMX_IOMUXC_SD2_DAT2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_DAT1_ALT0_SD2_DATA1 = 0,
+ IMX_IOMUXC_SD2_DAT1_ALT1_ECSPI5_SS0 = 1,
+ IMX_IOMUXC_SD2_DAT1_ALT2_EIM_CS2_B = 2,
+ IMX_IOMUXC_SD2_DAT1_ALT3_AUD4_TXFS = 3,
+ IMX_IOMUXC_SD2_DAT1_ALT4_KEY_COL7 = 4,
+ IMX_IOMUXC_SD2_DAT1_ALT5_GPIO1_IO14 = 5,
+} IMX_IOMUXC_SD2_DAT1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_DAT0_ALT0_SD2_DATA0 = 0,
+ IMX_IOMUXC_SD2_DAT0_ALT1_ECSPI5_MISO = 1,
+ IMX_IOMUXC_SD2_DAT0_ALT3_AUD4_RXD = 3,
+ IMX_IOMUXC_SD2_DAT0_ALT4_KEY_ROW7 = 4,
+ IMX_IOMUXC_SD2_DAT0_ALT5_GPIO1_IO15 = 5,
+ IMX_IOMUXC_SD2_DAT0_ALT6_DCIC2_OUT = 6,
+} IMX_IOMUXC_SD2_DAT0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_DAT0_ALT0_SD1_DATA0 = 0,
+ IMX_IOMUXC_SD1_DAT0_ALT1_ECSPI5_MISO = 1,
+ IMX_IOMUXC_SD1_DAT0_ALT3_GPT_CAPTURE1 = 3,
+ IMX_IOMUXC_SD1_DAT0_ALT5_GPIO1_IO16 = 5,
+} IMX_IOMUXC_SD1_DAT0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_DAT1_ALT0_SD1_DATA1 = 0,
+ IMX_IOMUXC_SD1_DAT1_ALT1_ECSPI5_SS0 = 1,
+ IMX_IOMUXC_SD1_DAT1_ALT2_PWM3_OUT = 2,
+ IMX_IOMUXC_SD1_DAT1_ALT3_GPT_CAPTURE2 = 3,
+ IMX_IOMUXC_SD1_DAT1_ALT5_GPIO1_IO17 = 5,
+} IMX_IOMUXC_SD1_DAT1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_CMD_ALT0_SD1_CMD = 0, // in and out
+ IMX_IOMUXC_SD1_CMD_ALT1_ECSPI5_MOSI = 1,
+ IMX_IOMUXC_SD1_CMD_ALT2_PWM4_OUT = 2,
+ IMX_IOMUXC_SD1_CMD_ALT3_GPT_COMPARE1 = 3,
+ IMX_IOMUXC_SD1_CMD_ALT5_GPIO1_IO18 = 5,
+} IMX_IOMUXC_SD1_CMD_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_DAT2_ALT0_SD1_DATA2 = 0,
+ IMX_IOMUXC_SD1_DAT2_ALT1_ECSPI5_SS1 = 1,
+ IMX_IOMUXC_SD1_DAT2_ALT2_GPT_COMPARE2 = 2,
+ IMX_IOMUXC_SD1_DAT2_ALT3_PWM2_OUT = 3,
+ IMX_IOMUXC_SD1_DAT2_ALT4_WDOG1_B = 4,
+ IMX_IOMUXC_SD1_DAT2_ALT5_GPIO1_IO19 = 5,
+ IMX_IOMUXC_SD1_DAT2_ALT6_WDOG1_RESET_B_DEB = 6,
+} IMX_IOMUXC_SD1_DAT2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_CLK_ALT0_SD1_CLK = 0, // out
+ IMX_IOMUXC_SD1_CLK_ALT1_ECSPI5_SCLK = 1,
+ IMX_IOMUXC_SD1_CLK_ALT2_XTALOSC_OSC32K_32K_OUT = 2,
+ IMX_IOMUXC_SD1_CLK_ALT3_GPT_CLKIN = 3,
+ IMX_IOMUXC_SD1_CLK_ALT5_GPIO1_IO20 = 5,
+} IMX_IOMUXC_SD1_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_DAT3_ALT0_SD1_DATA3 = 0,
+ IMX_IOMUXC_SD1_DAT3_ALT1_ECSPI5_SS2 = 1,
+ IMX_IOMUXC_SD1_DAT3_ALT2_GPT_COMPARE3 = 2,
+ IMX_IOMUXC_SD1_DAT3_ALT3_PWM1_OUT = 3,
+ IMX_IOMUXC_SD1_DAT3_ALT4_WDOG2_B = 4,
+ IMX_IOMUXC_SD1_DAT3_ALT5_GPIO1_IO21 = 5,
+ IMX_IOMUXC_SD1_DAT3_ALT6_WDOG2_RESET_B_DEB = 6,
+} IMX_IOMUXC_SD1_DAT3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_MDIO_ALT1_ENET_MDIO = 1,
+ IMX_IOMUXC_ENET_MDIO_ALT2_ESAI_RX_CLK = 2,
+ IMX_IOMUXC_ENET_MDIO_ALT4_ENET_1588_EVENT1_OUT = 4,
+ IMX_IOMUXC_ENET_MDIO_ALT5_GPIO1_IO22 = 5,
+ IMX_IOMUXC_ENET_MDIO_ALT6_SPDIF_LOCK = 6,
+} IMX_IOMUXC_ENET_MDIO_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_REF_CLK_ALT1_ENET_TX_CLK = 1,
+ IMX_IOMUXC_ENET_REF_CLK_ALT2_ESAI_RX_FS = 2,
+ IMX_IOMUXC_ENET_REF_CLK_ALT5_GPIO1_IO23 = 5,
+ IMX_IOMUXC_ENET_REF_CLK_ALT6_SPDIF_SR_CLK = 6,
+} IMX_IOMUXC_ENET_REF_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_RX_ER_ALT0_USB_OTG_ID = 0,
+ IMX_IOMUXC_ENET_RX_ER_ALT1_ENET_RX_ER = 1,
+ IMX_IOMUXC_ENET_RX_ER_ALT2_ESAI_RX_HF_CLK = 2,
+ IMX_IOMUXC_ENET_RX_ER_ALT3_SPDIF_IN = 3,
+ IMX_IOMUXC_ENET_RX_ER_ALT4_ENET_1588_EVENT2_OUT = 4,
+ IMX_IOMUXC_ENET_RX_ER_ALT5_GPIO1_IO24 = 5,
+} IMX_IOMUXC_ENET_RX_ER_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_CRS_DV_ALT1_ENET_RX_EN = 1,
+ IMX_IOMUXC_ENET_CRS_DV_ALT2_ESAI_TX_CLK = 2,
+ IMX_IOMUXC_ENET_CRS_DV_ALT3_SPDIF_EXT_CLK = 3,
+ IMX_IOMUXC_ENET_CRS_DV_ALT5_GPIO1_IO25 = 5,
+} IMX_IOMUXC_ENET_CRS_DV_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_RXD1_ALT0_MLB_SIG = 0,
+ IMX_IOMUXC_ENET_RXD1_ALT1_ENET_RX_DATA1 = 1,
+ IMX_IOMUXC_ENET_RXD1_ALT2_ESAI_TX_FS = 2,
+ IMX_IOMUXC_ENET_RXD1_ALT4_ENET_1588_EVENT3_OUT = 4,
+ IMX_IOMUXC_ENET_RXD1_ALT5_GPIO1_IO26 = 5,
+} IMX_IOMUXC_ENET_RXD1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_RXD0_ALT0_XTALOSC_OSC32K_32K_OUT = 0,
+ IMX_IOMUXC_ENET_RXD0_ALT1_ENET_RX_DATA0 = 1,
+ IMX_IOMUXC_ENET_RXD0_ALT2_ESAI_TX_HF_CLK = 2,
+ IMX_IOMUXC_ENET_RXD0_ALT3_SPDIF_OUT = 3,
+ IMX_IOMUXC_ENET_RXD0_ALT5_GPIO1_IO27 = 5,
+} IMX_IOMUXC_ENET_RXD0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_TX_EN_ALT1_ENET_TX_EN = 1,
+ IMX_IOMUXC_ENET_TX_EN_ALT2_ESAI_TX3_RX2 = 2,
+ IMX_IOMUXC_ENET_TX_EN_ALT5_GPIO1_IO28 = 5,
+} IMX_IOMUXC_ENET_TX_EN_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_TXD1_ALT0_MLB_CLK = 0,
+ IMX_IOMUXC_ENET_TXD1_ALT1_ENET_TX_DATA1 = 1,
+ IMX_IOMUXC_ENET_TXD1_ALT2_ESAI_TX2_RX3 = 2,
+ IMX_IOMUXC_ENET_TXD1_ALT4_ENET_1588_EVENT0_IN = 4,
+ IMX_IOMUXC_ENET_TXD1_ALT5_GPIO1_IO29 = 5,
+} IMX_IOMUXC_ENET_TXD1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_TXD0_ALT1_ENET_TX_DATA0 = 1,
+ IMX_IOMUXC_ENET_TXD0_ALT2_ESAI_TX4_RX1 = 2,
+ IMX_IOMUXC_ENET_TXD0_ALT5_GPIO1_IO30 = 5,
+} IMX_IOMUXC_ENET_TXD0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET_MDC_ALT0_MLB_DATA = 0,
+ IMX_IOMUXC_ENET_MDC_ALT1_ENET_MDC = 1,
+ IMX_IOMUXC_ENET_MDC_ALT2_ESAI_TX5_RX0 = 2,
+ IMX_IOMUXC_ENET_MDC_ALT4_ENET_1588_EVENT1_IN = 4,
+ IMX_IOMUXC_ENET_MDC_ALT5_GPIO1_IO31 = 5,
+} IMX_IOMUXC_ENET_MDC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D0_ALT0_NAND_DATA00 = 0,
+ IMX_IOMUXC_NANDF_D0_ALT1_SD1_DATA4 = 1,
+ IMX_IOMUXC_NANDF_D0_ALT5_GPIO2_IO00 = 5,
+} IMX_IOMUXC_NANDF_D0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D1_ALT0_NAND_DATA01 = 0,
+ IMX_IOMUXC_NANDF_D1_ALT1_SD1_DATA5 = 1,
+ IMX_IOMUXC_NANDF_D1_ALT5_GPIO2_IO01 = 5,
+} IMX_IOMUXC_NANDF_D1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D2_ALT0_NAND_DATA02 = 0,
+ IMX_IOMUXC_NANDF_D2_ALT1_SD1_DATA6 = 1,
+ IMX_IOMUXC_NANDF_D2_ALT5_GPIO2_IO02 = 5,
+} IMX_IOMUXC_NANDF_D2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D3_ALT0_NAND_DATA03 = 0,
+ IMX_IOMUXC_NANDF_D3_ALT1_SD1_DATA7 = 1,
+ IMX_IOMUXC_NANDF_D3_ALT5_GPIO2_IO03 = 5,
+} IMX_IOMUXC_NANDF_D3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D4_ALT0_NAND_DATA04 = 0,
+ IMX_IOMUXC_NANDF_D4_ALT1_SD2_DATA4 = 1,
+ IMX_IOMUXC_NANDF_D4_ALT5_GPIO2_IO04 = 5,
+} IMX_IOMUXC_NANDF_D4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D5_ALT0_NAND_DATA05 = 0,
+ IMX_IOMUXC_NANDF_D5_ALT1_SD2_DATA5 = 1,
+ IMX_IOMUXC_NANDF_D5_ALT5_GPIO2_IO05 = 5,
+} IMX_IOMUXC_NANDF_D5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D6_ALT0_NAND_DATA06 = 0,
+ IMX_IOMUXC_NANDF_D6_ALT1_SD2_DATA6 = 1,
+ IMX_IOMUXC_NANDF_D6_ALT5_GPIO2_IO06 = 5,
+} IMX_IOMUXC_NANDF_D6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_D7_ALT0_NAND_DATA07 = 0,
+ IMX_IOMUXC_NANDF_D7_ALT1_SD2_DATA7 = 1,
+ IMX_IOMUXC_NANDF_D7_ALT5_GPIO2_IO07 = 5,
+} IMX_IOMUXC_NANDF_D7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT0_ALT1_SD4_DATA0 = 1,
+ IMX_IOMUXC_SD4_DAT0_ALT2_NAND_DQS = 2,
+ IMX_IOMUXC_SD4_DAT0_ALT5_GPIO2_IO08 = 5,
+} IMX_IOMUXC_SD4_DAT0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT1_ALT1_SD4_DATA1 = 1,
+ IMX_IOMUXC_SD4_DAT1_ALT2_PWM3_OUT = 2,
+ IMX_IOMUXC_SD4_DAT1_ALT5_GPIO2_IO09 = 5,
+} IMX_IOMUXC_SD4_DAT1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT2_ALT1_SD4_DATA2 = 1,
+ IMX_IOMUXC_SD4_DAT2_ALT2_PWM4_OUT = 2,
+ IMX_IOMUXC_SD4_DAT2_ALT5_GPIO2_IO10 = 5,
+} IMX_IOMUXC_SD4_DAT2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT3_ALT1_SD4_DATA3 = 1,
+ IMX_IOMUXC_SD4_DAT3_ALT5_GPIO2_IO11 = 5,
+} IMX_IOMUXC_SD4_DAT3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT4_ALT1_SD4_DATA4 = 1,
+ IMX_IOMUXC_SD4_DAT4_ALT2_UART2_RX_DATA = 2,
+ IMX_IOMUXC_SD4_DAT4_ALT5_GPIO2_IO12 = 5,
+} IMX_IOMUXC_SD4_DAT4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT5_ALT1_SD4_DATA5 = 1,
+ IMX_IOMUXC_SD4_DAT5_ALT2_UART2_RTS_B = 2,
+ IMX_IOMUXC_SD4_DAT5_ALT5_GPIO2_IO13 = 5,
+} IMX_IOMUXC_SD4_DAT5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT6_ALT1_SD4_DATA6 = 1,
+ IMX_IOMUXC_SD4_DAT6_ALT2_UART2_CTS_B = 2,
+ IMX_IOMUXC_SD4_DAT6_ALT5_GPIO2_IO14 = 5,
+} IMX_IOMUXC_SD4_DAT6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DAT7_ALT1_SD4_DATA7 = 1,
+ IMX_IOMUXC_SD4_DAT7_ALT2_UART2_TX_DATA = 2,
+ IMX_IOMUXC_SD4_DAT7_ALT5_GPIO2_IO15 = 5,
+} IMX_IOMUXC_SD4_DAT7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A22_ALT0_EIM_ADDR22 = 0,
+ IMX_IOMUXC_EIM_A22_ALT1_IPU1_DISP1_DATA17 = 1,
+ IMX_IOMUXC_EIM_A22_ALT2_IPU1_CSI1_DATA17 = 2,
+ IMX_IOMUXC_EIM_A22_ALT5_GPIO2_IO16 = 5,
+ IMX_IOMUXC_EIM_A22_ALT7_SRC_BOOT_CFG22 = 7,
+ IMX_IOMUXC_EIM_A22_ALT8_EPDC_GDSP = 8,
+} IMX_IOMUXC_EIM_A22_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A21_ALT0_EIM_ADDR21 = 0,
+ IMX_IOMUXC_EIM_A21_ALT1_IPU1_DISP1_DATA16 = 1,
+ IMX_IOMUXC_EIM_A21_ALT2_IPU1_CSI1_DATA16 = 2,
+ IMX_IOMUXC_EIM_A21_ALT5_GPIO2_IO17 = 5,
+ IMX_IOMUXC_EIM_A21_ALT7_SRC_BOOT_CFG21 = 7,
+ IMX_IOMUXC_EIM_A21_ALT8_EPDC_GDCLK = 8
+} IMX_IOMUXC_EIM_A21_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A20_ALT0_EIM_ADDR20 = 0,
+ IMX_IOMUXC_EIM_A20_ALT1_IPU1_DISP1_DATA15 = 1,
+ IMX_IOMUXC_EIM_A20_ALT2_IPU1_CSI1_DATA15 = 2,
+ IMX_IOMUXC_EIM_A20_ALT5_GPIO2_IO18 = 5,
+ IMX_IOMUXC_EIM_A20_ALT7_SRC_BOOT_CFG20 = 7,
+ IMX_IOMUXC_EIM_A20_ALT8_EPDC_PWR_CTRL2 = 8
+} IMX_IOMUXC_EIM_A20_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A19_ALT0_EIM_ADDR19 = 0,
+ IMX_IOMUXC_EIM_A19_ALT1_IPU1_DISP1_DATA14 = 1,
+ IMX_IOMUXC_EIM_A19_ALT2_IPU1_CSI1_DATA14 = 2,
+ IMX_IOMUXC_EIM_A19_ALT5_GPIO2_IO19 = 5,
+ IMX_IOMUXC_EIM_A19_ALT7_SRC_BOOT_CFG19 = 7,
+ IMX_IOMUXC_EIM_A19_ALT8_EPDC_PWR_CTRL1 = 8
+} IMX_IOMUXC_EIM_A19_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A18_ALT0_EIM_ADDR18 = 0,
+ IMX_IOMUXC_EIM_A18_ALT1_IPU1_DISP1_DATA13 = 1,
+ IMX_IOMUXC_EIM_A18_ALT2_IPU1_CSI1_DATA13 = 2,
+ IMX_IOMUXC_EIM_A18_ALT5_GPIO2_IO20 = 5,
+ IMX_IOMUXC_EIM_A18_ALT7_SRC_BOOT_CFG18 = 7,
+ IMX_IOMUXC_EIM_A18_ALT8_EPDC_PWR_CTRL0 = 8
+} IMX_IOMUXC_EIM_A18_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A17_ALT0_EIM_ADDR17 = 0,
+ IMX_IOMUXC_EIM_A17_ALT1_IPU1_DISP1_DATA12 = 1,
+ IMX_IOMUXC_EIM_A17_ALT2_IPU1_CSI1_DATA12 = 2,
+ IMX_IOMUXC_EIM_A17_ALT5_GPIO2_IO21 = 5,
+ IMX_IOMUXC_EIM_A17_ALT7_SRC_BOOT_CFG17 = 7,
+ IMX_IOMUXC_EIM_A17_ALT8_EPDC_PWR_STAT = 8
+} IMX_IOMUXC_EIM_A17_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A16_ALT0_EIM_ADDR16 = 0,
+ IMX_IOMUXC_EIM_A16_ALT1_IPU1_DI1_DISP_CLK = 1,
+ IMX_IOMUXC_EIM_A16_ALT2_IPU1_CSI1_PIXCLK = 2,
+ IMX_IOMUXC_EIM_A16_ALT5_GPIO2_IO22 = 5,
+ IMX_IOMUXC_EIM_A16_ALT7_SRC_BOOT_CFG16 = 7,
+ IMX_IOMUXC_EIM_A16_ALT8_EPDC_DATA00 = 8
+} IMX_IOMUXC_EIM_A16_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_CS0_ALT0_EIM_CS0_B = 0,
+ IMX_IOMUXC_EIM_CS0_ALT1_IPU1_DI1_PIN05 = 1,
+ IMX_IOMUXC_EIM_CS0_ALT2_ECSPI2_SCLK = 2,
+ IMX_IOMUXC_EIM_CS0_ALT5_GPIO2_IO23 = 5,
+} IMX_IOMUXC_EIM_CS0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_CS1_ALT0_EIM_CS1_B = 0,
+ IMX_IOMUXC_EIM_CS1_ALT1_IPU1_DI1_PIN06 = 1,
+ IMX_IOMUXC_EIM_CS1_ALT2_ECSPI2_MOSI = 2,
+ IMX_IOMUXC_EIM_CS1_ALT5_GPIO2_IO24 = 5,
+} IMX_IOMUXC_EIM_CS1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_OE_ALT0_EIM_OE_B = 0,
+ IMX_IOMUXC_EIM_OE_ALT1_IPU1_DI1_PIN07 = 1,
+ IMX_IOMUXC_EIM_OE_ALT2_ECSPI2_MISO = 2,
+ IMX_IOMUXC_EIM_OE_ALT5_GPIO2_IO25 = 5,
+} IMX_IOMUXC_EIM_OE_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_RW_ALT0_EIM_RW = 0,
+ IMX_IOMUXC_EIM_RW_ALT1_IPU1_DI1_PIN08 = 1,
+ IMX_IOMUXC_EIM_RW_ALT2_ECSPI2_SS0 = 2,
+ IMX_IOMUXC_EIM_RW_ALT5_GPIO2_IO26 = 5,
+ IMX_IOMUXC_EIM_RW_ALT7_SRC_BOOT_CFG29 = 7,
+} IMX_IOMUXC_EIM_RW_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_LBA_ALT0_EIM_LBA_B = 0,
+ IMX_IOMUXC_EIM_LBA_ALT1_IPU1_DI1_PIN17 = 1,
+ IMX_IOMUXC_EIM_LBA_ALT2_ECSPI2_SS1 = 2,
+ IMX_IOMUXC_EIM_LBA_ALT5_GPIO2_IO27 = 5,
+ IMX_IOMUXC_EIM_LBA_ALT7_SRC_BOOT_CFG26 = 7,
+} IMX_IOMUXC_EIM_LBA_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_EB0_ALT0_EIM_EB0_B = 0,
+ IMX_IOMUXC_EIM_EB0_ALT1_IPU1_DISP1_DATA11 = 1,
+ IMX_IOMUXC_EIM_EB0_ALT2_IPU1_CSI1_DATA11 = 2,
+ IMX_IOMUXC_EIM_EB0_ALT4_CCM_PMIC_READY = 4,
+ IMX_IOMUXC_EIM_EB0_ALT5_GPIO2_IO28 = 5,
+ IMX_IOMUXC_EIM_EB0_ALT7_SRC_BOOT_CFG27 = 7,
+ IMX_IOMUXC_EIM_EB0_ALT8_EPDC_PWR_COM = 8
+} IMX_IOMUXC_EIM_EB0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_EB1_ALT0_EIM_EB1_B = 0,
+ IMX_IOMUXC_EIM_EB1_ALT1_IPU1_DISP1_DATA10 = 1,
+ IMX_IOMUXC_EIM_EB1_ALT2_IPU1_CSI1_DATA10 = 2,
+ IMX_IOMUXC_EIM_EB1_ALT5_GPIO2_IO29 = 5,
+ IMX_IOMUXC_EIM_EB1_ALT7_SRC_BOOT_CFG28 = 7,
+ IMX_IOMUXC_EIM_EB1_ALT8_EPDC_SDSHR = 8
+} IMX_IOMUXC_EIM_EB1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_EB2_ALT0_EIM_EB2_B = 0,
+ IMX_IOMUXC_EIM_EB2_ALT1_ECSPI1_SS0 = 1,
+ IMX_IOMUXC_EIM_EB2_ALT3_IPU1_CSI1_DATA19 = 3,
+ IMX_IOMUXC_EIM_EB2_ALT4_HDMI_TX_DDC_SCL = 4,
+ IMX_IOMUXC_EIM_EB2_ALT5_GPIO2_IO30 = 5,
+ IMX_IOMUXC_EIM_EB2_ALT6_I2C2_SCL = 6,
+ IMX_IOMUXC_EIM_EB2_ALT7_SRC_BOOT_CFG30 = 7,
+ IMX_IOMUXC_EIM_EB2_ALT8_EPDC_DATA05 = 8
+} IMX_IOMUXC_EIM_EB2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_EB3_ALT0_EIM_EB3_B = 0,
+ IMX_IOMUXC_EIM_EB3_ALT1_ECSPI4_RDY = 1,
+ IMX_IOMUXC_EIM_EB3_ALT2_UART3_RTS_B = 2,
+ IMX_IOMUXC_EIM_EB3_ALT3_UART1_RI_B = 3,
+ IMX_IOMUXC_EIM_EB3_ALT4_IPU1_CSI1_HSYNC = 4,
+ IMX_IOMUXC_EIM_EB3_ALT5_GPIO2_IO31 = 5,
+ IMX_IOMUXC_EIM_EB3_ALT6_IPU1_DI1_PIN03 = 6,
+ IMX_IOMUXC_EIM_EB3_ALT7_SRC_BOOT_CFG31 = 7,
+ IMX_IOMUXC_EIM_EB3_ALT8_EPDC_SDCE0 = 8,
+ IMX_IOMUXC_EIM_EB3_ALT9_EIM_ACLK_FREERUN = 9
+} IMX_IOMUXC_EIM_EB3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA0_ALT0_EIM_AD00 = 0,
+ IMX_IOMUXC_EIM_DA0_ALT1_IPU1_DISP1_DATA09 = 1,
+ IMX_IOMUXC_EIM_DA0_ALT2_IPU1_CSI1_DATA09 = 2,
+ IMX_IOMUXC_EIM_DA0_ALT5_GPIO3_IO00 = 5,
+ IMX_IOMUXC_EIM_DA0_ALT7_SRC_BOOT_CFG00 = 7,
+ IMX_IOMUXC_EIM_DA0_ALT8_EPDC_SDCLK_N = 8
+} IMX_IOMUXC_EIM_DA0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA1_ALT0_EIM_AD01 = 0,
+ IMX_IOMUXC_EIM_DA1_ALT1_IPU1_DISP1_DATA08 = 1,
+ IMX_IOMUXC_EIM_DA1_ALT2_IPU1_CSI1_DATA08 = 2,
+ IMX_IOMUXC_EIM_DA1_ALT5_GPIO3_IO01 = 5,
+ IMX_IOMUXC_EIM_DA1_ALT7_SRC_BOOT_CFG01 = 7,
+ IMX_IOMUXC_EIM_DA1_ALT8_EPDC_SDLE = 8
+} IMX_IOMUXC_EIM_DA1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA2_ALT0_EIM_AD02 = 0,
+ IMX_IOMUXC_EIM_DA2_ALT1_IPU1_DISP1_DATA07 = 1,
+ IMX_IOMUXC_EIM_DA2_ALT2_IPU1_CSI1_DATA07 = 2,
+ IMX_IOMUXC_EIM_DA2_ALT5_GPIO3_IO02 = 5,
+ IMX_IOMUXC_EIM_DA2_ALT7_SRC_BOOT_CFG02 = 7,
+ IMX_IOMUXC_EIM_DA2_ALT8_EPDC_BDR02 = 8
+} IMX_IOMUXC_EIM_DA2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA3_ALT0_EIM_AD03 = 0,
+ IMX_IOMUXC_EIM_DA3_ALT1_IPU1_DISP1_DATA06 = 1,
+ IMX_IOMUXC_EIM_DA3_ALT2_IPU1_CSI1_DATA06 = 2,
+ IMX_IOMUXC_EIM_DA3_ALT5_GPIO3_IO03 = 5,
+ IMX_IOMUXC_EIM_DA3_ALT7_SRC_BOOT_CFG03 = 7,
+ IMX_IOMUXC_EIM_DA3_ALT8_EPDC_BDR1 = 8
+} IMX_IOMUXC_EIM_DA3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA4_ALT0_EIM_AD04 = 0,
+ IMX_IOMUXC_EIM_DA4_ALT1_IPU1_DISP1_DATA05 = 1,
+ IMX_IOMUXC_EIM_DA4_ALT2_IPU1_CSI1_DATA05 = 2,
+ IMX_IOMUXC_EIM_DA4_ALT5_GPIO3_IO04 = 5,
+ IMX_IOMUXC_EIM_DA4_ALT7_SRC_BOOT_CFG04 = 7,
+ IMX_IOMUXC_EIM_DA4_ALT8_EPDC_SDCE0 = 8
+} IMX_IOMUXC_EIM_DA4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA5_ALT0_EIM_AD05 = 0,
+ IMX_IOMUXC_EIM_DA5_ALT1_IPU1_DISP1_DATA04 = 1,
+ IMX_IOMUXC_EIM_DA5_ALT2_IPU1_CSI1_DATA04 = 2,
+ IMX_IOMUXC_EIM_DA5_ALT5_GPIO3_IO05 = 5,
+ IMX_IOMUXC_EIM_DA5_ALT7_SRC_BOOT_CFG05 = 7,
+ IMX_IOMUXC_EIM_DA5_ALT8_EPDC_SDCE1 = 8
+} IMX_IOMUXC_EIM_DA5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA6_ALT0_EIM_AD06 = 0,
+ IMX_IOMUXC_EIM_DA6_ALT1_IPU1_DISP1_DATA03 = 1,
+ IMX_IOMUXC_EIM_DA6_ALT2_IPU1_CSI1_DATA03 = 2,
+ IMX_IOMUXC_EIM_DA6_ALT5_GPIO3_IO06 = 5,
+ IMX_IOMUXC_EIM_DA6_ALT7_SRC_BOOT_CFG06 = 7,
+ IMX_IOMUXC_EIM_DA6_ALT8_EPDC_SDCE2 = 8
+} IMX_IOMUXC_EIM_DA6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA7_ALT0_EIM_AD07 = 0,
+ IMX_IOMUXC_EIM_DA7_ALT1_IPU1_DISP1_DATA02 = 1,
+ IMX_IOMUXC_EIM_DA7_ALT2_IPU1_CSI1_DATA02 = 2,
+ IMX_IOMUXC_EIM_DA7_ALT5_GPIO3_IO07 = 5,
+ IMX_IOMUXC_EIM_DA7_ALT7_SRC_BOOT_CFG07 = 7,
+ IMX_IOMUXC_EIM_DA7_ALT8_EPDC_SDCE37 = 8
+} IMX_IOMUXC_EIM_DA7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA8_ALT0_EIM_AD08 = 0,
+ IMX_IOMUXC_EIM_DA8_ALT1_IPU1_DISP1_DATA01 = 1,
+ IMX_IOMUXC_EIM_DA8_ALT2_IPU1_CSI1_DATA01 = 2,
+ IMX_IOMUXC_EIM_DA8_ALT5_GPIO3_IO08 = 5,
+ IMX_IOMUXC_EIM_DA8_ALT7_SRC_BOOT_CFG08 = 7,
+ IMX_IOMUXC_EIM_DA8_ALT8_EPDC_SDCE4 = 8
+} IMX_IOMUXC_EIM_DA8_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA9_ALT0_EIM_AD09 = 0,
+ IMX_IOMUXC_EIM_DA9_ALT1_IPU1_DISP1_DATA00 = 1,
+ IMX_IOMUXC_EIM_DA9_ALT2_IPU1_CSI1_DATA00 = 2,
+ IMX_IOMUXC_EIM_DA9_ALT5_GPIO3_IO09 = 5,
+ IMX_IOMUXC_EIM_DA9_ALT7_SRC_BOOT_CFG09 = 7,
+ IMX_IOMUXC_EIM_DA9_ALT8_EPDC_SDCE5 = 8
+} IMX_IOMUXC_EIM_DA9_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA10_ALT0_EIM_AD10 = 0,
+ IMX_IOMUXC_EIM_DA10_ALT1_IPU1_DI1_PIN15 = 1,
+ IMX_IOMUXC_EIM_DA10_ALT2_IPU1_CSI1_DATA_EN = 2,
+ IMX_IOMUXC_EIM_DA10_ALT5_GPIO3_IO10 = 5,
+ IMX_IOMUXC_EIM_DA10_ALT7_SRC_BOOT_CFG10 = 7,
+ IMX_IOMUXC_EIM_DA10_ALT8_EPDC_DATA01 = 8
+} IMX_IOMUXC_EIM_DA10_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA11_ALT0_EIM_AD11 = 0,
+ IMX_IOMUXC_EIM_DA11_ALT1_IPU1_DI1_PIN02 = 1,
+ IMX_IOMUXC_EIM_DA11_ALT2_IPU1_CSI1_HSYNC = 2,
+ IMX_IOMUXC_EIM_DA11_ALT5_GPIO3_IO11 = 5,
+ IMX_IOMUXC_EIM_DA11_ALT7_SRC_BOOT_CFG11 = 7,
+ IMX_IOMUXC_EIM_DA11_ALT8_EPDC_DATA03 = 8
+} IMX_IOMUXC_EIM_DA11_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA12_ALT0_EIM_AD12 = 0,
+ IMX_IOMUXC_EIM_DA12_ALT1_IPU1_DI1_PIN03 = 1,
+ IMX_IOMUXC_EIM_DA12_ALT2_IPU1_CSI1_VSYNC = 2,
+ IMX_IOMUXC_EIM_DA12_ALT5_GPIO3_IO12 = 5,
+ IMX_IOMUXC_EIM_DA12_ALT7_SRC_BOOT_CFG12 = 7,
+ IMX_IOMUXC_EIM_DA12_ALT8_EPDC_DATA02 = 8
+} IMX_IOMUXC_EIM_DA12_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA13_ALT0_EIM_AD13 = 0,
+ IMX_IOMUXC_EIM_DA13_ALT1_IPU1_DI1_D0_CS = 1,
+ IMX_IOMUXC_EIM_DA13_ALT5_GPIO3_IO13 = 5,
+ IMX_IOMUXC_EIM_DA13_ALT7_SRC_BOOT_CFG13 = 7,
+} IMX_IOMUXC_EIM_DA13_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA14_ALT0_EIM_AD14 = 0,
+ IMX_IOMUXC_EIM_DA14_ALT1_IPU1_DI1_D1_CS = 1,
+ IMX_IOMUXC_EIM_DA14_ALT5_GPIO3_IO14 = 5,
+ IMX_IOMUXC_EIM_DA14_ALT7_SRC_BOOT_CFG14 = 7,
+} IMX_IOMUXC_EIM_DA14_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_DA15_ALT0_EIM_AD15 = 0,
+ IMX_IOMUXC_EIM_DA15_ALT1_IPU1_DI1_PIN01 = 1,
+ IMX_IOMUXC_EIM_DA15_ALT2_IPU1_DI1_PIN04 = 2,
+ IMX_IOMUXC_EIM_DA15_ALT5_GPIO3_IO15 = 5,
+ IMX_IOMUXC_EIM_DA15_ALT7_SRC_BOOT_CFG15 = 7,
+} IMX_IOMUXC_EIM_DA15_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D16_ALT0_EIM_DATA16 = 0,
+ IMX_IOMUXC_EIM_D16_ALT1_ECSPI1_SCLK = 1,
+ IMX_IOMUXC_EIM_D16_ALT2_IPU1_DI0_PIN05 = 2,
+ IMX_IOMUXC_EIM_D16_ALT3_IPU1_CSI1_DATA18 = 3,
+ IMX_IOMUXC_EIM_D16_ALT4_HDMI_TX_DDC_SDA = 4,
+ IMX_IOMUXC_EIM_D16_ALT5_GPIO3_IO16 = 5,
+ IMX_IOMUXC_EIM_D16_ALT6_I2C2_SDA = 6,
+ IMX_IOMUXC_EIM_D16_ALT8_EPDC_DATA10 = 8
+} IMX_IOMUXC_EIM_D16_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D17_ALT0_EIM_DATA17 = 0,
+ IMX_IOMUXC_EIM_D17_ALT1_ECSPI1_MISO = 1,
+ IMX_IOMUXC_EIM_D17_ALT2_IPU1_DI0_PIN06 = 2,
+ IMX_IOMUXC_EIM_D17_ALT3_IPU1_CSI1_PIXCLK = 3,
+ IMX_IOMUXC_EIM_D17_ALT4_DCIC1_OUT = 4,
+ IMX_IOMUXC_EIM_D17_ALT5_GPIO3_IO17 = 5,
+ IMX_IOMUXC_EIM_D17_ALT6_I2C3_SCL = 6,
+ IMX_IOMUXC_EIM_D17_ALT8_EPDC_VCOM0 = 8
+} IMX_IOMUXC_EIM_D17_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D18_ALT0_EIM_DATA18 = 0,
+ IMX_IOMUXC_EIM_D18_ALT1_ECSPI1_MOSI = 1,
+ IMX_IOMUXC_EIM_D18_ALT2_IPU1_DI0_PIN07 = 2,
+ IMX_IOMUXC_EIM_D18_ALT3_IPU1_CSI1_DATA17 = 3,
+ IMX_IOMUXC_EIM_D18_ALT4_IPU1_DI1_D0_CS = 4,
+ IMX_IOMUXC_EIM_D18_ALT5_GPIO3_IO18 = 5,
+ IMX_IOMUXC_EIM_D18_ALT6_I2C3_SDA = 6,
+ IMX_IOMUXC_EIM_D18_ALT8_EPDC_VCOM1 = 8
+} IMX_IOMUXC_EIM_D18_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D19_ALT0_EIM_DATA19 = 0,
+ IMX_IOMUXC_EIM_D19_ALT1_ECSPI1_SS1 = 1,
+ IMX_IOMUXC_EIM_D19_ALT2_IPU1_DI0_PIN08 = 2,
+ IMX_IOMUXC_EIM_D19_ALT3_IPU1_CSI1_DATA16 = 3,
+ IMX_IOMUXC_EIM_D19_ALT4_UART1_CTS_B = 4,
+ IMX_IOMUXC_EIM_D19_ALT5_GPIO3_IO19 = 5,
+ IMX_IOMUXC_EIM_D19_ALT6_EPIT1_OUT = 6,
+ IMX_IOMUXC_EIM_D19_ALT8_EPDC_DATA12 = 8
+} IMX_IOMUXC_EIM_D19_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D20_ALT0_EIM_DATA20 = 0,
+ IMX_IOMUXC_EIM_D20_ALT1_ECSPI4_SS0 = 1,
+ IMX_IOMUXC_EIM_D20_ALT2_IPU1_DI0_PIN16 = 2,
+ IMX_IOMUXC_EIM_D20_ALT3_IPU1_CSI1_DATA15 = 3,
+ IMX_IOMUXC_EIM_D20_ALT4_UART1_RTS_B = 4,
+ IMX_IOMUXC_EIM_D20_ALT5_GPIO3_IO20 = 5,
+ IMX_IOMUXC_EIM_D20_ALT6_EPIT2_OUT = 6
+} IMX_IOMUXC_EIM_D20_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D21_ALT0_EIM_DATA21 = 0,
+ IMX_IOMUXC_EIM_D21_ALT1_ECSPI4_SCLK = 1,
+ IMX_IOMUXC_EIM_D21_ALT2_IPU1_DI0_PIN17 = 2,
+ IMX_IOMUXC_EIM_D21_ALT3_IPU1_CSI1_DATA11 = 3,
+ IMX_IOMUXC_EIM_D21_ALT4_USB_OTG_OC = 4,
+ IMX_IOMUXC_EIM_D21_ALT5_GPIO3_IO21 = 5,
+ IMX_IOMUXC_EIM_D21_ALT6_I2C1_SCL = 6,
+ IMX_IOMUXC_EIM_D21_ALT7_SPDIF_IN = 7,
+} IMX_IOMUXC_EIM_D21_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D22_ALT0_EIM_DATA22 = 0,
+ IMX_IOMUXC_EIM_D22_ALT1_ECSPI4_MISO = 1,
+ IMX_IOMUXC_EIM_D22_ALT2_IPU1_DI0_PIN01 = 2,
+ IMX_IOMUXC_EIM_D22_ALT3_IPU1_CSI1_DATA10 = 3,
+ IMX_IOMUXC_EIM_D22_ALT4_USB_OTG_PWR = 4,
+ IMX_IOMUXC_EIM_D22_ALT5_GPIO3_IO22 = 5,
+ IMX_IOMUXC_EIM_D22_ALT6_SPDIF_OUT = 6,
+ IMX_IOMUXC_EIM_D22_ALT8_EPDC_SDCE6 = 8
+} IMX_IOMUXC_EIM_D22_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D23_ALT0_EIM_DATA23 = 0,
+ IMX_IOMUXC_EIM_D23_ALT1_IPU1_DI0_D0_CS = 1,
+ IMX_IOMUXC_EIM_D23_ALT2_UART3_CTS_B = 2,
+ IMX_IOMUXC_EIM_D23_ALT3_UART1_DCD_B = 3,
+ IMX_IOMUXC_EIM_D23_ALT4_IPU1_CSI1_DATA_EN = 4,
+ IMX_IOMUXC_EIM_D23_ALT5_GPIO3_IO23 = 5,
+ IMX_IOMUXC_EIM_D23_ALT6_IPU1_DI1_PIN02 = 6,
+ IMX_IOMUXC_EIM_D23_ALT7_IPU1_DI1_PIN14 = 7,
+ IMX_IOMUXC_EIM_D23_ALT8_EPDC_DATA11 = 8
+} IMX_IOMUXC_EIM_D23_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D24_ALT0_EIM_DATA24 = 0,
+ IMX_IOMUXC_EIM_D24_ALT1_ECSPI4_SS2 = 1,
+ IMX_IOMUXC_EIM_D24_ALT2_UART3_TX_DATA = 2,
+ IMX_IOMUXC_EIM_D24_ALT3_ECSPI1_SS2 = 3,
+ IMX_IOMUXC_EIM_D24_ALT4_ECSPI2_SS2 = 4,
+ IMX_IOMUXC_EIM_D24_ALT5_GPIO3_IO24 = 5,
+ IMX_IOMUXC_EIM_D24_ALT6_AUD5_RXFS = 6,
+ IMX_IOMUXC_EIM_D24_ALT7_UART1_DTR_B = 7,
+} IMX_IOMUXC_EIM_D24_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D25_ALT0_EIM_DATA25 = 0,
+ IMX_IOMUXC_EIM_D25_ALT1_ECSPI4_SS3 = 1,
+ IMX_IOMUXC_EIM_D25_ALT2_UART3_RX_DATA = 2,
+ IMX_IOMUXC_EIM_D25_ALT3_ECSPI1_SS3 = 3,
+ IMX_IOMUXC_EIM_D25_ALT4_ECSPI2_SS3 = 4,
+ IMX_IOMUXC_EIM_D25_ALT5_GPIO3_IO25 = 5,
+ IMX_IOMUXC_EIM_D25_ALT6_AUD5_RXC = 6,
+ IMX_IOMUXC_EIM_D25_ALT7_UART1_DSR_B = 7,
+} IMX_IOMUXC_EIM_D25_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D26_ALT0_EIM_DATA26 = 0,
+ IMX_IOMUXC_EIM_D26_ALT1_IPU1_DI1_PIN11 = 1,
+ IMX_IOMUXC_EIM_D26_ALT2_IPU1_CSI0_DATA01 = 2,
+ IMX_IOMUXC_EIM_D26_ALT3_IPU1_CSI1_DATA14 = 3,
+ IMX_IOMUXC_EIM_D26_ALT4_UART2_TX_DATA = 4,
+ IMX_IOMUXC_EIM_D26_ALT5_GPIO3_IO26 = 5,
+ IMX_IOMUXC_EIM_D26_ALT6_IPU1_SISG2 = 6,
+ IMX_IOMUXC_EIM_D26_ALT7_IPU1_DISP1_DATA22 = 7,
+ IMX_IOMUXC_EIM_D26_ALT8_EPDC_SDOE = 8
+} IMX_IOMUXC_EIM_D26_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D27_ALT0_EIM_DATA27 = 0,
+ IMX_IOMUXC_EIM_D27_ALT1_IPU1_DI1_PIN13 = 1,
+ IMX_IOMUXC_EIM_D27_ALT2_IPU1_CSI0_DATA00 = 2,
+ IMX_IOMUXC_EIM_D27_ALT3_IPU1_CSI1_DATA13 = 3,
+ IMX_IOMUXC_EIM_D27_ALT4_UART2_RX_DATA = 4,
+ IMX_IOMUXC_EIM_D27_ALT5_GPIO3_IO27 = 5,
+ IMX_IOMUXC_EIM_D27_ALT6_IPU1_SISG3 = 6,
+ IMX_IOMUXC_EIM_D27_ALT7_IPU1_DISP1_DATA23 = 7,
+ IMX_IOMUXC_EIM_D27_ALT8_EPDC_SDOE = 8
+} IMX_IOMUXC_EIM_D27_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D28_ALT0_EIM_DATA28 = 0,
+ IMX_IOMUXC_EIM_D28_ALT1_I2C1_SDA = 1,
+ IMX_IOMUXC_EIM_D28_ALT2_ECSPI4_MOSI = 2,
+ IMX_IOMUXC_EIM_D28_ALT3_IPU1_CSI1_DATA12 = 3,
+ IMX_IOMUXC_EIM_D28_ALT4_UART2_CTS_B = 4,
+ IMX_IOMUXC_EIM_D28_ALT5_GPIO3_IO28 = 5,
+ IMX_IOMUXC_EIM_D28_ALT6_IPU1_EXT_TRIG = 6,
+ IMX_IOMUXC_EIM_D28_ALT7_IPU1_DI0_PIN13 = 7,
+ IMX_IOMUXC_EIM_D28_ALT8_EPDC_PWR_CTRL3 = 8
+} IMX_IOMUXC_EIM_D28_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D29_ALT0_EIM_DATA29 = 0,
+ IMX_IOMUXC_EIM_D29_ALT1_IPU1_DI1_PIN15 = 1,
+ IMX_IOMUXC_EIM_D29_ALT2_ECSPI4_SS0 = 2,
+ IMX_IOMUXC_EIM_D29_ALT4_UART2_RTS_B = 4,
+ IMX_IOMUXC_EIM_D29_ALT5_GPIO3_IO29 = 5,
+ IMX_IOMUXC_EIM_D29_ALT6_IPU1_CSI1_VSYNC = 6,
+ IMX_IOMUXC_EIM_D29_ALT7_IPU1_DI0_PIN14 = 7,
+ IMX_IOMUXC_EIM_D29_ALT8_EPDC_PWR_WAKE = 8
+} IMX_IOMUXC_EIM_D29_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D30_ALT0_EIM_DATA30 = 0,
+ IMX_IOMUXC_EIM_D30_ALT1_IPU1_DISP1_DATA21 = 1,
+ IMX_IOMUXC_EIM_D30_ALT2_IPU1_DI0_PIN11 = 2,
+ IMX_IOMUXC_EIM_D30_ALT3_IPU1_CSI0_DATA03 = 3,
+ IMX_IOMUXC_EIM_D30_ALT4_UART3_CTS_B = 4,
+ IMX_IOMUXC_EIM_D30_ALT5_GPIO3_IO30 = 5,
+ IMX_IOMUXC_EIM_D30_ALT6_USB_H1_OC = 6,
+} IMX_IOMUXC_EIM_D30_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_D31_ALT0_EIM_DATA31 = 0,
+ IMX_IOMUXC_EIM_D31_ALT1_IPU1_DISP1_DATA20 = 1,
+ IMX_IOMUXC_EIM_D31_ALT2_IPU1_DI0_PIN12 = 2,
+ IMX_IOMUXC_EIM_D31_ALT3_IPU1_CSI0_DATA02 = 3,
+ IMX_IOMUXC_EIM_D31_ALT4_UART3_RTS_B = 4,
+ IMX_IOMUXC_EIM_D31_ALT5_GPIO3_IO31 = 5,
+ IMX_IOMUXC_EIM_D31_ALT6_USB_H1_PWR = 6,
+} IMX_IOMUXC_EIM_D31_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_19_ALT0_KEY_COL5 = 0,
+ IMX_IOMUXC_GPIO_19_ALT1_ENET_1588_EVENT0_OUT = 1,
+ IMX_IOMUXC_GPIO_19_ALT2_SPDIF_OUT = 2,
+ IMX_IOMUXC_GPIO_19_ALT3_CCM_CLKO1 = 3,
+ IMX_IOMUXC_GPIO_19_ALT4_ECSPI1_RDY = 4,
+ IMX_IOMUXC_GPIO_19_ALT5_GPIO4_IO05 = 5,
+ IMX_IOMUXC_GPIO_19_ALT6_ENET_TX_ER = 6,
+} IMX_IOMUXC_GPIO_19_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_COL0_ALT0_ECSPI1_SCLK = 0,
+ IMX_IOMUXC_KEY_COL0_ALT1_ENET_RX_DATA3 = 1,
+ IMX_IOMUXC_KEY_COL0_ALT2_AUD5_TXC = 2,
+ IMX_IOMUXC_KEY_COL0_ALT3_KEY_COL0 = 3,
+ IMX_IOMUXC_KEY_COL0_ALT4_UART4_TX_DATA = 4,
+ IMX_IOMUXC_KEY_COL0_ALT5_GPIO4_IO06 = 5,
+ IMX_IOMUXC_KEY_COL0_ALT6_DCIC1_OUT = 6,
+} IMX_IOMUXC_KEY_COL0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_ROW0_ALT0_ECSPI1_MOSI = 0,
+ IMX_IOMUXC_KEY_ROW0_ALT1_ENET_TX_DATA3 = 1,
+ IMX_IOMUXC_KEY_ROW0_ALT2_AUD5_TXD = 2,
+ IMX_IOMUXC_KEY_ROW0_ALT3_KEY_ROW0 = 3,
+ IMX_IOMUXC_KEY_ROW0_ALT4_UART4_RX_DATA = 4,
+ IMX_IOMUXC_KEY_ROW0_ALT5_GPIO4_IO07 = 5,
+ IMX_IOMUXC_KEY_ROW0_ALT6_DCIC2_OUT = 6,
+} IMX_IOMUXC_KEY_ROW0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_COL1_ALT0_ECSPI1_MISO = 0,
+ IMX_IOMUXC_KEY_COL1_ALT1_ENET_MDIO = 1,
+ IMX_IOMUXC_KEY_COL1_ALT2_AUD5_TXFS = 2,
+ IMX_IOMUXC_KEY_COL1_ALT3_KEY_COL1 = 3,
+ IMX_IOMUXC_KEY_COL1_ALT4_UART5_TX_DATA = 4,
+ IMX_IOMUXC_KEY_COL1_ALT5_GPIO4_IO08 = 5,
+ IMX_IOMUXC_KEY_COL1_ALT6_SD1_VSELECT = 6, // out
+} IMX_IOMUXC_KEY_COL1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_ROW1_ALT0_ECSPI1_SS0 = 0,
+ IMX_IOMUXC_KEY_ROW1_ALT1_ENET_COL = 1,
+ IMX_IOMUXC_KEY_ROW1_ALT2_AUD5_RXD = 2,
+ IMX_IOMUXC_KEY_ROW1_ALT3_KEY_ROW1 = 3,
+ IMX_IOMUXC_KEY_ROW1_ALT4_UART5_RX_DATA = 4,
+ IMX_IOMUXC_KEY_ROW1_ALT5_GPIO4_IO09 = 5,
+ IMX_IOMUXC_KEY_ROW1_ALT6_SD2_VSELECT = 6,
+} IMX_IOMUXC_KEY_ROW1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_COL2_ALT0_ECSPI1_SS1 = 0,
+ IMX_IOMUXC_KEY_COL2_ALT1_ENET_RX_DATA2 = 1,
+ IMX_IOMUXC_KEY_COL2_ALT2_FLEXCAN1_TX = 2,
+ IMX_IOMUXC_KEY_COL2_ALT3_KEY_COL2 = 3,
+ IMX_IOMUXC_KEY_COL2_ALT4_ENET_MDC = 4,
+ IMX_IOMUXC_KEY_COL2_ALT5_GPIO4_IO10 = 5,
+ IMX_IOMUXC_KEY_COL2_ALT6_USB_H1_PWR_CTL_WAKE = 6,
+} IMX_IOMUXC_KEY_COL2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_ROW2_ALT0_ECSPI1_SS2 = 0,
+ IMX_IOMUXC_KEY_ROW2_ALT1_ENET_TX_DATA2 = 1,
+ IMX_IOMUXC_KEY_ROW2_ALT2_FLEXCAN1_RX = 2,
+ IMX_IOMUXC_KEY_ROW2_ALT3_KEY_ROW2 = 3,
+ IMX_IOMUXC_KEY_ROW2_ALT4_SD2_VSELECT = 4,
+ IMX_IOMUXC_KEY_ROW2_ALT5_GPIO4_IO11 = 5,
+ IMX_IOMUXC_KEY_ROW2_ALT6_HDMI_TX_CEC_LINE = 6,
+} IMX_IOMUXC_KEY_ROW2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_COL3_ALT0_ECSPI1_SS3 = 0,
+ IMX_IOMUXC_KEY_COL3_ALT1_ENET_CRS = 1,
+ IMX_IOMUXC_KEY_COL3_ALT2_HDMI_TX_DDC_SCL = 2,
+ IMX_IOMUXC_KEY_COL3_ALT3_KEY_COL3 = 3,
+ IMX_IOMUXC_KEY_COL3_ALT4_I2C2_SCL = 4,
+ IMX_IOMUXC_KEY_COL3_ALT5_GPIO4_IO12 = 5,
+ IMX_IOMUXC_KEY_COL3_ALT6_SPDIF_IN = 6,
+} IMX_IOMUXC_KEY_COL3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_ROW3_ALT0_XTALOSC_OSC32K_32K_OUT = 0,
+ IMX_IOMUXC_KEY_ROW3_ALT1_ASRC_EXT_CLK = 1,
+ IMX_IOMUXC_KEY_ROW3_ALT2_HDMI_TX_DDC_SDA = 2,
+ IMX_IOMUXC_KEY_ROW3_ALT3_KEY_ROW3 = 3,
+ IMX_IOMUXC_KEY_ROW3_ALT4_I2C2_SDA = 4,
+ IMX_IOMUXC_KEY_ROW3_ALT5_GPIO4_IO13 = 5,
+ IMX_IOMUXC_KEY_ROW3_ALT6_SD1_VSELECT = 6,
+} IMX_IOMUXC_KEY_ROW3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_COL4_ALT0_FLEXCAN2_TX = 0,
+ IMX_IOMUXC_KEY_COL4_ALT1_IPU1_SISG4 = 1,
+ IMX_IOMUXC_KEY_COL4_ALT2_USB_OTG_OC = 2,
+ IMX_IOMUXC_KEY_COL4_ALT3_KEY_COL4 = 3,
+ IMX_IOMUXC_KEY_COL4_ALT4_UART5_RTS_B = 4,
+ IMX_IOMUXC_KEY_COL4_ALT5_GPIO4_IO14 = 5,
+} IMX_IOMUXC_KEY_COL4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_ROW4_ALT0_FLEXCAN2_RX = 0,
+ IMX_IOMUXC_KEY_ROW4_ALT1_IPU1_SISG5 = 1,
+ IMX_IOMUXC_KEY_ROW4_ALT2_USB_OTG_PWR = 2,
+ IMX_IOMUXC_KEY_ROW4_ALT3_KEY_ROW4 = 3,
+ IMX_IOMUXC_KEY_ROW4_ALT4_UART5_CTS_B = 4,
+ IMX_IOMUXC_KEY_ROW4_ALT5_GPIO4_IO15 = 5,
+} IMX_IOMUXC_KEY_ROW4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DI0_DISP_CLK_ALT0_IPU1_DI0_DISP_CLK = 0,
+ IMX_IOMUXC_DI0_DISP_CLK_ALT5_GPIO4_IO16 = 5,
+} IMX_IOMUXC_DI0_DISP_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DI0_PIN15_ALT0_IPU1_DI0_PIN15 = 0,
+ IMX_IOMUXC_DI0_PIN15_ALT2_AUD6_TXC = 2,
+ IMX_IOMUXC_DI0_PIN15_ALT5_GPIO4_IO17 = 5,
+} IMX_IOMUXC_DI0_PIN15_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DI0_PIN2_ALT0_IPU1_DI0_PIN02 = 0,
+ IMX_IOMUXC_DI0_PIN2_ALT2_AUD6_TXD = 2,
+ IMX_IOMUXC_DI0_PIN2_ALT5_GPIO4_IO18 = 5,
+} IMX_IOMUXC_DI0_PIN2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DI0_PIN3_ALT0_IPU1_DI0_PIN03 = 0,
+ IMX_IOMUXC_DI0_PIN3_ALT2_AUD6_TXFS = 2,
+ IMX_IOMUXC_DI0_PIN3_ALT5_GPIO4_IO19 = 5,
+} IMX_IOMUXC_DI0_PIN3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DI0_PIN4_ALT0_IPU1_DI0_PIN04 = 0,
+ IMX_IOMUXC_DI0_PIN4_ALT2_AUD6_RXD = 2,
+ IMX_IOMUXC_DI0_PIN4_ALT3_SD1_WP = 3, // in
+ IMX_IOMUXC_DI0_PIN4_ALT5_GPIO4_IO20 = 5,
+} IMX_IOMUXC_DI0_PIN4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT0_ALT0_IPU1_DISP0_DATA00 = 0,
+ IMX_IOMUXC_DISP0_DAT0_ALT2_ECSPI3_SCLK = 2,
+ IMX_IOMUXC_DISP0_DAT0_ALT5_GPIO4_IO21 = 5,
+} IMX_IOMUXC_DISP0_DAT0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT1_ALT0_IPU1_DISP0_DATA01 = 0,
+ IMX_IOMUXC_DISP0_DAT1_ALT2_ECSPI3_MOSI = 2,
+ IMX_IOMUXC_DISP0_DAT1_ALT5_GPIO4_IO22 = 5,
+} IMX_IOMUXC_DISP0_DAT1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT2_ALT0_IPU1_DISP0_DATA02 = 0,
+ IMX_IOMUXC_DISP0_DAT2_ALT2_ECSPI3_MISO = 2,
+ IMX_IOMUXC_DISP0_DAT2_ALT5_GPIO4_IO23 = 5,
+} IMX_IOMUXC_DISP0_DAT2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT3_ALT0_IPU1_DISP0_DATA03 = 0,
+ IMX_IOMUXC_DISP0_DAT3_ALT2_ECSPI3_SS0 = 2,
+ IMX_IOMUXC_DISP0_DAT3_ALT5_GPIO4_IO24 = 5,
+} IMX_IOMUXC_DISP0_DAT3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT4_ALT0_IPU1_DISP0_DATA04 = 0,
+ IMX_IOMUXC_DISP0_DAT4_ALT2_ECSPI3_SS1 = 2,
+ IMX_IOMUXC_DISP0_DAT4_ALT5_GPIO4_IO25 = 5,
+} IMX_IOMUXC_DISP0_DAT4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT5_ALT0_IPU1_DISP0_DATA05 = 0,
+ IMX_IOMUXC_DISP0_DAT5_ALT2_ECSPI3_SS2 = 2,
+ IMX_IOMUXC_DISP0_DAT5_ALT3_AUD6_RXFS = 3,
+ IMX_IOMUXC_DISP0_DAT5_ALT5_GPIO4_IO26 = 5,
+} IMX_IOMUXC_DISP0_DAT5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT6_ALT0_IPU1_DISP0_DATA06 = 0,
+ IMX_IOMUXC_DISP0_DAT6_ALT2_ECSPI3_SS3 = 2,
+ IMX_IOMUXC_DISP0_DAT6_ALT3_AUD6_RXC = 3,
+ IMX_IOMUXC_DISP0_DAT6_ALT5_GPIO4_IO27 = 5,
+} IMX_IOMUXC_DISP0_DAT6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT7_ALT0_IPU1_DISP0_DATA07 = 0,
+ IMX_IOMUXC_DISP0_DAT7_ALT2_ECSPI3_RDY = 2,
+ IMX_IOMUXC_DISP0_DAT7_ALT5_GPIO4_IO28 = 5,
+} IMX_IOMUXC_DISP0_DAT7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT8_ALT0_IPU1_DISP0_DATA08 = 0,
+ IMX_IOMUXC_DISP0_DAT8_ALT2_PWM1_OUT = 2,
+ IMX_IOMUXC_DISP0_DAT8_ALT3_WDOG1_B = 3,
+ IMX_IOMUXC_DISP0_DAT8_ALT5_GPIO4_IO29 = 5,
+} IMX_IOMUXC_DISP0_DAT8_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT9_ALT0_IPU1_DISP0_DATA09 = 0,
+ IMX_IOMUXC_DISP0_DAT9_ALT2_PWM2_OUT = 2,
+ IMX_IOMUXC_DISP0_DAT9_ALT3_WDOG2_B = 3,
+ IMX_IOMUXC_DISP0_DAT9_ALT5_GPIO4_IO30 = 5,
+} IMX_IOMUXC_DISP0_DAT9_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT10_ALT0_IPU1_DISP0_DATA10 = 0,
+ IMX_IOMUXC_DISP0_DAT10_ALT5_GPIO4_IO31 = 5,
+} IMX_IOMUXC_DISP0_DAT10_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_WAIT_ALT0_EIM_WAIT_B = 0,
+ IMX_IOMUXC_EIM_WAIT_ALT1_EIM_DTACK_B = 1,
+ IMX_IOMUXC_EIM_WAIT_ALT5_GPIO5_IO00 = 5,
+ IMX_IOMUXC_EIM_WAIT_ALT7_SRC_BOOT_CFG25 = 7,
+} IMX_IOMUXC_EIM_WAIT_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A25_ALT0_EIM_ADDR25 = 0,
+ IMX_IOMUXC_EIM_A25_ALT1_ECSPI4_SS1 = 1,
+ IMX_IOMUXC_EIM_A25_ALT2_ECSPI2_RDY = 2,
+ IMX_IOMUXC_EIM_A25_ALT3_IPU1_DI1_PIN12 = 3,
+ IMX_IOMUXC_EIM_A25_ALT4_IPU1_DI0_D1_CS = 4,
+ IMX_IOMUXC_EIM_A25_ALT5_GPIO5_IO02 = 5,
+ IMX_IOMUXC_EIM_A25_ALT6_HDMI_TX_CEC_LINE = 6,
+} IMX_IOMUXC_EIM_A25_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A24_ALT0_EIM_ADDR24 = 0,
+ IMX_IOMUXC_EIM_A24_ALT1_IPU1_DISP1_DATA19 = 1,
+ IMX_IOMUXC_EIM_A24_ALT2_IPU1_CSI1_DATA19 = 2,
+ IMX_IOMUXC_EIM_A24_ALT4_IPU1_SISG2 = 4,
+ IMX_IOMUXC_EIM_A24_ALT5_GPIO5_IO04 = 5,
+ IMX_IOMUXC_EIM_A24_ALT7_SRC_BOOT_CFG24 = 7,
+} IMX_IOMUXC_EIM_A24_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT11_ALT0_IPU1_DISP0_DATA11 = 0,
+ IMX_IOMUXC_DISP0_DAT11_ALT5_GPIO5_IO05 = 5,
+} IMX_IOMUXC_DISP0_DAT11_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT12_ALT0_IPU1_DISP0_DATA12 = 0,
+ IMX_IOMUXC_DISP0_DAT12_ALT5_GPIO5_IO06 = 5,
+} IMX_IOMUXC_DISP0_DAT12_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT13_ALT0_IPU1_DISP0_DATA13 = 0,
+ IMX_IOMUXC_DISP0_DAT13_ALT3_AUD5_RXFS = 3,
+ IMX_IOMUXC_DISP0_DAT13_ALT5_GPIO5_IO07 = 5,
+} IMX_IOMUXC_DISP0_DAT13_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT14_ALT0_IPU1_DISP0_DATA14 = 0,
+ IMX_IOMUXC_DISP0_DAT14_ALT3_AUD5_RXC = 3,
+ IMX_IOMUXC_DISP0_DAT14_ALT5_GPIO5_IO08 = 5,
+} IMX_IOMUXC_DISP0_DAT14_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT15_ALT0_IPU1_DISP0_DATA15 = 0,
+ IMX_IOMUXC_DISP0_DAT15_ALT2_ECSPI1_SS1 = 2,
+ IMX_IOMUXC_DISP0_DAT15_ALT3_ECSPI2_SS1 = 3,
+ IMX_IOMUXC_DISP0_DAT15_ALT5_GPIO5_IO09 = 5,
+} IMX_IOMUXC_DISP0_DAT15_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT16_ALT0_IPU1_DISP0_DATA16 = 0,
+ IMX_IOMUXC_DISP0_DAT16_ALT2_ECSPI2_MOSI = 2,
+ IMX_IOMUXC_DISP0_DAT16_ALT3_AUD5_TXC = 3,
+ IMX_IOMUXC_DISP0_DAT16_ALT4_SDMA_EXT_EVENT0 = 4,
+ IMX_IOMUXC_DISP0_DAT16_ALT5_GPIO5_IO10 = 5,
+} IMX_IOMUXC_DISP0_DAT16_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT17_ALT0_IPU1_DISP0_DATA17 = 0,
+ IMX_IOMUXC_DISP0_DAT17_ALT2_ECSPI2_MISO = 2,
+ IMX_IOMUXC_DISP0_DAT17_ALT3_AUD5_TXD = 3,
+ IMX_IOMUXC_DISP0_DAT17_ALT4_SDMA_EXT_EVENT1 = 4,
+ IMX_IOMUXC_DISP0_DAT17_ALT5_GPIO5_IO11 = 5,
+} IMX_IOMUXC_DISP0_DAT17_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT18_ALT0_IPU1_DISP0_DATA18 = 0,
+ IMX_IOMUXC_DISP0_DAT18_ALT2_ECSPI2_SS0 = 2,
+ IMX_IOMUXC_DISP0_DAT18_ALT3_AUD5_TXFS = 3,
+ IMX_IOMUXC_DISP0_DAT18_ALT4_AUD4_RXFS = 4,
+ IMX_IOMUXC_DISP0_DAT18_ALT5_GPIO5_IO12 = 5,
+ IMX_IOMUXC_DISP0_DAT18_ALT7_EIM_CS2_B = 7,
+} IMX_IOMUXC_DISP0_DAT18_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT19_ALT0_IPU1_DISP0_DATA19 = 0,
+ IMX_IOMUXC_DISP0_DAT19_ALT2_ECSPI2_SCLK = 2,
+ IMX_IOMUXC_DISP0_DAT19_ALT3_AUD5_RXD = 3,
+ IMX_IOMUXC_DISP0_DAT19_ALT4_AUD4_RXC = 4,
+ IMX_IOMUXC_DISP0_DAT19_ALT5_GPIO5_IO13 = 5,
+ IMX_IOMUXC_DISP0_DAT19_ALT7_EIM_CS3_B = 7,
+} IMX_IOMUXC_DISP0_DAT19_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT20_ALT0_IPU1_DISP0_DATA20 = 0,
+ IMX_IOMUXC_DISP0_DAT20_ALT2_ECSPI1_SCLK = 2,
+ IMX_IOMUXC_DISP0_DAT20_ALT3_AUD4_TXC = 3,
+ IMX_IOMUXC_DISP0_DAT20_ALT5_GPIO5_IO14 = 5,
+} IMX_IOMUXC_DISP0_DAT20_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT21_ALT0_IPU1_DISP0_DATA21 = 0,
+ IMX_IOMUXC_DISP0_DAT21_ALT2_ECSPI1_MOSI = 2,
+ IMX_IOMUXC_DISP0_DAT21_ALT3_AUD4_TXD = 3,
+ IMX_IOMUXC_DISP0_DAT21_ALT5_GPIO5_IO15 = 5,
+} IMX_IOMUXC_DISP0_DAT21_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT22_ALT0_IPU1_DISP0_DATA22 = 0,
+ IMX_IOMUXC_DISP0_DAT22_ALT2_ECSPI1_MISO = 2,
+ IMX_IOMUXC_DISP0_DAT22_ALT3_AUD4_TXFS = 3,
+ IMX_IOMUXC_DISP0_DAT22_ALT5_GPIO5_IO16 = 5,
+} IMX_IOMUXC_DISP0_DAT22_ALT;
+
+typedef enum {
+ IMX_IOMUXC_DISP0_DAT23_ALT0_IPU1_DISP0_DATA23 = 0,
+ IMX_IOMUXC_DISP0_DAT23_ALT2_ECSPI1_SS0 = 2,
+ IMX_IOMUXC_DISP0_DAT23_ALT3_AUD4_RXD = 3,
+ IMX_IOMUXC_DISP0_DAT23_ALT5_GPIO5_IO17 = 5,
+} IMX_IOMUXC_DISP0_DAT23_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_PIXCLK_ALT0_IPU1_CSI0_PIXCLK = 0,
+ IMX_IOMUXC_CSI0_PIXCLK_ALT5_GPIO5_IO18 = 5,
+ IMX_IOMUXC_CSI0_PIXCLK_ALT7_ARM_EVENTO = 7,
+} IMX_IOMUXC_CSI0_PIXCLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_MCLK_ALT0_IPU1_CSI0_HSYNC = 0,
+ IMX_IOMUXC_CSI0_MCLK_ALT3_CCM_CLKO1 = 3,
+ IMX_IOMUXC_CSI0_MCLK_ALT5_GPIO5_IO19 = 5,
+ IMX_IOMUXC_CSI0_MCLK_ALT7_ARM_TRACE_CTL = 7,
+} IMX_IOMUXC_CSI0_MCLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DATA_EN_ALT0_IPU1_CSI0_DATA_EN = 0,
+ IMX_IOMUXC_CSI0_DATA_EN_ALT1_EIM_DATA00 = 1,
+ IMX_IOMUXC_CSI0_DATA_EN_ALT5_GPIO5_IO20 = 5,
+ IMX_IOMUXC_CSI0_DATA_EN_ALT7_ARM_TRACE_CLK = 7,
+} IMX_IOMUXC_CSI0_DATA_EN_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_VSYNC_ALT0_IPU1_CSI0_VSYNC = 0,
+ IMX_IOMUXC_CSI0_VSYNC_ALT1_EIM_DATA01 = 1,
+ IMX_IOMUXC_CSI0_VSYNC_ALT5_GPIO5_IO21 = 5,
+ IMX_IOMUXC_CSI0_VSYNC_ALT7_ARM_TRACE00 = 7,
+} IMX_IOMUXC_CSI0_VSYNC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT4_ALT0_IPU1_CSI0_DATA04 = 0,
+ IMX_IOMUXC_CSI0_DAT4_ALT1_EIM_DATA02 = 1,
+ IMX_IOMUXC_CSI0_DAT4_ALT2_ECSPI1_SCLK = 2,
+ IMX_IOMUXC_CSI0_DAT4_ALT3_KEY_COL5 = 3,
+ IMX_IOMUXC_CSI0_DAT4_ALT4_AUD3_TXC = 4,
+ IMX_IOMUXC_CSI0_DAT4_ALT5_GPIO5_IO22 = 5,
+ IMX_IOMUXC_CSI0_DAT4_ALT7_ARM_TRACE01 = 7,
+} IMX_IOMUXC_CSI0_DAT4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT5_ALT0_IPU1_CSI0_DATA05 = 0,
+ IMX_IOMUXC_CSI0_DAT5_ALT1_EIM_DATA03 = 1,
+ IMX_IOMUXC_CSI0_DAT5_ALT2_ECSPI1_MOSI = 2,
+ IMX_IOMUXC_CSI0_DAT5_ALT3_KEY_ROW5 = 3,
+ IMX_IOMUXC_CSI0_DAT5_ALT4_AUD3_TXD = 4,
+ IMX_IOMUXC_CSI0_DAT5_ALT5_GPIO5_IO23 = 5,
+ IMX_IOMUXC_CSI0_DAT5_ALT7_ARM_TRACE02 = 7,
+} IMX_IOMUXC_CSI0_DAT5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT6_ALT0_IPU1_CSI0_DATA06 = 0,
+ IMX_IOMUXC_CSI0_DAT6_ALT1_EIM_DATA04 = 1,
+ IMX_IOMUXC_CSI0_DAT6_ALT2_ECSPI1_MISO = 2,
+ IMX_IOMUXC_CSI0_DAT6_ALT3_KEY_COL6 = 3,
+ IMX_IOMUXC_CSI0_DAT6_ALT4_AUD3_TXFS = 4,
+ IMX_IOMUXC_CSI0_DAT6_ALT5_GPIO5_IO24 = 5,
+ IMX_IOMUXC_CSI0_DAT6_ALT7_ARM_TRACE03 = 7,
+} IMX_IOMUXC_CSI0_DAT6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT7_ALT0_IPU1_CSI0_DATA07 = 0,
+ IMX_IOMUXC_CSI0_DAT7_ALT1_EIM_DATA05 = 1,
+ IMX_IOMUXC_CSI0_DAT7_ALT2_ECSPI1_SS0 = 2,
+ IMX_IOMUXC_CSI0_DAT7_ALT3_KEY_ROW6 = 3,
+ IMX_IOMUXC_CSI0_DAT7_ALT4_AUD3_RXD = 4,
+ IMX_IOMUXC_CSI0_DAT7_ALT5_GPIO5_IO25 = 5,
+ IMX_IOMUXC_CSI0_DAT7_ALT7_ARM_TRACE04 = 7,
+} IMX_IOMUXC_CSI0_DAT7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT8_ALT0_IPU1_CSI0_DATA08 = 0,
+ IMX_IOMUXC_CSI0_DAT8_ALT1_EIM_DATA06 = 1,
+ IMX_IOMUXC_CSI0_DAT8_ALT2_ECSPI2_SCLK = 2,
+ IMX_IOMUXC_CSI0_DAT8_ALT3_KEY_COL7 = 3,
+ IMX_IOMUXC_CSI0_DAT8_ALT4_I2C1_SDA = 4,
+ IMX_IOMUXC_CSI0_DAT8_ALT5_GPIO5_IO26 = 5,
+ IMX_IOMUXC_CSI0_DAT8_ALT7_ARM_TRACE05 = 7,
+} IMX_IOMUXC_CSI0_DAT8_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT9_ALT0_IPU1_CSI0_DATA09 = 0,
+ IMX_IOMUXC_CSI0_DAT9_ALT1_EIM_DATA07 = 1,
+ IMX_IOMUXC_CSI0_DAT9_ALT2_ECSPI2_MOSI = 2,
+ IMX_IOMUXC_CSI0_DAT9_ALT3_KEY_ROW7 = 3,
+ IMX_IOMUXC_CSI0_DAT9_ALT4_I2C1_SCL = 4,
+ IMX_IOMUXC_CSI0_DAT9_ALT5_GPIO5_IO27 = 5,
+ IMX_IOMUXC_CSI0_DAT9_ALT7_ARM_TRACE06 = 7,
+} IMX_IOMUXC_CSI0_DAT9_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT10_ALT0_IPU1_CSI0_DATA10 = 0,
+ IMX_IOMUXC_CSI0_DAT10_ALT1_AUD3_RXC = 1,
+ IMX_IOMUXC_CSI0_DAT10_ALT2_ECSPI2_MISO = 2,
+ IMX_IOMUXC_CSI0_DAT10_ALT3_UART1_TX_DATA = 3,
+ IMX_IOMUXC_CSI0_DAT10_ALT5_GPIO5_IO28 = 5,
+ IMX_IOMUXC_CSI0_DAT10_ALT7_ARM_TRACE07 = 7,
+} IMX_IOMUXC_CSI0_DAT10_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT11_ALT0_IPU1_CSI0_DATA11 = 0,
+ IMX_IOMUXC_CSI0_DAT11_ALT1_AUD3_RXFS = 1,
+ IMX_IOMUXC_CSI0_DAT11_ALT2_ECSPI2_SS0 = 2,
+ IMX_IOMUXC_CSI0_DAT11_ALT3_UART1_RX_DATA = 3,
+ IMX_IOMUXC_CSI0_DAT11_ALT5_GPIO5_IO29 = 5,
+ IMX_IOMUXC_CSI0_DAT11_ALT7_ARM_TRACE08 = 7,
+} IMX_IOMUXC_CSI0_DAT11_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT12_ALT0_IPU1_CSI0_DATA12 = 0,
+ IMX_IOMUXC_CSI0_DAT12_ALT1_EIM_DATA08 = 1,
+ IMX_IOMUXC_CSI0_DAT12_ALT3_UART4_TX_DATA = 3,
+ IMX_IOMUXC_CSI0_DAT12_ALT5_GPIO5_IO30 = 5,
+ IMX_IOMUXC_CSI0_DAT12_ALT7_ARM_TRACE09 = 7,
+} IMX_IOMUXC_CSI0_DAT12_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT13_ALT0_IPU1_CSI0_DATA13 = 0,
+ IMX_IOMUXC_CSI0_DAT13_ALT1_EIM_DATA09 = 1,
+ IMX_IOMUXC_CSI0_DAT13_ALT3_UART4_RX_DATA = 3,
+ IMX_IOMUXC_CSI0_DAT13_ALT5_GPIO5_IO31 = 5,
+ IMX_IOMUXC_CSI0_DAT13_ALT7_ARM_TRACE10 = 7,
+} IMX_IOMUXC_CSI0_DAT13_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT14_ALT0_IPU1_CSI0_DATA14 = 0,
+ IMX_IOMUXC_CSI0_DAT14_ALT1_EIM_DATA10 = 1,
+ IMX_IOMUXC_CSI0_DAT14_ALT3_UART5_TX_DATA = 3,
+ IMX_IOMUXC_CSI0_DAT14_ALT5_GPIO6_IO00 = 5,
+ IMX_IOMUXC_CSI0_DAT14_ALT7_ARM_TRACE11 = 7,
+} IMX_IOMUXC_CSI0_DAT14_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT15_ALT0_IPU1_CSI0_DATA15 = 0,
+ IMX_IOMUXC_CSI0_DAT15_ALT1_EIM_DATA11 = 1,
+ IMX_IOMUXC_CSI0_DAT15_ALT3_UART5_RX_DATA = 3,
+ IMX_IOMUXC_CSI0_DAT15_ALT5_GPIO6_IO01 = 5,
+ IMX_IOMUXC_CSI0_DAT15_ALT7_ARM_TRACE12 = 7,
+} IMX_IOMUXC_CSI0_DAT15_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT16_ALT0_IPU1_CSI0_DATA16 = 0,
+ IMX_IOMUXC_CSI0_DAT16_ALT1_EIM_DATA12 = 1,
+ IMX_IOMUXC_CSI0_DAT16_ALT3_UART4_RTS_B = 3,
+ IMX_IOMUXC_CSI0_DAT16_ALT5_GPIO6_IO02 = 5,
+ IMX_IOMUXC_CSI0_DAT16_ALT7_ARM_TRACE13 = 7,
+} IMX_IOMUXC_CSI0_DAT16_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT17_ALT0_IPU1_CSI0_DATA17 = 0,
+ IMX_IOMUXC_CSI0_DAT17_ALT1_EIM_DATA13 = 1,
+ IMX_IOMUXC_CSI0_DAT17_ALT3_UART4_CTS_B = 3,
+ IMX_IOMUXC_CSI0_DAT17_ALT5_GPIO6_IO03 = 5,
+ IMX_IOMUXC_CSI0_DAT17_ALT7_ARM_TRACE14 = 7,
+} IMX_IOMUXC_CSI0_DAT17_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT18_ALT0_IPU1_CSI0_DATA18 = 0,
+ IMX_IOMUXC_CSI0_DAT18_ALT1_EIM_DATA14 = 1,
+ IMX_IOMUXC_CSI0_DAT18_ALT3_UART5_RTS_B = 3,
+ IMX_IOMUXC_CSI0_DAT18_ALT5_GPIO6_IO04 = 5,
+ IMX_IOMUXC_CSI0_DAT18_ALT7_ARM_TRACE15 = 7,
+} IMX_IOMUXC_CSI0_DAT18_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI0_DAT19_ALT0_IPU1_CSI0_DATA19 = 0,
+ IMX_IOMUXC_CSI0_DAT19_ALT1_EIM_DATA15 = 1,
+ IMX_IOMUXC_CSI0_DAT19_ALT3_UART5_CTS_B = 3,
+ IMX_IOMUXC_CSI0_DAT19_ALT5_GPIO6_IO05 = 5,
+} IMX_IOMUXC_CSI0_DAT19_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_A23_ALT0_EIM_ADDR23 = 0,
+ IMX_IOMUXC_EIM_A23_ALT1_IPU1_DISP1_DATA18 = 1,
+ IMX_IOMUXC_EIM_A23_ALT2_IPU1_CSI1_DATA18 = 2,
+ IMX_IOMUXC_EIM_A23_ALT4_IPU1_SISG3 = 4,
+ IMX_IOMUXC_EIM_A23_ALT5_GPIO6_IO06 = 5,
+ IMX_IOMUXC_EIM_A23_ALT7_SRC_BOOT_CFG23 = 7,
+ IMX_IOMUXC_EIM_A23_ALT8_EPDC_GDOE = 8
+} IMX_IOMUXC_EIM_A23_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_CLE_ALT0_NAND_CLE = 0,
+ IMX_IOMUXC_NANDF_CLE_ALT5_GPIO6_IO07 = 5,
+} IMX_IOMUXC_NANDF_CLE_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_ALE_ALT0_NAND_ALE = 0,
+ IMX_IOMUXC_NANDF_ALE_ALT1_SD4_RESET = 1,
+ IMX_IOMUXC_NANDF_ALE_ALT5_GPIO6_IO08 = 5,
+} IMX_IOMUXC_NANDF_ALE_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_WP_B_ALT0_NAND_WP_B = 0,
+ IMX_IOMUXC_NANDF_WP_B_ALT5_GPIO6_IO09 = 5,
+ IMX_IOMUXC_NANDF_WP_B_ALT9_I2C4_SCL = 9
+} IMX_IOMUXC_NANDF_WP_B_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_RB0_ALT0_NAND_READY_B = 0,
+ IMX_IOMUXC_NANDF_RB0_ALT5_GPIO6_IO10 = 5,
+} IMX_IOMUXC_NANDF_RB0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_CS0_ALT0_NAND_CE0_B = 0,
+ IMX_IOMUXC_NANDF_CS0_ALT5_GPIO6_IO11 = 5,
+} IMX_IOMUXC_NANDF_CS0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_CS1_ALT0_NAND_CE1_B = 0,
+ IMX_IOMUXC_NANDF_CS1_ALT1_SD4_VSELECT = 1,
+ IMX_IOMUXC_NANDF_CS1_ALT2_SD3_VSELECT = 2,
+ IMX_IOMUXC_NANDF_CS1_ALT5_GPIO6_IO14 = 5,
+} IMX_IOMUXC_NANDF_CS1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_CS2_ALT0_NAND_CE2_B = 0,
+ IMX_IOMUXC_NANDF_CS2_ALT1_IPU1_SISG0 = 1,
+ IMX_IOMUXC_NANDF_CS2_ALT2_ESAI_TX0 = 2,
+ IMX_IOMUXC_NANDF_CS2_ALT3_EIM_CRE = 3,
+ IMX_IOMUXC_NANDF_CS2_ALT4_CCM_CLKO2 = 4,
+ IMX_IOMUXC_NANDF_CS2_ALT5_GPIO6_IO15 = 5
+} IMX_IOMUXC_NANDF_CS2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NANDF_CS3_ALT0_NAND_CE3_B = 0,
+ IMX_IOMUXC_NANDF_CS3_ALT1_IPU1_SISG1 = 1,
+ IMX_IOMUXC_NANDF_CS3_ALT2_ESAI_TX1 = 2,
+ IMX_IOMUXC_NANDF_CS3_ALT3_EIM_ADDR26 = 3,
+ IMX_IOMUXC_NANDF_CS3_ALT5_GPIO6_IO16 = 5,
+ IMX_IOMUXC_NANDF_CS3_ALT6_I2C4_SDA = 9,
+} IMX_IOMUXC_NANDF_CS3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT7_ALT0_SD3_DATA7 = 0,
+ IMX_IOMUXC_SD3_DAT7_ALT1_UART1_TX_DATA = 1,
+ IMX_IOMUXC_SD3_DAT7_ALT5_GPIO6_IO17 = 5,
+} IMX_IOMUXC_SD3_DAT7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT6_ALT0_SD3_DATA6 = 0,
+ IMX_IOMUXC_SD3_DAT6_ALT1_UART1_RX_DATA = 1,
+ IMX_IOMUXC_SD3_DAT6_ALT5_GPIO6_IO18 = 5,
+} IMX_IOMUXC_SD3_DAT6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_TXC_ALT0_USB_H2_DATA = 0,
+ IMX_IOMUXC_RGMII_TXC_ALT1_RGMII_TXC = 1,
+ IMX_IOMUXC_RGMII_TXC_ALT2_SPDIF_EXT_CLK = 2,
+ IMX_IOMUXC_RGMII_TXC_ALT5_GPIO6_IO19 = 5,
+ IMX_IOMUXC_RGMII_TXC_ALT7_XTALOSC_REF_CLK_24M = 7,
+} IMX_IOMUXC_RGMII_TXC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_TD0_ALT0_HSI_TX_READY = 0,
+ IMX_IOMUXC_RGMII_TD0_ALT1_RGMII_TD0 = 1,
+ IMX_IOMUXC_RGMII_TD0_ALT5_GPIO6_IO20 = 5,
+} IMX_IOMUXC_RGMII_TD0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_TD1_ALT0_HSI_RX_FLAG = 0,
+ IMX_IOMUXC_RGMII_TD1_ALT1_RGMII_TD1 = 1,
+ IMX_IOMUXC_RGMII_TD1_ALT5_GPIO6_IO21 = 5,
+} IMX_IOMUXC_RGMII_TD1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_TD2_ALT0_HSI_RX_DATA = 0,
+ IMX_IOMUXC_RGMII_TD2_ALT1_RGMII_TD2 = 1,
+ IMX_IOMUXC_RGMII_TD2_ALT5_GPIO6_IO22 = 5,
+} IMX_IOMUXC_RGMII_TD2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_TD3_ALT0_HSI_RX_WAKE = 0,
+ IMX_IOMUXC_RGMII_TD3_ALT1_RGMII_TD3 = 1,
+ IMX_IOMUXC_RGMII_TD3_ALT5_GPIO6_IO23 = 5,
+} IMX_IOMUXC_RGMII_TD3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_RX_CTL_ALT0_USB_H3_DATA = 0,
+ IMX_IOMUXC_RGMII_RX_CTL_ALT1_RGMII_RX_CTL = 1,
+ IMX_IOMUXC_RGMII_RX_CTL_ALT5_GPIO6_IO24 = 5,
+} IMX_IOMUXC_RGMII_RX_CTL_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_RD0_ALT0_HSI_RX_READY = 0,
+ IMX_IOMUXC_RGMII_RD0_ALT1_RGMII_RD0 = 1,
+ IMX_IOMUXC_RGMII_RD0_ALT5_GPIO6_IO25 = 5,
+} IMX_IOMUXC_RGMII_RD0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_TX_CTL_ALT0_USB_H2_STROBE = 0,
+ IMX_IOMUXC_RGMII_TX_CTL_ALT1_RGMII_TX_CTL = 1,
+ IMX_IOMUXC_RGMII_TX_CTL_ALT5_GPIO6_IO26 = 5,
+ IMX_IOMUXC_RGMII_TX_CTL_ALT7_ENET_REF_CLK = 7,
+} IMX_IOMUXC_RGMII_TX_CTL_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_RD1_ALT0_HSI_TX_FLAG = 0,
+ IMX_IOMUXC_RGMII_RD1_ALT1_RGMII_RD1 = 1,
+ IMX_IOMUXC_RGMII_RD1_ALT5_GPIO6_IO27 = 5,
+} IMX_IOMUXC_RGMII_RD1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_RD2_ALT0_HSI_TX_DATA = 0,
+ IMX_IOMUXC_RGMII_RD2_ALT1_RGMII_RD2 = 1,
+ IMX_IOMUXC_RGMII_RD2_ALT5_GPIO6_IO28 = 5,
+} IMX_IOMUXC_RGMII_RD2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_RD3_ALT0_HSI_TX_WAKE = 0,
+ IMX_IOMUXC_RGMII_RD3_ALT1_RGMII_RD3 = 1,
+ IMX_IOMUXC_RGMII_RD3_ALT5_GPIO6_IO29 = 5,
+} IMX_IOMUXC_RGMII_RD3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII_RXC_ALT0_USB_H3_STROBE = 0,
+ IMX_IOMUXC_RGMII_RXC_ALT1_RGMII_RXC = 1,
+ IMX_IOMUXC_RGMII_RXC_ALT5_GPIO6_IO30 = 5,
+} IMX_IOMUXC_RGMII_RXC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_EIM_BCLK_ALT0_EIM_BCLK = 0,
+ IMX_IOMUXC_EIM_BCLK_ALT1_IPU1_DI1_PIN16 = 1,
+ IMX_IOMUXC_EIM_BCLK_ALT5_GPIO6_IO31 = 5,
+} IMX_IOMUXC_EIM_BCLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT5_ALT0_SD3_DATA5 = 0,
+ IMX_IOMUXC_SD3_DAT5_ALT1_UART2_TX_DATA = 1,
+ IMX_IOMUXC_SD3_DAT5_ALT5_GPIO7_IO00 = 5,
+} IMX_IOMUXC_SD3_DAT5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT4_ALT0_SD3_DATA4 = 0,
+ IMX_IOMUXC_SD3_DAT4_ALT1_UART2_RX_DATA = 1,
+ IMX_IOMUXC_SD3_DAT4_ALT5_GPIO7_IO01 = 5,
+} IMX_IOMUXC_SD3_DAT4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_CMD_ALT0_SD3_CMD = 0,
+ IMX_IOMUXC_SD3_CMD_ALT1_UART2_CTS_B = 1,
+ IMX_IOMUXC_SD3_CMD_ALT2_FLEXCAN1_TX = 2,
+ IMX_IOMUXC_SD3_CMD_ALT5_GPIO7_IO02 = 5,
+} IMX_IOMUXC_SD3_CMD_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_CLK_ALT0_SD3_CLK = 0,
+ IMX_IOMUXC_SD3_CLK_ALT1_UART2_RTS_B = 1,
+ IMX_IOMUXC_SD3_CLK_ALT2_FLEXCAN1_RX = 2,
+ IMX_IOMUXC_SD3_CLK_ALT5_GPIO7_IO03 = 5,
+} IMX_IOMUXC_SD3_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT0_ALT0_SD3_DATA0 = 0,
+ IMX_IOMUXC_SD3_DAT0_ALT1_UART1_CTS_B = 1,
+ IMX_IOMUXC_SD3_DAT0_ALT2_FLEXCAN2_TX = 2,
+ IMX_IOMUXC_SD3_DAT0_ALT5_GPIO7_IO04 = 5,
+} IMX_IOMUXC_SD3_DAT0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT1_ALT0_SD3_DATA1 = 0,
+ IMX_IOMUXC_SD3_DAT1_ALT1_UART1_RTS_B = 1,
+ IMX_IOMUXC_SD3_DAT1_ALT2_FLEXCAN2_RX = 2,
+ IMX_IOMUXC_SD3_DAT1_ALT5_GPIO7_IO05 = 5,
+} IMX_IOMUXC_SD3_DAT1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT2_ALT0_SD3_DATA2 = 0,
+ IMX_IOMUXC_SD3_DAT2_ALT5_GPIO7_IO06 = 5,
+} IMX_IOMUXC_SD3_DAT2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DAT3_ALT0_SD3_DATA3 = 0,
+ IMX_IOMUXC_SD3_DAT3_ALT1_UART3_CTS_B = 1,
+ IMX_IOMUXC_SD3_DAT3_ALT5_GPIO7_IO07 = 5,
+} IMX_IOMUXC_SD3_DAT3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_RST_ALT0_SD3_RESET = 0,
+ IMX_IOMUXC_SD3_RST_ALT1_UART3_RTS_B = 1,
+ IMX_IOMUXC_SD3_RST_ALT5_GPIO7_IO08 = 5,
+} IMX_IOMUXC_SD3_RST_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_CMD_ALT0_SD4_CMD = 0,
+ IMX_IOMUXC_SD4_CMD_ALT1_NAND_RE_B = 1,
+ IMX_IOMUXC_SD4_CMD_ALT2_UART3_TX_DATA = 2,
+ IMX_IOMUXC_SD4_CMD_ALT5_GPIO7_IO09 = 5,
+} IMX_IOMUXC_SD4_CMD_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_CLK_ALT0_SD4_CLK = 0,
+ IMX_IOMUXC_SD4_CLK_ALT1_NAND_WE_B = 1,
+ IMX_IOMUXC_SD4_CLK_ALT2_UART3_RX_DATA = 2,
+ IMX_IOMUXC_SD4_CLK_ALT5_GPIO7_IO10 = 5,
+} IMX_IOMUXC_SD4_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_16_ALT0_ESAI_TX3_RX2 = 0,
+ IMX_IOMUXC_GPIO_16_ALT1_ENET_1588_EVENT2_IN = 1,
+ IMX_IOMUXC_GPIO_16_ALT2_ENET_REF_CLK = 2,
+ IMX_IOMUXC_GPIO_16_ALT3_SD1_LCTL = 3, // out LED
+ IMX_IOMUXC_GPIO_16_ALT4_SPDIF_IN = 4,
+ IMX_IOMUXC_GPIO_16_ALT5_GPIO7_IO11 = 5,
+ IMX_IOMUXC_GPIO_16_ALT6_I2C3_SDA = 6,
+ IMX_IOMUXC_GPIO_16_ALT7_JTAG_DE_B = 7,
+} IMX_IOMUXC_GPIO_16_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_17_ALT0_ESAI_TX0 = 0,
+ IMX_IOMUXC_GPIO_17_ALT1_ENET_1588_EVENT3_IN = 1,
+ IMX_IOMUXC_GPIO_17_ALT2_CCM_PMIC_READY = 2,
+ IMX_IOMUXC_GPIO_17_ALT3_SDMA_EXT_EVENT0 = 3,
+ IMX_IOMUXC_GPIO_17_ALT4_SPDIF_OUT = 4,
+ IMX_IOMUXC_GPIO_17_ALT5_GPIO7_IO12 = 5,
+} IMX_IOMUXC_GPIO_17_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO_18_ALT0_ESAI_TX1 = 0,
+ IMX_IOMUXC_GPIO_18_ALT1_ENET_RX_CLK = 1,
+ IMX_IOMUXC_GPIO_18_ALT2_SD3_VSELECT = 2,
+ IMX_IOMUXC_GPIO_18_ALT3_SDMA_EXT_EVENT1 = 3,
+ IMX_IOMUXC_GPIO_18_ALT4_ASRC_EXT_CLK = 4,
+ IMX_IOMUXC_GPIO_18_ALT5_GPIO7_IO13 = 5,
+ IMX_IOMUXC_GPIO_18_ALT6_SNVS_VIO_5_CTL = 6,
+} IMX_IOMUXC_GPIO_18_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ECSPI1_MISO_EIM_DATA17_ALT1 = 0,
+ IMX_IOMUXC_ECSPI1_MISO_DISP0_DATA22_ALT2 = 1,
+ IMX_IOMUXC_ECSPI1_MISO_KEY_COL1_ALT0 = 2,
+ IMX_IOMUXC_ECSPI1_MISO_CSI0_DATA06_ALT2 = 3,
+} IMX_IOMUXC_ECSPI1_MISO_SELECT_INPUT;
+
+typedef enum {
+ IMX_IOMUXC_ECSPI2_MISO_EIM_OE_B_ALT2 = 0,
+ IMX_IOMUXC_ECSPI2_MISO_DISP0_DATA17_ALT2 = 1,
+ IMX_IOMUXC_ECSPI2_MISO_CSI0_DATA10_ALT2 = 2,
+} IMX_IOMUXC_ECSPI2_MISO_SELECT_INPUT;
+
+#endif // _IMX6_IOMUX_SDL_H_
diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6IoMux_SX.h b/Silicon/NXP/iMX6Pkg/Include/iMX6IoMux_SX.h
new file mode 100644
index 000000000000..aa3732f16b18
--- /dev/null
+++ b/Silicon/NXP/iMX6Pkg/Include/iMX6IoMux_SX.h
@@ -0,0 +1,2275 @@
+/** @file
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _IMX6_IOMUX_SX_H_
+#define _IMX6_IOMUX_SX_H_
+
+//
+// IMX_PAD register defines.
+//
+typedef enum {
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00)
+ IMX_PAD_GPIO1_IO00 = _IMX_PAD(0x35C, 0x14), // I2C1_SCL
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01)
+ IMX_PAD_GPIO1_IO01 = _IMX_PAD(0x360, 0x18), // I2C1_SDA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02)
+ IMX_PAD_GPIO1_IO02 = _IMX_PAD(0x364, 0x1C), // I2C2_SCL
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03)
+ IMX_PAD_GPIO1_IO03 = _IMX_PAD(0x368, 0x20), // I2C2_SDA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04)
+ IMX_PAD_GPIO1_IO04 = _IMX_PAD(0x36C, 0x24), // UART1_TX_DATA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05)
+ IMX_PAD_GPIO1_IO05 = _IMX_PAD(0x370, 0x28), // UART1_RX_DATA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06)
+ IMX_PAD_GPIO1_IO06 = _IMX_PAD(0x374, 0x2C), // UART2_TX_DATA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07)
+ IMX_PAD_GPIO1_IO07 = _IMX_PAD(0x378, 0x30), // UART2_RX_DATA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08)
+ IMX_PAD_GPIO1_IO08 = _IMX_PAD(0x37C, 0x34), // USB_OTG1_OC
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09)
+ IMX_PAD_GPIO1_IO09 = _IMX_PAD(0x380, 0x38), // USB_OTG1_PWR
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10)
+ IMX_PAD_GPIO1_IO10 = _IMX_PAD(0x384, 0x3C), // USB_OTG1_ID
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11)
+ IMX_PAD_GPIO1_IO11 = _IMX_PAD(0x388, 0x40), // USB_OTG2_OC
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12)
+ IMX_PAD_GPIO1_IO12 = _IMX_PAD(0x38C, 0x44), // USB_OTG2_PWR
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13)
+ IMX_PAD_GPIO1_IO13 = _IMX_PAD(0x390, 0x48), // WDOG1_ANY
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00)
+ IMX_PAD_CSI_DATA00 = _IMX_PAD(0x394, 0x4C), // CSI1_DATA02
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01)
+ IMX_PAD_CSI_DATA01 = _IMX_PAD(0x398, 0x50), // CSI1_DATA03
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02)
+ IMX_PAD_CSI_DATA02 = _IMX_PAD(0x39C, 0x54), // CSI1_DATA04
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03)
+ IMX_PAD_CSI_DATA03 = _IMX_PAD(0x3A0, 0x58), // CSI1_DATA05
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04)
+ IMX_PAD_CSI_DATA04 = _IMX_PAD(0x3A4, 0x5C), // CSI1_DATA06
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05)
+ IMX_PAD_CSI_DATA05 = _IMX_PAD(0x3A8, 0x60), // CSI1_DATA07
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06)
+ IMX_PAD_CSI_DATA06 = _IMX_PAD(0x3AC, 0x64), // CSI1_DATA08
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07)
+ IMX_PAD_CSI_DATA07 = _IMX_PAD(0x3B0, 0x68), // CSI1_DATA09
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC)
+ IMX_PAD_CSI_HSYNC = _IMX_PAD(0x3B4, 0x6C), // CSI1_HSYNC
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK)
+ IMX_PAD_CSI_MCLK = _IMX_PAD(0x3B8, 0x70), // CSI1_MCLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK)
+ IMX_PAD_CSI_PIXCLK = _IMX_PAD(0x3BC, 0x74), // CSI1_PIXCLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC)
+ IMX_PAD_CSI_VSYNC = _IMX_PAD(0x3C0, 0x78), // CSI1_VSYNC
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET1_COL)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET1_COL)
+ IMX_PAD_ENET1_COL = _IMX_PAD(0x3C4, 0x7C), // ENET1_COL
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS)
+ IMX_PAD_ENET1_CRS = _IMX_PAD(0x3C8, 0x80), // ENET1_CRS
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC)
+ IMX_PAD_ENET1_MDC = _IMX_PAD(0x3CC, 0x84), // ENET1_MDC
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO)
+ IMX_PAD_ENET1_MDIO = _IMX_PAD(0x3D0, 0x88), // ENET1_MDIO
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK)
+ IMX_PAD_ENET1_RX_CLK = _IMX_PAD(0x3D4, 0x8C), // ENET1_RX_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK)
+ IMX_PAD_ENET1_TX_CLK = _IMX_PAD(0x3D8, 0x90), // ENET1_TX_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET2_COL)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET2_COL)
+ IMX_PAD_ENET2_COL = _IMX_PAD(0x3DC, 0x94), // ENET2_COL
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS)
+ IMX_PAD_ENET2_CRS = _IMX_PAD(0x3E0, 0x98), // ENET2_CRS
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK)
+ IMX_PAD_ENET2_RX_CLK = _IMX_PAD(0x3E4, 0x9C), // ENET2_RX_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK)
+ IMX_PAD_ENET2_TX_CLK = _IMX_PAD(0x3E8, 0xA0), // ENET2_TX_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL0)
+ IMX_PAD_KEY_COL0 = _IMX_PAD(0x3EC, 0xA4), // KPP_COL0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL1)
+ IMX_PAD_KEY_COL1 = _IMX_PAD(0x3F0, 0xA8), // KPP_COL1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL2)
+ IMX_PAD_KEY_COL2 = _IMX_PAD(0x3F4, 0xAC), // KPP_COL2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL3)
+ IMX_PAD_KEY_COL3 = _IMX_PAD(0x3F8, 0xB0), // KPP_COL3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_COL4)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_COL4)
+ IMX_PAD_KEY_COL4 = _IMX_PAD(0x3FC, 0xB4), // KPP_COL4
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0)
+ IMX_PAD_KEY_ROW0 = _IMX_PAD(0x400, 0xB8), // KPP_ROW0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1)
+ IMX_PAD_KEY_ROW1 = _IMX_PAD(0x404, 0xBC), // KPP_ROW1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2)
+ IMX_PAD_KEY_ROW2 = _IMX_PAD(0x408, 0xC0), // KPP_ROW2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3)
+ IMX_PAD_KEY_ROW3 = _IMX_PAD(0x40C, 0xC4), // KPP_ROW3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4)
+ IMX_PAD_KEY_ROW4 = _IMX_PAD(0x410, 0xC8), // KPP_ROW4
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK)
+ IMX_PAD_LCD1_CLK = _IMX_PAD(0x414, 0xCC), // LCD1_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00)
+ IMX_PAD_LCD1_DATA00 = _IMX_PAD(0x418, 0xD0), // LCD1_DATA00
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01)
+ IMX_PAD_LCD1_DATA01 = _IMX_PAD(0x41C, 0xD4), // LCD1_DATA01
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02)
+ IMX_PAD_LCD1_DATA02 = _IMX_PAD(0x420, 0xD8), // LCD1_DATA02
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03)
+ IMX_PAD_LCD1_DATA03 = _IMX_PAD(0x424, 0xDC), // LCD1_DATA03
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04)
+ IMX_PAD_LCD1_DATA04 = _IMX_PAD(0x428, 0xE0), // LCD1_DATA04
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05)
+ IMX_PAD_LCD1_DATA05 = _IMX_PAD(0x42C, 0xE4), // LCD1_DATA05
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06)
+ IMX_PAD_LCD1_DATA06 = _IMX_PAD(0x430, 0xE8), // LCD1_DATA06
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07)
+ IMX_PAD_LCD1_DATA07 = _IMX_PAD(0x434, 0xEC), // LCD1_DATA07
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08)
+ IMX_PAD_LCD1_DATA08 = _IMX_PAD(0x438, 0xF0), // LCD1_DATA08
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09)
+ IMX_PAD_LCD1_DATA09 = _IMX_PAD(0x43C, 0xF4), // LCD1_DATA09
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10)
+ IMX_PAD_LCD1_DATA10 = _IMX_PAD(0x440, 0xF8), // LCD1_DATA10
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11)
+ IMX_PAD_LCD1_DATA11 = _IMX_PAD(0x444, 0xFC), // LCD1_DATA11
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12)
+ IMX_PAD_LCD1_DATA12 = _IMX_PAD(0x448, 0x100), // LCD1_DATA12
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13)
+ IMX_PAD_LCD1_DATA13 = _IMX_PAD(0x44C, 0x104), // LCD1_DATA13
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14)
+ IMX_PAD_LCD1_DATA14 = _IMX_PAD(0x450, 0x108), // LCD1_DATA14
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15)
+ IMX_PAD_LCD1_DATA15 = _IMX_PAD(0x454, 0x10C), // LCD1_DATA15
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16)
+ IMX_PAD_LCD1_DATA16 = _IMX_PAD(0x458, 0x110), // LCD1_DATA16
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17)
+ IMX_PAD_LCD1_DATA17 = _IMX_PAD(0x45C, 0x114), // LCD1_DATA17
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18)
+ IMX_PAD_LCD1_DATA18 = _IMX_PAD(0x460, 0x118), // LCD1_DATA18
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19)
+ IMX_PAD_LCD1_DATA19 = _IMX_PAD(0x464, 0x11C), // LCD1_DATA19
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20)
+ IMX_PAD_LCD1_DATA20 = _IMX_PAD(0x468, 0x120), // LCD1_DATA20
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21)
+ IMX_PAD_LCD1_DATA21 = _IMX_PAD(0x46C, 0x124), // LCD1_DATA21
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22)
+ IMX_PAD_LCD1_DATA22 = _IMX_PAD(0x470, 0x128), // LCD1_DATA22
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23)
+ IMX_PAD_LCD1_DATA23 = _IMX_PAD(0x474, 0x12C), // LCD1_DATA23
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE)
+ IMX_PAD_LCD1_ENABLE = _IMX_PAD(0x478, 0x130), // LCD1_ENABLE
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC)
+ IMX_PAD_LCD1_HSYNC = _IMX_PAD(0x47C, 0x134), // LCD1_HSYNC
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET)
+ IMX_PAD_LCD1_RESET = _IMX_PAD(0x480, 0x138), // LCD1_RESET
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC)
+ IMX_PAD_LCD1_VSYNC = _IMX_PAD(0x484, 0x13C), // LCD1_VSYNC
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_ALE)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_ALE)
+ IMX_PAD_NAND_ALE = _IMX_PAD(0x488, 0x140), // NAND_ALE
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B)
+ IMX_PAD_NAND_CE0_B = _IMX_PAD(0x48C, 0x144), // NAND_CE0_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B)
+ IMX_PAD_NAND_CE1_B = _IMX_PAD(0x490, 0x148), // NAND_CE1_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_CLE)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_CLE)
+ IMX_PAD_NAND_CLE = _IMX_PAD(0x494, 0x14C), // NAND_CLE
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00)
+ IMX_PAD_NAND_DATA00 = _IMX_PAD(0x498, 0x150), // NAND_DATA00
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01)
+ IMX_PAD_NAND_DATA01 = _IMX_PAD(0x49C, 0x154), // NAND_DATA01
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02)
+ IMX_PAD_NAND_DATA02 = _IMX_PAD(0x4A0, 0x158), // NAND_DATA02
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03)
+ IMX_PAD_NAND_DATA03 = _IMX_PAD(0x4A4, 0x15C), // NAND_DATA03
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04)
+ IMX_PAD_NAND_DATA04 = _IMX_PAD(0x4A8, 0x160), // NAND_DATA04
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05)
+ IMX_PAD_NAND_DATA05 = _IMX_PAD(0x4AC, 0x164), // NAND_DATA05
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06)
+ IMX_PAD_NAND_DATA06 = _IMX_PAD(0x4B0, 0x168), // NAND_DATA06
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07)
+ IMX_PAD_NAND_DATA07 = _IMX_PAD(0x4B4, 0x16C), // NAND_DATA07
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B)
+ IMX_PAD_NAND_RE_B = _IMX_PAD(0x4B8, 0x170), // NAND_RE_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B)
+ IMX_PAD_NAND_READY_B = _IMX_PAD(0x4BC, 0x174), // NAND_READY_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B)
+ IMX_PAD_NAND_WE_B = _IMX_PAD(0x4C0, 0x178), // NAND_WE_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B)
+ IMX_PAD_NAND_WP_B = _IMX_PAD(0x4C4, 0x17C), // NAND_WP_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0)
+ IMX_PAD_QSPI1A_DATA0 = _IMX_PAD(0x4C8, 0x180), // QSPI1A_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1)
+ IMX_PAD_QSPI1A_DATA1 = _IMX_PAD(0x4CC, 0x184), // QSPI1A_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2)
+ IMX_PAD_QSPI1A_DATA2 = _IMX_PAD(0x4D0, 0x188), // QSPI1A_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3)
+ IMX_PAD_QSPI1A_DATA3 = _IMX_PAD(0x4D4, 0x18C), // QSPI1A_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS)
+ IMX_PAD_QSPI1A_DQS = _IMX_PAD(0x4D8, 0x190), // QSPI1A_DQS
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK)
+ IMX_PAD_QSPI1A_SCLK = _IMX_PAD(0x4DC, 0x194), // QSPI1A_SCLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B)
+ IMX_PAD_QSPI1A_SS0_B = _IMX_PAD(0x4E0, 0x198), // QSPI1A_SS0_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B)
+ IMX_PAD_QSPI1A_SS1_B = _IMX_PAD(0x4E4, 0x19C), // QSPI1A_SS1_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0)
+ IMX_PAD_QSPI1B_DATA0 = _IMX_PAD(0x4E8, 0x1A0), // QSPI1B_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1)
+ IMX_PAD_QSPI1B_DATA1 = _IMX_PAD(0x4EC, 0x1A4), // QSPI1B_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2)
+ IMX_PAD_QSPI1B_DATA2 = _IMX_PAD(0x4F0, 0x1A8), // QSPI1B_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3)
+ IMX_PAD_QSPI1B_DATA3 = _IMX_PAD(0x4F4, 0x1AC), // QSPI1B_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS)
+ IMX_PAD_QSPI1B_DQS = _IMX_PAD(0x4F8, 0x1B0), // QSPI1B_DQS
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK)
+ IMX_PAD_QSPI1B_SCLK = _IMX_PAD(0x4FC, 0x1B4), // QSPI1B_SCLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B)
+ IMX_PAD_QSPI1B_SS0_B = _IMX_PAD(0x500, 0x1B8), // QSPI1B_SS0_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B)
+ IMX_PAD_QSPI1B_SS1_B = _IMX_PAD(0x504, 0x1BC), // QSPI1B_SS1_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0)
+ IMX_PAD_RGMII1_RD0 = _IMX_PAD(0x508, 0x1C0), // ENET1_RX_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1)
+ IMX_PAD_RGMII1_RD1 = _IMX_PAD(0x50C, 0x1C4), // ENET1_RX_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2)
+ IMX_PAD_RGMII1_RD2 = _IMX_PAD(0x510, 0x1C8), // ENET1_RX_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3)
+ IMX_PAD_RGMII1_RD3 = _IMX_PAD(0x514, 0x1CC), // ENET1_RX_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL)
+ IMX_PAD_RGMII1_RX_CTL = _IMX_PAD(0x518, 0x1D0), // ENET1_RX_EN
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC)
+ IMX_PAD_RGMII1_RXC = _IMX_PAD(0x51C, 0x1D4), // ENET1_RGMII_RXC
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0)
+ IMX_PAD_RGMII1_TD0 = _IMX_PAD(0x520, 0x1D8), // ENET1_TX_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1)
+ IMX_PAD_RGMII1_TD1 = _IMX_PAD(0x524, 0x1DC), // ENET1_TX_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2)
+ IMX_PAD_RGMII1_TD2 = _IMX_PAD(0x528, 0x1E0), // ENET1_TX_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3)
+ IMX_PAD_RGMII1_TD3 = _IMX_PAD(0x52C, 0x1E4), // ENET1_TX_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL)
+ IMX_PAD_RGMII1_TX_CTL = _IMX_PAD(0x530, 0x1E8), // ENET1_TX_EN
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC)
+ IMX_PAD_RGMII1_TXC = _IMX_PAD(0x534, 0x1EC), // ENET1_RGMII_TXC
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0)
+ IMX_PAD_RGMII2_RD0 = _IMX_PAD(0x538, 0x1F0), // ENET2_RX_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1)
+ IMX_PAD_RGMII2_RD1 = _IMX_PAD(0x53C, 0x1F4), // ENET2_RX_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2)
+ IMX_PAD_RGMII2_RD2 = _IMX_PAD(0x540, 0x1F8), // ENET2_RX_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3)
+ IMX_PAD_RGMII2_RD3 = _IMX_PAD(0x544, 0x1FC), // ENET2_RX_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL)
+ IMX_PAD_RGMII2_RX_CTL = _IMX_PAD(0x548, 0x200), // ENET2_RX_EN
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC)
+ IMX_PAD_RGMII2_RXC = _IMX_PAD(0x54C, 0x204), // ENET2_RGMII_RXC
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0)
+ IMX_PAD_RGMII2_TD0 = _IMX_PAD(0x550, 0x208), // ENET2_TX_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1)
+ IMX_PAD_RGMII2_TD1 = _IMX_PAD(0x554, 0x20C), // ENET2_TX_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2)
+ IMX_PAD_RGMII2_TD2 = _IMX_PAD(0x558, 0x210), // ENET2_TX_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3)
+ IMX_PAD_RGMII2_TD3 = _IMX_PAD(0x55C, 0x214), // ENET2_TX_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL)
+ IMX_PAD_RGMII2_TX_CTL = _IMX_PAD(0x560, 0x218), // ENET2_TX_EN
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC)
+ IMX_PAD_RGMII2_TXC = _IMX_PAD(0x564, 0x21C), // ENET2_RGMII_TXC
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_CLK)
+ IMX_PAD_SD1_CLK = _IMX_PAD(0x568, 0x220), // SD1_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_CMD)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_CMD)
+ IMX_PAD_SD1_CMD = _IMX_PAD(0x56C, 0x224), // SD1_CMD
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0)
+ IMX_PAD_SD1_DATA0 = _IMX_PAD(0x570, 0x228), // SD1_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1)
+ IMX_PAD_SD1_DATA1 = _IMX_PAD(0x574, 0x22C), // SD1_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2)
+ IMX_PAD_SD1_DATA2 = _IMX_PAD(0x578, 0x230), // SD1_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3)
+ IMX_PAD_SD1_DATA3 = _IMX_PAD(0x57C, 0x234), // SD1_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_CLK)
+ IMX_PAD_SD2_CLK = _IMX_PAD(0x580, 0x238), // SD2_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_CMD)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_CMD)
+ IMX_PAD_SD2_CMD = _IMX_PAD(0x584, 0x23C), // SD2_CMD
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0)
+ IMX_PAD_SD2_DATA0 = _IMX_PAD(0x588, 0x240), // SD2_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1)
+ IMX_PAD_SD2_DATA1 = _IMX_PAD(0x58C, 0x244), // SD2_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2)
+ IMX_PAD_SD2_DATA2 = _IMX_PAD(0x590, 0x248), // SD2_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3)
+ IMX_PAD_SD2_DATA3 = _IMX_PAD(0x594, 0x24C), // SD2_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_CLK)
+ IMX_PAD_SD4_CLK = _IMX_PAD(0x5C0, 0x278), // SD4_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_CMD)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_CMD)
+ IMX_PAD_SD4_CMD = _IMX_PAD(0x5C4, 0x27C), // SD4_CMD
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0)
+ IMX_PAD_SD4_DATA0 = _IMX_PAD(0x5C8, 0x280), // SD4_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1)
+ IMX_PAD_SD4_DATA1 = _IMX_PAD(0x5CC, 0x284), // SD4_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2)
+ IMX_PAD_SD4_DATA2 = _IMX_PAD(0x5D0, 0x288), // SD4_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3)
+ IMX_PAD_SD4_DATA3 = _IMX_PAD(0x5D4, 0x28C), // SD4_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4)
+ IMX_PAD_SD4_DATA4 = _IMX_PAD(0x5D8, 0x290), // SD4_DATA4
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5)
+ IMX_PAD_SD4_DATA5 = _IMX_PAD(0x5DC, 0x294), // SD4_DATA5
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6)
+ IMX_PAD_SD4_DATA6 = _IMX_PAD(0x5E0, 0x298), // SD4_DATA6
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7)
+ IMX_PAD_SD4_DATA7 = _IMX_PAD(0x5E4, 0x29C), // SD4_DATA7
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B)
+ IMX_PAD_SD4_RESET_B = _IMX_PAD(0x5E8, 0x2A0), // SD4_RESET_B
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_CLK)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_CLK)
+ IMX_PAD_SD3_CLK = _IMX_PAD(0x598, 0x250), // SD3_CLK
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_CMD)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_CMD)
+ IMX_PAD_SD3_CMD = _IMX_PAD(0x59C, 0x254), // SD3_CMD
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0)
+ IMX_PAD_SD3_DATA0 = _IMX_PAD(0x5A0, 0x258), // SD3_DATA0
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1)
+ IMX_PAD_SD3_DATA1 = _IMX_PAD(0x5A4, 0x25C), // SD3_DATA1
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2)
+ IMX_PAD_SD3_DATA2 = _IMX_PAD(0x5A8, 0x260), // SD3_DATA2
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3)
+ IMX_PAD_SD3_DATA3 = _IMX_PAD(0x5AC, 0x264), // SD3_DATA3
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4)
+ IMX_PAD_SD3_DATA4 = _IMX_PAD(0x5B0, 0x268), // SD3_DATA4
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5)
+ IMX_PAD_SD3_DATA5 = _IMX_PAD(0x5B4, 0x26C), // SD3_DATA5
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6)
+ IMX_PAD_SD3_DATA6 = _IMX_PAD(0x5B8, 0x270), // SD3_DATA6
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7)
+ IMX_PAD_SD3_DATA7 = _IMX_PAD(0x5BC, 0x274), // SD3_DATA7
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA)
+ IMX_PAD_USB_H_DATA = _IMX_PAD(0x5EC, 0x2A4), // USB_H_DATA
+
+ // Pad Control Register (IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE)
+ // Pad Mux Register (IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE)
+ IMX_PAD_USB_H_STROBE = _IMX_PAD(0x5F0, 0x2A8), // USB_H_STROBE
+
+} IMX_PAD;
+
+//
+// Alternate function numbers
+//
+
+// Alternate function numbers
+typedef enum {
+ IMX_IOMUXC_GPIO1_IO00_ALT0_I2C1_SCL = 0,
+ IMX_IOMUXC_GPIO1_IO00_ALT1_SD1_VSELECT = 1,
+ IMX_IOMUXC_GPIO1_IO00_ALT2_SPDIF_LOCK = 2,
+ IMX_IOMUXC_GPIO1_IO00_ALT4_WDOG1_ANY = 4,
+ IMX_IOMUXC_GPIO1_IO00_ALT5_GPIO1_IO00 = 5,
+ IMX_IOMUXC_GPIO1_IO00_ALT6_SNVS_VIO_5 = 6,
+} IMX_IOMUXC_GPIO1_IO00_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO1_IO01_ALT0_I2C1_SDA = 0,
+ IMX_IOMUXC_GPIO1_IO01_ALT1_SD1_RESET_B = 1,
+ IMX_IOMUXC_GPIO1_IO01_ALT2_SPDIF_SR_CLK = 2,
+ IMX_IOMUXC_GPIO1_IO01_ALT4_WDOG3_B = 4,
+ IMX_IOMUXC_GPIO1_IO01_ALT5_GPIO1_IO01 = 5,
+ IMX_IOMUXC_GPIO1_IO01_ALT6_SNVS_VIO_5_CTL = 6,
+} IMX_IOMUXC_GPIO1_IO01_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO1_IO02_ALT0_I2C2_SCL = 0,
+ IMX_IOMUXC_GPIO1_IO02_ALT1_SD1_CD_B = 1,
+ IMX_IOMUXC_GPIO1_IO02_ALT2_CSI2_MCLK = 2,
+ IMX_IOMUXC_GPIO1_IO02_ALT4_WDOG1_B = 4,
+ IMX_IOMUXC_GPIO1_IO02_ALT5_GPIO1_IO02 = 5,
+ IMX_IOMUXC_GPIO1_IO02_ALT6_CCM_REF_EN_B = 6,
+} IMX_IOMUXC_GPIO1_IO02_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO1_IO03_ALT0_I2C2_SDA = 0,
+ IMX_IOMUXC_GPIO1_IO03_ALT1_SD1_WP = 1,
+ IMX_IOMUXC_GPIO1_IO03_ALT2_ENET1_REF_CLK_25M = 2,
+ IMX_IOMUXC_GPIO1_IO03_ALT4_WDOG2_B = 4,
+ IMX_IOMUXC_GPIO1_IO03_ALT5_GPIO1_IO03 = 5,
+} IMX_IOMUXC_GPIO1_IO03_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO1_IO04_ALT0_UART1_TX_DATA = 0,
+ IMX_IOMUXC_GPIO1_IO04_ALT1_SD2_RESET_B = 1,
+ IMX_IOMUXC_GPIO1_IO04_ALT2_ENET1_MDC = 2,
+ IMX_IOMUXC_GPIO1_IO04_ALT4_ENET2_REF_CLK2 = 4,
+ IMX_IOMUXC_GPIO1_IO04_ALT5_GPIO1_IO04 = 5,
+} IMX_IOMUXC_GPIO1_IO04_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO1_IO05_ALT0_UART1_RX_DATA = 0,
+ IMX_IOMUXC_GPIO1_IO05_ALT1_SD2_VSELECT = 1,
+ IMX_IOMUXC_GPIO1_IO05_ALT2_ENET1_MDIO = 2,
+ IMX_IOMUXC_GPIO1_IO05_ALT3_ASRC_EXT_CLK = 3,
+ IMX_IOMUXC_GPIO1_IO05_ALT4_ENET1_REF_CLK1 = 4,
+ IMX_IOMUXC_GPIO1_IO05_ALT5_GPIO1_IO05 = 5,
+} IMX_IOMUXC_GPIO1_IO05_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO1_IO06_ALT0_UART2_TX_DATA = 0,
+ IMX_IOMUXC_GPIO1_IO06_ALT1_SD2_CD_B = 1,
+ IMX_IOMUXC_GPIO1_IO06_ALT2_ENET2_MDC = 2,
+ IMX_IOMUXC_GPIO1_IO06_ALT3_CSI1_MCLK = 3,
+ IMX_IOMUXC_GPIO1_IO06_ALT4_UART1_RTS_B = 4,
+ IMX_IOMUXC_GPIO1_IO06_ALT5_GPIO1_IO06 = 5,
+} IMX_IOMUXC_GPIO1_IO06_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO1_IO07_ALT0_UART2_RX_DATA = 0,
+ IMX_IOMUXC_GPIO1_IO07_ALT1_SD2_WP = 1,
+ IMX_IOMUXC_GPIO1_IO07_ALT2_ENET2_MDIO = 2,
+ IMX_IOMUXC_GPIO1_IO07_ALT3_AUDIO_CLK_OUT = 3,
+ IMX_IOMUXC_GPIO1_IO07_ALT4_UART1_CTS_B = 4,
+ IMX_IOMUXC_GPIO1_IO07_ALT5_GPIO1_IO07 = 5,
+ IMX_IOMUXC_GPIO1_IO07_ALT7_DCIC2_OUT = 7,
+} IMX_IOMUXC_GPIO1_IO07_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO1_IO08_ALT0_USB_OTG1_OC = 0,
+ IMX_IOMUXC_GPIO1_IO08_ALT1_WDOG1_B = 1,
+ IMX_IOMUXC_GPIO1_IO08_ALT2_SDMA_EXT_EVENT0 = 2,
+ IMX_IOMUXC_GPIO1_IO08_ALT3_CCM_PMIC_READY = 3,
+ IMX_IOMUXC_GPIO1_IO08_ALT4_UART2_RTS_B = 4,
+ IMX_IOMUXC_GPIO1_IO08_ALT5_GPIO1_IO08 = 5,
+ IMX_IOMUXC_GPIO1_IO08_ALT7_DCIC1_OUT = 7,
+} IMX_IOMUXC_GPIO1_IO08_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO1_IO09_ALT0_USB_OTG1_PWR = 0,
+ IMX_IOMUXC_GPIO1_IO09_ALT1_WDOG2_B = 1,
+ IMX_IOMUXC_GPIO1_IO09_ALT2_SDMA_EXT_EVENT1 = 2,
+ IMX_IOMUXC_GPIO1_IO09_ALT4_UART2_CTS_B = 4,
+ IMX_IOMUXC_GPIO1_IO09_ALT5_GPIO1_IO09 = 5,
+} IMX_IOMUXC_GPIO1_IO09_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO1_IO10_ALT0_USB_OTG1_ID = 0,
+ IMX_IOMUXC_GPIO1_IO10_ALT1_SPDIF_EXT_CLK = 1,
+ IMX_IOMUXC_GPIO1_IO10_ALT2_PWM1_OUT = 2,
+ IMX_IOMUXC_GPIO1_IO10_ALT4_CSI1_FIELD = 4,
+ IMX_IOMUXC_GPIO1_IO10_ALT5_GPIO1_IO10 = 5,
+} IMX_IOMUXC_GPIO1_IO10_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO1_IO11_ALT0_USB_OTG2_OC = 0,
+ IMX_IOMUXC_GPIO1_IO11_ALT1_SPDIF_IN = 1,
+ IMX_IOMUXC_GPIO1_IO11_ALT2_PWM2_OUT = 2,
+ IMX_IOMUXC_GPIO1_IO11_ALT3_CCM_CLKO1 = 3,
+ IMX_IOMUXC_GPIO1_IO11_ALT4_MLB_DATA = 4,
+ IMX_IOMUXC_GPIO1_IO11_ALT5_GPIO1_IO11 = 5,
+} IMX_IOMUXC_GPIO1_IO11_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO1_IO12_ALT0_USB_OTG2_PWR = 0,
+ IMX_IOMUXC_GPIO1_IO12_ALT1_SPDIF_OUT = 1,
+ IMX_IOMUXC_GPIO1_IO12_ALT2_PWM3_OUT = 2,
+ IMX_IOMUXC_GPIO1_IO12_ALT3_CCM_CLKO2 = 3,
+ IMX_IOMUXC_GPIO1_IO12_ALT4_MLB_CLK = 4,
+ IMX_IOMUXC_GPIO1_IO12_ALT5_GPIO1_IO12 = 5,
+} IMX_IOMUXC_GPIO1_IO12_ALT;
+
+typedef enum {
+ IMX_IOMUXC_GPIO1_IO13_ALT0_WDOG1_ANY = 0,
+ IMX_IOMUXC_GPIO1_IO13_ALT1_USB_OTG2_ID = 1,
+ IMX_IOMUXC_GPIO1_IO13_ALT2_PWM4_OUT = 2,
+ IMX_IOMUXC_GPIO1_IO13_ALT4_MLB_SIG = 4,
+ IMX_IOMUXC_GPIO1_IO13_ALT5_GPIO1_IO13 = 5,
+} IMX_IOMUXC_GPIO1_IO13_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI_DATA00_ALT0_CSI1_DATA02 = 0,
+ IMX_IOMUXC_CSI_DATA00_ALT1_ESAI_TX_CLK = 1,
+ IMX_IOMUXC_CSI_DATA00_ALT2_AUD6_TXC = 2,
+ IMX_IOMUXC_CSI_DATA00_ALT3_I2C1_SCL = 3,
+ IMX_IOMUXC_CSI_DATA00_ALT4_UART6_RI_B = 4,
+ IMX_IOMUXC_CSI_DATA00_ALT5_GPIO1_IO14 = 5,
+ IMX_IOMUXC_CSI_DATA00_ALT6_EIM_DATA23 = 6,
+ IMX_IOMUXC_CSI_DATA00_ALT7_SAI1_TX_BCLK = 7,
+} IMX_IOMUXC_CSI_DATA00_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI_DATA01_ALT0_CSI1_DATA03 = 0,
+ IMX_IOMUXC_CSI_DATA01_ALT1_ESAI_TX_FS = 1,
+ IMX_IOMUXC_CSI_DATA01_ALT2_AUD6_TXFS = 2,
+ IMX_IOMUXC_CSI_DATA01_ALT3_I2C1_SDA = 3,
+ IMX_IOMUXC_CSI_DATA01_ALT4_UART6_DSR_B = 4,
+ IMX_IOMUXC_CSI_DATA01_ALT5_GPIO1_IO15 = 5,
+ IMX_IOMUXC_CSI_DATA01_ALT6_EIM_DATA22 = 6,
+ IMX_IOMUXC_CSI_DATA01_ALT7_SAI1_TX_SYNC = 7,
+} IMX_IOMUXC_CSI_DATA01_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI_DATA02_ALT0_CSI1_DATA04 = 0,
+ IMX_IOMUXC_CSI_DATA02_ALT1_ESAI_RX_CLK = 1,
+ IMX_IOMUXC_CSI_DATA02_ALT2_AUD6_RXC = 2,
+ IMX_IOMUXC_CSI_DATA02_ALT3_KPP_COL5 = 3,
+ IMX_IOMUXC_CSI_DATA02_ALT4_UART6_DTR_B = 4,
+ IMX_IOMUXC_CSI_DATA02_ALT5_GPIO1_IO16 = 5,
+ IMX_IOMUXC_CSI_DATA02_ALT6_EIM_DATA21 = 6,
+ IMX_IOMUXC_CSI_DATA02_ALT7_SAI1_RX_BCLK = 7,
+} IMX_IOMUXC_CSI_DATA02_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI_DATA03_ALT0_CSI1_DATA05 = 0,
+ IMX_IOMUXC_CSI_DATA03_ALT1_ESAI_RX_FS = 1,
+ IMX_IOMUXC_CSI_DATA03_ALT2_AUD6_RXFS = 2,
+ IMX_IOMUXC_CSI_DATA03_ALT3_KPP_ROW5 = 3,
+ IMX_IOMUXC_CSI_DATA03_ALT4_UART6_DCD_B = 4,
+ IMX_IOMUXC_CSI_DATA03_ALT5_GPIO1_IO17 = 5,
+ IMX_IOMUXC_CSI_DATA03_ALT6_EIM_DATA20 = 6,
+ IMX_IOMUXC_CSI_DATA03_ALT7_SAI1_RX_SYNC = 7,
+} IMX_IOMUXC_CSI_DATA03_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI_DATA04_ALT0_CSI1_DATA06 = 0,
+ IMX_IOMUXC_CSI_DATA04_ALT1_ESAI_TX1 = 1,
+ IMX_IOMUXC_CSI_DATA04_ALT2_SPDIF_OUT = 2,
+ IMX_IOMUXC_CSI_DATA04_ALT3_KPP_COL6 = 3,
+ IMX_IOMUXC_CSI_DATA04_ALT4_UART6_RX_DATA = 4,
+ IMX_IOMUXC_CSI_DATA04_ALT5_GPIO1_IO18 = 5,
+ IMX_IOMUXC_CSI_DATA04_ALT6_EIM_DATA19 = 6,
+ IMX_IOMUXC_CSI_DATA04_ALT7_PWM5_OUT = 7,
+} IMX_IOMUXC_CSI_DATA04_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI_DATA05_ALT0_CSI1_DATA07 = 0,
+ IMX_IOMUXC_CSI_DATA05_ALT1_ESAI_TX4_RX1 = 1,
+ IMX_IOMUXC_CSI_DATA05_ALT2_SPDIF_IN = 2,
+ IMX_IOMUXC_CSI_DATA05_ALT3_KPP_ROW6 = 3,
+ IMX_IOMUXC_CSI_DATA05_ALT4_UART6_TX_DATA = 4,
+ IMX_IOMUXC_CSI_DATA05_ALT5_GPIO1_IO19 = 5,
+ IMX_IOMUXC_CSI_DATA05_ALT6_EIM_DATA18 = 6,
+ IMX_IOMUXC_CSI_DATA05_ALT7_PWM6_OUT = 7,
+} IMX_IOMUXC_CSI_DATA05_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI_DATA06_ALT0_CSI1_DATA08 = 0,
+ IMX_IOMUXC_CSI_DATA06_ALT1_ESAI_TX2_RX3 = 1,
+ IMX_IOMUXC_CSI_DATA06_ALT2_I2C4_SCL = 2,
+ IMX_IOMUXC_CSI_DATA06_ALT3_KPP_COL7 = 3,
+ IMX_IOMUXC_CSI_DATA06_ALT4_UART6_RTS_B = 4,
+ IMX_IOMUXC_CSI_DATA06_ALT5_GPIO1_IO20 = 5,
+ IMX_IOMUXC_CSI_DATA06_ALT6_EIM_DATA17 = 6,
+ IMX_IOMUXC_CSI_DATA06_ALT7_DCIC2_OUT = 7,
+} IMX_IOMUXC_CSI_DATA06_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI_DATA07_ALT0_CSI1_DATA09 = 0,
+ IMX_IOMUXC_CSI_DATA07_ALT1_ESAI_TX3_RX2 = 1,
+ IMX_IOMUXC_CSI_DATA07_ALT2_I2C4_SDA = 2,
+ IMX_IOMUXC_CSI_DATA07_ALT3_KPP_ROW7 = 3,
+ IMX_IOMUXC_CSI_DATA07_ALT4_UART6_CTS_B = 4,
+ IMX_IOMUXC_CSI_DATA07_ALT5_GPIO1_IO21 = 5,
+ IMX_IOMUXC_CSI_DATA07_ALT6_EIM_DATA16 = 6,
+ IMX_IOMUXC_CSI_DATA07_ALT7_DCIC1_OUT = 7,
+} IMX_IOMUXC_CSI_DATA07_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI_HSYNC_ALT0_CSI1_HSYNC = 0,
+ IMX_IOMUXC_CSI_HSYNC_ALT1_ESAI_TX0 = 1,
+ IMX_IOMUXC_CSI_HSYNC_ALT2_AUD6_TXD = 2,
+ IMX_IOMUXC_CSI_HSYNC_ALT3_UART4_RTS_B = 3,
+ IMX_IOMUXC_CSI_HSYNC_ALT4_MQS_LEFT = 4,
+ IMX_IOMUXC_CSI_HSYNC_ALT5_GPIO1_IO22 = 5,
+ IMX_IOMUXC_CSI_HSYNC_ALT6_EIM_DATA25 = 6,
+ IMX_IOMUXC_CSI_HSYNC_ALT7_SAI1_TX_DATA0 = 7,
+} IMX_IOMUXC_CSI_HSYNC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI_MCLK_ALT0_CSI1_MCLK = 0,
+ IMX_IOMUXC_CSI_MCLK_ALT1_ESAI_TX_HF_CLK = 1,
+ IMX_IOMUXC_CSI_MCLK_ALT3_UART4_RX_DATA = 3,
+ IMX_IOMUXC_CSI_MCLK_ALT4_XTALOSC_REF_CLK_32K = 4,
+ IMX_IOMUXC_CSI_MCLK_ALT5_GPIO1_IO23 = 5,
+ IMX_IOMUXC_CSI_MCLK_ALT6_EIM_DATA26 = 6,
+ IMX_IOMUXC_CSI_MCLK_ALT7_CSI1_FIELD = 7,
+} IMX_IOMUXC_CSI_MCLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI_PIXCLK_ALT0_CSI1_PIXCLK = 0,
+ IMX_IOMUXC_CSI_PIXCLK_ALT1_ESAI_RX_HF_CLK = 1,
+ IMX_IOMUXC_CSI_PIXCLK_ALT2_AUDIO_CLK_OUT = 2,
+ IMX_IOMUXC_CSI_PIXCLK_ALT3_UART4_TX_DATA = 3,
+ IMX_IOMUXC_CSI_PIXCLK_ALT4_XTALOSC_REF_CLK_24M = 4,
+ IMX_IOMUXC_CSI_PIXCLK_ALT5_GPIO1_IO24 = 5,
+ IMX_IOMUXC_CSI_PIXCLK_ALT6_EIM_DATA27 = 6,
+ IMX_IOMUXC_CSI_PIXCLK_ALT7_ESAI_TX_HF_CLK = 7,
+} IMX_IOMUXC_CSI_PIXCLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_CSI_VSYNC_ALT0_CSI1_VSYNC = 0,
+ IMX_IOMUXC_CSI_VSYNC_ALT1_ESAI_TX5_RX0 = 1,
+ IMX_IOMUXC_CSI_VSYNC_ALT2_AUD6_RXD = 2,
+ IMX_IOMUXC_CSI_VSYNC_ALT3_UART4_CTS_B = 3,
+ IMX_IOMUXC_CSI_VSYNC_ALT4_MQS_RIGHT = 4,
+ IMX_IOMUXC_CSI_VSYNC_ALT5_GPIO1_IO25 = 5,
+ IMX_IOMUXC_CSI_VSYNC_ALT6_EIM_DATA24 = 6,
+ IMX_IOMUXC_CSI_VSYNC_ALT7_SAI1_RX_DATA0 = 7,
+} IMX_IOMUXC_CSI_VSYNC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET1_COL_ALT0_ENET1_COL = 0,
+ IMX_IOMUXC_ENET1_COL_ALT1_ENET2_MDC = 1,
+ IMX_IOMUXC_ENET1_COL_ALT2_AUD4_TXC = 2,
+ IMX_IOMUXC_ENET1_COL_ALT3_UART1_RI_B = 3,
+ IMX_IOMUXC_ENET1_COL_ALT4_SPDIF_EXT_CLK = 4,
+ IMX_IOMUXC_ENET1_COL_ALT5_GPIO2_IO00 = 5,
+ IMX_IOMUXC_ENET1_COL_ALT6_CSI2_DATA23 = 6,
+ IMX_IOMUXC_ENET1_COL_ALT7_LCD2_DATA16 = 7,
+} IMX_IOMUXC_ENET1_COL_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET1_CRS_ALT0_ENET1_CRS = 0,
+ IMX_IOMUXC_ENET1_CRS_ALT1_ENET2_MDIO = 1,
+ IMX_IOMUXC_ENET1_CRS_ALT2_AUD4_TXD = 2,
+ IMX_IOMUXC_ENET1_CRS_ALT3_UART1_DCD_B = 3,
+ IMX_IOMUXC_ENET1_CRS_ALT4_SPDIF_LOCK = 4,
+ IMX_IOMUXC_ENET1_CRS_ALT5_GPIO2_IO01 = 5,
+ IMX_IOMUXC_ENET1_CRS_ALT6_CSI2_DATA22 = 6,
+ IMX_IOMUXC_ENET1_CRS_ALT7_LCD2_DATA17 = 7,
+} IMX_IOMUXC_ENET1_CRS_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET1_MDC_ALT0_ENET1_MDC = 0,
+ IMX_IOMUXC_ENET1_MDC_ALT1_ENET2_MDC = 1,
+ IMX_IOMUXC_ENET1_MDC_ALT2_AUD3_RXFS = 2,
+ IMX_IOMUXC_ENET1_MDC_ALT3_XTALOSC_REF_CLK_24M = 3,
+ IMX_IOMUXC_ENET1_MDC_ALT4_EPIT2_OUT = 4,
+ IMX_IOMUXC_ENET1_MDC_ALT5_GPIO2_IO02 = 5,
+ IMX_IOMUXC_ENET1_MDC_ALT6_USB_OTG1_PWR = 6,
+ IMX_IOMUXC_ENET1_MDC_ALT7_PWM7_OUT = 7,
+} IMX_IOMUXC_ENET1_MDC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET1_MDIO_ALT0_ENET1_MDIO = 0,
+ IMX_IOMUXC_ENET1_MDIO_ALT1_ENET2_MDIO = 1,
+ IMX_IOMUXC_ENET1_MDIO_ALT2_AUDIO_CLK_OUT = 2,
+ IMX_IOMUXC_ENET1_MDIO_ALT4_EPIT1_OUT = 4,
+ IMX_IOMUXC_ENET1_MDIO_ALT5_GPIO2_IO03 = 5,
+ IMX_IOMUXC_ENET1_MDIO_ALT6_USB_OTG1_OC = 6,
+ IMX_IOMUXC_ENET1_MDIO_ALT7_PWM8_OUT = 7,
+} IMX_IOMUXC_ENET1_MDIO_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET1_RX_CLK_ALT0_ENET1_RX_CLK = 0,
+ IMX_IOMUXC_ENET1_RX_CLK_ALT1_ENET1_REF_CLK_25M = 1,
+ IMX_IOMUXC_ENET1_RX_CLK_ALT2_AUD4_TXFS = 2,
+ IMX_IOMUXC_ENET1_RX_CLK_ALT3_UART1_DSR_B = 3,
+ IMX_IOMUXC_ENET1_RX_CLK_ALT4_SPDIF_OUT = 4,
+ IMX_IOMUXC_ENET1_RX_CLK_ALT5_GPIO2_IO04 = 5,
+ IMX_IOMUXC_ENET1_RX_CLK_ALT6_CSI2_DATA21 = 6,
+ IMX_IOMUXC_ENET1_RX_CLK_ALT7_LCD2_DATA18 = 7,
+} IMX_IOMUXC_ENET1_RX_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET1_TX_CLK_ALT0_ENET1_TX_CLK = 0,
+ IMX_IOMUXC_ENET1_TX_CLK_ALT1_ENET1_REF_CLK1 = 1,
+ IMX_IOMUXC_ENET1_TX_CLK_ALT2_AUD4_RXD = 2,
+ IMX_IOMUXC_ENET1_TX_CLK_ALT3_UART1_DTR_B = 3,
+ IMX_IOMUXC_ENET1_TX_CLK_ALT4_SPDIF_SR_CLK = 4,
+ IMX_IOMUXC_ENET1_TX_CLK_ALT5_GPIO2_IO05 = 5,
+ IMX_IOMUXC_ENET1_TX_CLK_ALT6_CSI2_DATA20 = 6,
+ IMX_IOMUXC_ENET1_TX_CLK_ALT7_LCD2_DATA19 = 7,
+} IMX_IOMUXC_ENET1_TX_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET2_COL_ALT0_ENET2_COL = 0,
+ IMX_IOMUXC_ENET2_COL_ALT1_ENET1_MDC = 1,
+ IMX_IOMUXC_ENET2_COL_ALT2_AUD4_RXC = 2,
+ IMX_IOMUXC_ENET2_COL_ALT3_UART1_RX_DATA = 3,
+ IMX_IOMUXC_ENET2_COL_ALT4_SPDIF_IN = 4,
+ IMX_IOMUXC_ENET2_COL_ALT5_GPIO2_IO06 = 5,
+ IMX_IOMUXC_ENET2_COL_ALT6_USB_OTG1_ID = 6,
+ IMX_IOMUXC_ENET2_COL_ALT7_LCD2_DATA20 = 7,
+} IMX_IOMUXC_ENET2_COL_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET2_CRS_ALT0_ENET2_CRS = 0,
+ IMX_IOMUXC_ENET2_CRS_ALT1_ENET1_MDIO = 1,
+ IMX_IOMUXC_ENET2_CRS_ALT2_AUD4_RXFS = 2,
+ IMX_IOMUXC_ENET2_CRS_ALT3_UART1_TX_DATA = 3,
+ IMX_IOMUXC_ENET2_CRS_ALT4_MLB_SIG = 4,
+ IMX_IOMUXC_ENET2_CRS_ALT5_GPIO2_IO07 = 5,
+ IMX_IOMUXC_ENET2_CRS_ALT6_USB_OTG2_ID = 6,
+ IMX_IOMUXC_ENET2_CRS_ALT7_LCD2_DATA21 = 7,
+} IMX_IOMUXC_ENET2_CRS_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET2_RX_CLK_ALT0_ENET2_RX_CLK = 0,
+ IMX_IOMUXC_ENET2_RX_CLK_ALT1_ENET2_REF_CLK_25M = 1,
+ IMX_IOMUXC_ENET2_RX_CLK_ALT2_I2C3_SCL = 2,
+ IMX_IOMUXC_ENET2_RX_CLK_ALT3_UART1_RTS_B = 3,
+ IMX_IOMUXC_ENET2_RX_CLK_ALT4_MLB_DATA = 4,
+ IMX_IOMUXC_ENET2_RX_CLK_ALT5_GPIO2_IO08 = 5,
+ IMX_IOMUXC_ENET2_RX_CLK_ALT6_USB_OTG2_OC = 6,
+ IMX_IOMUXC_ENET2_RX_CLK_ALT7_LCD2_DATA22 = 7,
+} IMX_IOMUXC_ENET2_RX_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_ENET2_TX_CLK_ALT0_ENET2_TX_CLK = 0,
+ IMX_IOMUXC_ENET2_TX_CLK_ALT1_ENET2_REF_CLK2 = 1,
+ IMX_IOMUXC_ENET2_TX_CLK_ALT2_I2C3_SDA = 2,
+ IMX_IOMUXC_ENET2_TX_CLK_ALT3_UART1_CTS_B = 3,
+ IMX_IOMUXC_ENET2_TX_CLK_ALT4_MLB_CLK = 4,
+ IMX_IOMUXC_ENET2_TX_CLK_ALT5_GPIO2_IO09 = 5,
+ IMX_IOMUXC_ENET2_TX_CLK_ALT6_USB_OTG2_PWR = 6,
+ IMX_IOMUXC_ENET2_TX_CLK_ALT7_LCD2_DATA23 = 7,
+} IMX_IOMUXC_ENET2_TX_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_COL0_ALT0_KPP_COL0 = 0,
+ IMX_IOMUXC_KEY_COL0_ALT1_SD3_CD_B = 1,
+ IMX_IOMUXC_KEY_COL0_ALT2_UART6_RTS_B = 2,
+ IMX_IOMUXC_KEY_COL0_ALT3_ECSPI1_SCLK = 3,
+ IMX_IOMUXC_KEY_COL0_ALT4_AUD5_TXC = 4,
+ IMX_IOMUXC_KEY_COL0_ALT5_GPIO2_IO10 = 5,
+ IMX_IOMUXC_KEY_COL0_ALT6_SDMA_EXT_EVENT1 = 6,
+ IMX_IOMUXC_KEY_COL0_ALT7_SAI2_TX_BCLK = 7,
+} IMX_IOMUXC_KEY_COL0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_COL1_ALT0_KPP_COL1 = 0,
+ IMX_IOMUXC_KEY_COL1_ALT1_SD3_RESET_B = 1,
+ IMX_IOMUXC_KEY_COL1_ALT2_UART6_TX_DATA = 2,
+ IMX_IOMUXC_KEY_COL1_ALT3_ECSPI1_MISO = 3,
+ IMX_IOMUXC_KEY_COL1_ALT4_AUD5_TXFS = 4,
+ IMX_IOMUXC_KEY_COL1_ALT5_GPIO2_IO11 = 5,
+ IMX_IOMUXC_KEY_COL1_ALT6_SD3_RESET = 6,
+ IMX_IOMUXC_KEY_COL1_ALT7_SAI2_TX_SYNC = 7,
+} IMX_IOMUXC_KEY_COL1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_COL2_ALT0_KPP_COL2 = 0,
+ IMX_IOMUXC_KEY_COL2_ALT1_SD4_CD_B = 1,
+ IMX_IOMUXC_KEY_COL2_ALT2_UART5_RTS_B = 2,
+ IMX_IOMUXC_KEY_COL2_ALT3_CAN1_TX = 3,
+ IMX_IOMUXC_KEY_COL2_ALT5_GPIO2_IO12 = 5,
+ IMX_IOMUXC_KEY_COL2_ALT6_EIM_DATA30 = 6,
+ IMX_IOMUXC_KEY_COL2_ALT7_ECSPI1_RDY = 7,
+} IMX_IOMUXC_KEY_COL2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_COL3_ALT0_KPP_COL3 = 0,
+ IMX_IOMUXC_KEY_COL3_ALT1_SD4_LCTL = 1,
+ IMX_IOMUXC_KEY_COL3_ALT2_UART5_TX_DATA = 2,
+ IMX_IOMUXC_KEY_COL3_ALT3_CAN2_TX = 3,
+ IMX_IOMUXC_KEY_COL3_ALT5_GPIO2_IO13 = 5,
+ IMX_IOMUXC_KEY_COL3_ALT6_EIM_DATA28 = 6,
+ IMX_IOMUXC_KEY_COL3_ALT7_ECSPI1_SS2 = 7,
+} IMX_IOMUXC_KEY_COL3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_COL4_ALT0_KPP_COL4 = 0,
+ IMX_IOMUXC_KEY_COL4_ALT1_ENET2_MDC = 1,
+ IMX_IOMUXC_KEY_COL4_ALT2_I2C3_SCL = 2,
+ IMX_IOMUXC_KEY_COL4_ALT3_SD2_LCTL = 3,
+ IMX_IOMUXC_KEY_COL4_ALT4_AUD5_RXC = 4,
+ IMX_IOMUXC_KEY_COL4_ALT5_GPIO2_IO14 = 5,
+ IMX_IOMUXC_KEY_COL4_ALT6_EIM_CRE = 6,
+ IMX_IOMUXC_KEY_COL4_ALT7_SAI2_RX_BCLK = 7,
+} IMX_IOMUXC_KEY_COL4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_ROW0_ALT0_KPP_ROW0 = 0,
+ IMX_IOMUXC_KEY_ROW0_ALT1_SD3_WP = 1,
+ IMX_IOMUXC_KEY_ROW0_ALT2_UART6_CTS_B = 2,
+ IMX_IOMUXC_KEY_ROW0_ALT3_ECSPI1_MOSI = 3,
+ IMX_IOMUXC_KEY_ROW0_ALT4_AUD5_TXD = 4,
+ IMX_IOMUXC_KEY_ROW0_ALT5_GPIO2_IO15 = 5,
+ IMX_IOMUXC_KEY_ROW0_ALT6_SDMA_EXT_EVENT0 = 6,
+ IMX_IOMUXC_KEY_ROW0_ALT7_SAI2_TX_DATA0 = 7,
+} IMX_IOMUXC_KEY_ROW0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_ROW1_ALT0_KPP_ROW1 = 0,
+ IMX_IOMUXC_KEY_ROW1_ALT1_SD4_VSELECT = 1,
+ IMX_IOMUXC_KEY_ROW1_ALT2_UART6_RX_DATA = 2,
+ IMX_IOMUXC_KEY_ROW1_ALT3_ECSPI1_SS0 = 3,
+ IMX_IOMUXC_KEY_ROW1_ALT4_AUD5_RXD = 4,
+ IMX_IOMUXC_KEY_ROW1_ALT5_GPIO2_IO16 = 5,
+ IMX_IOMUXC_KEY_ROW1_ALT6_EIM_DATA31 = 6,
+ IMX_IOMUXC_KEY_ROW1_ALT7_SAI2_RX_DATA0 = 7,
+} IMX_IOMUXC_KEY_ROW1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_ROW2_ALT0_KPP_ROW2 = 0,
+ IMX_IOMUXC_KEY_ROW2_ALT1_SD4_WP = 1,
+ IMX_IOMUXC_KEY_ROW2_ALT2_UART5_CTS_B = 2,
+ IMX_IOMUXC_KEY_ROW2_ALT3_CAN1_RX = 3,
+ IMX_IOMUXC_KEY_ROW2_ALT5_GPIO2_IO17 = 5,
+ IMX_IOMUXC_KEY_ROW2_ALT6_EIM_DATA29 = 6,
+ IMX_IOMUXC_KEY_ROW2_ALT7_ECSPI1_SS3 = 7,
+} IMX_IOMUXC_KEY_ROW2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_ROW3_ALT0_KPP_ROW3 = 0,
+ IMX_IOMUXC_KEY_ROW3_ALT1_SD3_LCTL = 1,
+ IMX_IOMUXC_KEY_ROW3_ALT2_UART5_RX_DATA = 2,
+ IMX_IOMUXC_KEY_ROW3_ALT3_CAN2_RX = 3,
+ IMX_IOMUXC_KEY_ROW3_ALT5_GPIO2_IO18 = 5,
+ IMX_IOMUXC_KEY_ROW3_ALT6_EIM_DTACK_B = 6,
+ IMX_IOMUXC_KEY_ROW3_ALT7_ECSPI1_SS1 = 7,
+} IMX_IOMUXC_KEY_ROW3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_KEY_ROW4_ALT0_KPP_ROW4 = 0,
+ IMX_IOMUXC_KEY_ROW4_ALT1_ENET2_MDIO = 1,
+ IMX_IOMUXC_KEY_ROW4_ALT2_I2C3_SDA = 2,
+ IMX_IOMUXC_KEY_ROW4_ALT3_SD1_LCTL = 3,
+ IMX_IOMUXC_KEY_ROW4_ALT4_AUD5_RXFS = 4,
+ IMX_IOMUXC_KEY_ROW4_ALT5_GPIO2_IO19 = 5,
+ IMX_IOMUXC_KEY_ROW4_ALT6_EIM_ACLK_FREERUN = 6,
+ IMX_IOMUXC_KEY_ROW4_ALT7_SAI2_RX_SYNC = 7,
+} IMX_IOMUXC_KEY_ROW4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_CLK_ALT0_LCD1_CLK = 0,
+ IMX_IOMUXC_LCD1_CLK_ALT1_LCD1_WR_RWN = 1,
+ IMX_IOMUXC_LCD1_CLK_ALT2_AUD3_RXC = 2,
+ IMX_IOMUXC_LCD1_CLK_ALT3_ENET1_1588_EVENT2_IN = 3,
+ IMX_IOMUXC_LCD1_CLK_ALT4_CSI1_DATA16 = 4,
+ IMX_IOMUXC_LCD1_CLK_ALT5_GPIO3_IO00 = 5,
+ IMX_IOMUXC_LCD1_CLK_ALT6_SD1_WP = 6,
+} IMX_IOMUXC_LCD1_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA00_ALT0_LCD1_DATA00 = 0,
+ IMX_IOMUXC_LCD1_DATA00_ALT1_EIM_CS1_B = 1,
+ IMX_IOMUXC_LCD1_DATA00_ALT2_ARM_M4_TRACE0 = 2,
+ IMX_IOMUXC_LCD1_DATA00_ALT3_ARM_A9_TRACE00 = 3,
+ IMX_IOMUXC_LCD1_DATA00_ALT4_CSI1_DATA20 = 4,
+ IMX_IOMUXC_LCD1_DATA00_ALT5_GPIO3_IO01 = 5,
+ IMX_IOMUXC_LCD1_DATA00_ALT6_SRC_BOOT_CFG00 = 6,
+} IMX_IOMUXC_LCD1_DATA00_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA01_ALT0_LCD1_DATA01 = 0,
+ IMX_IOMUXC_LCD1_DATA01_ALT1_EIM_CS2_B = 1,
+ IMX_IOMUXC_LCD1_DATA01_ALT2_ARM_M4_TRACE1 = 2,
+ IMX_IOMUXC_LCD1_DATA01_ALT3_ARM_A9_TRACE01 = 3,
+ IMX_IOMUXC_LCD1_DATA01_ALT4_CSI1_DATA21 = 4,
+ IMX_IOMUXC_LCD1_DATA01_ALT5_GPIO3_IO02 = 5,
+ IMX_IOMUXC_LCD1_DATA01_ALT6_SRC_BOOT_CFG01 = 6,
+} IMX_IOMUXC_LCD1_DATA01_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA02_ALT0_LCD1_DATA02 = 0,
+ IMX_IOMUXC_LCD1_DATA02_ALT1_EIM_CS3_B = 1,
+ IMX_IOMUXC_LCD1_DATA02_ALT2_ARM_M4_TRACE2 = 2,
+ IMX_IOMUXC_LCD1_DATA02_ALT3_ARM_A9_TRACE02 = 3,
+ IMX_IOMUXC_LCD1_DATA02_ALT4_CSI1_DATA22 = 4,
+ IMX_IOMUXC_LCD1_DATA02_ALT5_GPIO3_IO03 = 5,
+ IMX_IOMUXC_LCD1_DATA02_ALT6_SRC_BOOT_CFG02 = 6,
+} IMX_IOMUXC_LCD1_DATA02_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA03_ALT0_LCD1_DATA03 = 0,
+ IMX_IOMUXC_LCD1_DATA03_ALT1_EIM_ADDR24 = 1,
+ IMX_IOMUXC_LCD1_DATA03_ALT2_ARM_M4_TRACE3 = 2,
+ IMX_IOMUXC_LCD1_DATA03_ALT3_ARM_A9_TRACE03 = 3,
+ IMX_IOMUXC_LCD1_DATA03_ALT4_CSI1_DATA23 = 4,
+ IMX_IOMUXC_LCD1_DATA03_ALT5_GPIO3_IO04 = 5,
+ IMX_IOMUXC_LCD1_DATA03_ALT6_SRC_BOOT_CFG03 = 6,
+} IMX_IOMUXC_LCD1_DATA03_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA04_ALT0_LCD1_DATA04 = 0,
+ IMX_IOMUXC_LCD1_DATA04_ALT1_EIM_ADDR25 = 1,
+ IMX_IOMUXC_LCD1_DATA04_ALT3_ARM_A9_TRACE04 = 3,
+ IMX_IOMUXC_LCD1_DATA04_ALT4_CSI1_VSYNC = 4,
+ IMX_IOMUXC_LCD1_DATA04_ALT5_GPIO3_IO05 = 5,
+ IMX_IOMUXC_LCD1_DATA04_ALT6_SRC_BOOT_CFG04 = 6,
+} IMX_IOMUXC_LCD1_DATA04_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA05_ALT0_LCD1_DATA05 = 0,
+ IMX_IOMUXC_LCD1_DATA05_ALT1_EIM_ADDR26 = 1,
+ IMX_IOMUXC_LCD1_DATA05_ALT3_ARM_A9_TRACE05 = 3,
+ IMX_IOMUXC_LCD1_DATA05_ALT4_CSI1_HSYNC = 4,
+ IMX_IOMUXC_LCD1_DATA05_ALT5_GPIO3_IO06 = 5,
+ IMX_IOMUXC_LCD1_DATA05_ALT6_SRC_BOOT_CFG05 = 6,
+} IMX_IOMUXC_LCD1_DATA05_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA06_ALT0_LCD1_DATA06 = 0,
+ IMX_IOMUXC_LCD1_DATA06_ALT1_EIM_EB2_B = 1,
+ IMX_IOMUXC_LCD1_DATA06_ALT3_ARM_A9_TRACE06 = 3,
+ IMX_IOMUXC_LCD1_DATA06_ALT4_CSI1_PIXCLK = 4,
+ IMX_IOMUXC_LCD1_DATA06_ALT5_GPIO3_IO07 = 5,
+ IMX_IOMUXC_LCD1_DATA06_ALT6_SRC_BOOT_CFG06 = 6,
+} IMX_IOMUXC_LCD1_DATA06_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA07_ALT0_LCD1_DATA07 = 0,
+ IMX_IOMUXC_LCD1_DATA07_ALT1_EIM_EB3_B = 1,
+ IMX_IOMUXC_LCD1_DATA07_ALT3_ARM_A9_TRACE07 = 3,
+ IMX_IOMUXC_LCD1_DATA07_ALT4_CSI1_MCLK = 4,
+ IMX_IOMUXC_LCD1_DATA07_ALT5_GPIO3_IO08 = 5,
+ IMX_IOMUXC_LCD1_DATA07_ALT6_SRC_BOOT_CFG07 = 6,
+} IMX_IOMUXC_LCD1_DATA07_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA08_ALT0_LCD1_DATA08 = 0,
+ IMX_IOMUXC_LCD1_DATA08_ALT1_EIM_AD08 = 1,
+ IMX_IOMUXC_LCD1_DATA08_ALT3_ARM_A9_TRACE08 = 3,
+ IMX_IOMUXC_LCD1_DATA08_ALT4_CSI1_DATA09 = 4,
+ IMX_IOMUXC_LCD1_DATA08_ALT5_GPIO3_IO09 = 5,
+ IMX_IOMUXC_LCD1_DATA08_ALT6_SRC_BOOT_CFG08 = 6,
+} IMX_IOMUXC_LCD1_DATA08_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA09_ALT0_LCD1_DATA09 = 0,
+ IMX_IOMUXC_LCD1_DATA09_ALT1_EIM_AD09 = 1,
+ IMX_IOMUXC_LCD1_DATA09_ALT3_ARM_A9_TRACE09 = 3,
+ IMX_IOMUXC_LCD1_DATA09_ALT4_CSI1_DATA08 = 4,
+ IMX_IOMUXC_LCD1_DATA09_ALT5_GPIO3_IO10 = 5,
+ IMX_IOMUXC_LCD1_DATA09_ALT6_SRC_BOOT_CFG09 = 6,
+} IMX_IOMUXC_LCD1_DATA09_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA10_ALT0_LCD1_DATA10 = 0,
+ IMX_IOMUXC_LCD1_DATA10_ALT1_EIM_AD10 = 1,
+ IMX_IOMUXC_LCD1_DATA10_ALT3_ARM_A9_TRACE10 = 3,
+ IMX_IOMUXC_LCD1_DATA10_ALT4_CSI1_DATA07 = 4,
+ IMX_IOMUXC_LCD1_DATA10_ALT5_GPIO3_IO11 = 5,
+ IMX_IOMUXC_LCD1_DATA10_ALT6_SRC_BOOT_CFG10 = 6,
+} IMX_IOMUXC_LCD1_DATA10_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA11_ALT0_LCD1_DATA11 = 0,
+ IMX_IOMUXC_LCD1_DATA11_ALT1_EIM_AD11 = 1,
+ IMX_IOMUXC_LCD1_DATA11_ALT3_ARM_A9_TRACE11 = 3,
+ IMX_IOMUXC_LCD1_DATA11_ALT4_CSI1_DATA06 = 4,
+ IMX_IOMUXC_LCD1_DATA11_ALT5_GPIO3_IO12 = 5,
+ IMX_IOMUXC_LCD1_DATA11_ALT6_SRC_BOOT_CFG11 = 6,
+} IMX_IOMUXC_LCD1_DATA11_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA12_ALT0_LCD1_DATA12 = 0,
+ IMX_IOMUXC_LCD1_DATA12_ALT1_EIM_AD12 = 1,
+ IMX_IOMUXC_LCD1_DATA12_ALT3_ARM_A9_TRACE12 = 3,
+ IMX_IOMUXC_LCD1_DATA12_ALT4_CSI1_DATA05 = 4,
+ IMX_IOMUXC_LCD1_DATA12_ALT5_GPIO3_IO13 = 5,
+ IMX_IOMUXC_LCD1_DATA12_ALT6_SRC_BOOT_CFG12 = 6,
+} IMX_IOMUXC_LCD1_DATA12_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA13_ALT0_LCD1_DATA13 = 0,
+ IMX_IOMUXC_LCD1_DATA13_ALT1_EIM_AD13 = 1,
+ IMX_IOMUXC_LCD1_DATA13_ALT3_ARM_A9_TRACE13 = 3,
+ IMX_IOMUXC_LCD1_DATA13_ALT4_CSI1_DATA04 = 4,
+ IMX_IOMUXC_LCD1_DATA13_ALT5_GPIO3_IO14 = 5,
+ IMX_IOMUXC_LCD1_DATA13_ALT6_SRC_BOOT_CFG13 = 6,
+} IMX_IOMUXC_LCD1_DATA13_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA14_ALT0_LCD1_DATA14 = 0,
+ IMX_IOMUXC_LCD1_DATA14_ALT1_EIM_AD14 = 1,
+ IMX_IOMUXC_LCD1_DATA14_ALT3_ARM_A9_TRACE14 = 3,
+ IMX_IOMUXC_LCD1_DATA14_ALT4_CSI1_DATA03 = 4,
+ IMX_IOMUXC_LCD1_DATA14_ALT5_GPIO3_IO15 = 5,
+ IMX_IOMUXC_LCD1_DATA14_ALT6_SRC_BOOT_CFG14 = 6,
+} IMX_IOMUXC_LCD1_DATA14_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA15_ALT0_LCD1_DATA15 = 0,
+ IMX_IOMUXC_LCD1_DATA15_ALT1_EIM_AD15 = 1,
+ IMX_IOMUXC_LCD1_DATA15_ALT3_ARM_A9_TRACE15 = 3,
+ IMX_IOMUXC_LCD1_DATA15_ALT4_CSI1_DATA02 = 4,
+ IMX_IOMUXC_LCD1_DATA15_ALT5_GPIO3_IO16 = 5,
+ IMX_IOMUXC_LCD1_DATA15_ALT6_SRC_BOOT_CFG15 = 6,
+} IMX_IOMUXC_LCD1_DATA15_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA16_ALT0_LCD1_DATA16 = 0,
+ IMX_IOMUXC_LCD1_DATA16_ALT1_EIM_ADDR16 = 1,
+ IMX_IOMUXC_LCD1_DATA16_ALT2_ARM_M4_TRACE_CLK = 2,
+ IMX_IOMUXC_LCD1_DATA16_ALT3_ARM_A9_TRACE_CLK = 3,
+ IMX_IOMUXC_LCD1_DATA16_ALT4_CSI1_DATA01 = 4,
+ IMX_IOMUXC_LCD1_DATA16_ALT5_GPIO3_IO17 = 5,
+ IMX_IOMUXC_LCD1_DATA16_ALT6_SRC_BOOT_CFG24 = 6,
+} IMX_IOMUXC_LCD1_DATA16_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA17_ALT0_LCD1_DATA17 = 0,
+ IMX_IOMUXC_LCD1_DATA17_ALT1_EIM_ADDR17 = 1,
+ IMX_IOMUXC_LCD1_DATA17_ALT3_ARM_A9_TRACE_CTL = 3,
+ IMX_IOMUXC_LCD1_DATA17_ALT4_CSI1_DATA00 = 4,
+ IMX_IOMUXC_LCD1_DATA17_ALT5_GPIO3_IO18 = 5,
+ IMX_IOMUXC_LCD1_DATA17_ALT6_SRC_BOOT_CFG25 = 6,
+} IMX_IOMUXC_LCD1_DATA17_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA18_ALT0_LCD1_DATA18 = 0,
+ IMX_IOMUXC_LCD1_DATA18_ALT1_EIM_ADDR18 = 1,
+ IMX_IOMUXC_LCD1_DATA18_ALT2_ARM_M4_EVENTO = 2,
+ IMX_IOMUXC_LCD1_DATA18_ALT3_ARM_A9_EVENTO = 3,
+ IMX_IOMUXC_LCD1_DATA18_ALT4_CSI1_DATA15 = 4,
+ IMX_IOMUXC_LCD1_DATA18_ALT5_GPIO3_IO19 = 5,
+ IMX_IOMUXC_LCD1_DATA18_ALT6_SRC_BOOT_CFG26 = 6,
+} IMX_IOMUXC_LCD1_DATA18_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA19_ALT0_LCD1_DATA19 = 0,
+ IMX_IOMUXC_LCD1_DATA19_ALT1_EIM_ADDR19 = 1,
+ IMX_IOMUXC_LCD1_DATA19_ALT2_ARM_M4_TRACE_SWO = 2,
+ IMX_IOMUXC_LCD1_DATA19_ALT4_CSI1_DATA14 = 4,
+ IMX_IOMUXC_LCD1_DATA19_ALT5_GPIO3_IO20 = 5,
+ IMX_IOMUXC_LCD1_DATA19_ALT6_SRC_BOOT_CFG27 = 6,
+} IMX_IOMUXC_LCD1_DATA19_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA20_ALT0_LCD1_DATA20 = 0,
+ IMX_IOMUXC_LCD1_DATA20_ALT1_EIM_ADDR20 = 1,
+ IMX_IOMUXC_LCD1_DATA20_ALT2_PWM8_OUT = 2,
+ IMX_IOMUXC_LCD1_DATA20_ALT3_ENET1_1588_EVENT2_OUT = 3,
+ IMX_IOMUXC_LCD1_DATA20_ALT4_CSI1_DATA13 = 4,
+ IMX_IOMUXC_LCD1_DATA20_ALT5_GPIO3_IO21 = 5,
+ IMX_IOMUXC_LCD1_DATA20_ALT6_SRC_BOOT_CFG28 = 6,
+} IMX_IOMUXC_LCD1_DATA20_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA21_ALT0_LCD1_DATA21 = 0,
+ IMX_IOMUXC_LCD1_DATA21_ALT1_EIM_ADDR21 = 1,
+ IMX_IOMUXC_LCD1_DATA21_ALT2_PWM7_OUT = 2,
+ IMX_IOMUXC_LCD1_DATA21_ALT3_ENET1_1588_EVENT3_OUT = 3,
+ IMX_IOMUXC_LCD1_DATA21_ALT4_CSI1_DATA12 = 4,
+ IMX_IOMUXC_LCD1_DATA21_ALT5_GPIO3_IO22 = 5,
+ IMX_IOMUXC_LCD1_DATA21_ALT6_SRC_BOOT_CFG29 = 6,
+} IMX_IOMUXC_LCD1_DATA21_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA22_ALT0_LCD1_DATA22 = 0,
+ IMX_IOMUXC_LCD1_DATA22_ALT1_EIM_ADDR22 = 1,
+ IMX_IOMUXC_LCD1_DATA22_ALT2_PWM6_OUT = 2,
+ IMX_IOMUXC_LCD1_DATA22_ALT3_ENET2_1588_EVENT2_OUT = 3,
+ IMX_IOMUXC_LCD1_DATA22_ALT4_CSI1_DATA11 = 4,
+ IMX_IOMUXC_LCD1_DATA22_ALT5_GPIO3_IO23 = 5,
+ IMX_IOMUXC_LCD1_DATA22_ALT6_SRC_BOOT_CFG30 = 6,
+} IMX_IOMUXC_LCD1_DATA22_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_DATA23_ALT0_LCD1_DATA23 = 0,
+ IMX_IOMUXC_LCD1_DATA23_ALT1_EIM_ADDR23 = 1,
+ IMX_IOMUXC_LCD1_DATA23_ALT2_PWM5_OUT = 2,
+ IMX_IOMUXC_LCD1_DATA23_ALT3_ENET2_1588_EVENT3_OUT = 3,
+ IMX_IOMUXC_LCD1_DATA23_ALT4_CSI1_DATA10 = 4,
+ IMX_IOMUXC_LCD1_DATA23_ALT5_GPIO3_IO24 = 5,
+ IMX_IOMUXC_LCD1_DATA23_ALT6_SRC_BOOT_CFG31 = 6,
+} IMX_IOMUXC_LCD1_DATA23_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_ENABLE_ALT0_LCD1_ENABLE = 0,
+ IMX_IOMUXC_LCD1_ENABLE_ALT1_LCD1_RD_E = 1,
+ IMX_IOMUXC_LCD1_ENABLE_ALT2_AUD3_TXC = 2,
+ IMX_IOMUXC_LCD1_ENABLE_ALT3_ENET1_1588_EVENT3_IN = 3,
+ IMX_IOMUXC_LCD1_ENABLE_ALT4_CSI1_DATA17 = 4,
+ IMX_IOMUXC_LCD1_ENABLE_ALT5_GPIO3_IO25 = 5,
+ IMX_IOMUXC_LCD1_ENABLE_ALT6_SD1_CD_B = 6,
+} IMX_IOMUXC_LCD1_ENABLE_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_HSYNC_ALT0_LCD1_HSYNC = 0,
+ IMX_IOMUXC_LCD1_HSYNC_ALT1_LCD1_RS = 1,
+ IMX_IOMUXC_LCD1_HSYNC_ALT2_AUD3_TXD = 2,
+ IMX_IOMUXC_LCD1_HSYNC_ALT3_ENET2_1588_EVENT2_IN = 3,
+ IMX_IOMUXC_LCD1_HSYNC_ALT4_CSI1_DATA18 = 4,
+ IMX_IOMUXC_LCD1_HSYNC_ALT5_GPIO3_IO26 = 5,
+ IMX_IOMUXC_LCD1_HSYNC_ALT6_SD2_WP = 6,
+} IMX_IOMUXC_LCD1_HSYNC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_RESET_ALT0_LCD1_RESET = 0,
+ IMX_IOMUXC_LCD1_RESET_ALT1_LCD1_CS = 1,
+ IMX_IOMUXC_LCD1_RESET_ALT2_AUD3_RXD = 2,
+ IMX_IOMUXC_LCD1_RESET_ALT3_ARM_A9_EVENTI = 3,
+ IMX_IOMUXC_LCD1_RESET_ALT4_ARM_M4_EVENTI = 4,
+ IMX_IOMUXC_LCD1_RESET_ALT5_GPIO3_IO27 = 5,
+ IMX_IOMUXC_LCD1_RESET_ALT6_CCM_PMIC_READY = 6,
+} IMX_IOMUXC_LCD1_RESET_ALT;
+
+typedef enum {
+ IMX_IOMUXC_LCD1_VSYNC_ALT0_LCD1_VSYNC = 0,
+ IMX_IOMUXC_LCD1_VSYNC_ALT1_LCD1_BUSY = 1,
+ IMX_IOMUXC_LCD1_VSYNC_ALT2_AUD3_TXFS = 2,
+ IMX_IOMUXC_LCD1_VSYNC_ALT3_ENET2_1588_EVENT3_IN = 3,
+ IMX_IOMUXC_LCD1_VSYNC_ALT4_CSI1_DATA19 = 4,
+ IMX_IOMUXC_LCD1_VSYNC_ALT5_GPIO3_IO28 = 5,
+ IMX_IOMUXC_LCD1_VSYNC_ALT6_SD2_CD_B = 6,
+} IMX_IOMUXC_LCD1_VSYNC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_ALE_ALT0_NAND_ALE = 0,
+ IMX_IOMUXC_NAND_ALE_ALT1_I2C3_SDA = 1,
+ IMX_IOMUXC_NAND_ALE_ALT2_QSPI2A_SS0_B = 2,
+ IMX_IOMUXC_NAND_ALE_ALT3_ECSPI2_SS0 = 3,
+ IMX_IOMUXC_NAND_ALE_ALT4_ESAI_TX3_RX2 = 4,
+ IMX_IOMUXC_NAND_ALE_ALT5_GPIO4_IO00 = 5,
+ IMX_IOMUXC_NAND_ALE_ALT6_EIM_CS0_B = 6,
+} IMX_IOMUXC_NAND_ALE_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_CE0_B_ALT0_NAND_CE0_B = 0,
+ IMX_IOMUXC_NAND_CE0_B_ALT1_SD2_VSELECT = 1,
+ IMX_IOMUXC_NAND_CE0_B_ALT2_QSPI2A_DATA2 = 2,
+ IMX_IOMUXC_NAND_CE0_B_ALT3_AUD4_TXC = 3,
+ IMX_IOMUXC_NAND_CE0_B_ALT4_ESAI_TX_CLK = 4,
+ IMX_IOMUXC_NAND_CE0_B_ALT5_GPIO4_IO01 = 5,
+ IMX_IOMUXC_NAND_CE0_B_ALT6_EIM_LBA_B = 6,
+} IMX_IOMUXC_NAND_CE0_B_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_CE1_B_ALT0_NAND_CE1_B = 0,
+ IMX_IOMUXC_NAND_CE1_B_ALT1_SD3_RESET_B = 1,
+ IMX_IOMUXC_NAND_CE1_B_ALT2_QSPI2A_DATA3 = 2,
+ IMX_IOMUXC_NAND_CE1_B_ALT3_AUD4_TXD = 3,
+ IMX_IOMUXC_NAND_CE1_B_ALT4_ESAI_TX0 = 4,
+ IMX_IOMUXC_NAND_CE1_B_ALT5_GPIO4_IO02 = 5,
+ IMX_IOMUXC_NAND_CE1_B_ALT6_EIM_OE = 6,
+} IMX_IOMUXC_NAND_CE1_B_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_CLE_ALT0_NAND_CLE = 0,
+ IMX_IOMUXC_NAND_CLE_ALT1_I2C3_SCL = 1,
+ IMX_IOMUXC_NAND_CLE_ALT2_QSPI2A_SCLK = 2,
+ IMX_IOMUXC_NAND_CLE_ALT3_ECSPI2_SCLK = 3,
+ IMX_IOMUXC_NAND_CLE_ALT4_ESAI_TX2_RX3 = 4,
+ IMX_IOMUXC_NAND_CLE_ALT5_GPIO4_IO03 = 5,
+ IMX_IOMUXC_NAND_CLE_ALT6_EIM_BCLK = 6,
+} IMX_IOMUXC_NAND_CLE_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_DATA00_ALT0_NAND_DATA00 = 0,
+ IMX_IOMUXC_NAND_DATA00_ALT1_SD1_DATA4 = 1,
+ IMX_IOMUXC_NAND_DATA00_ALT2_QSPI2B_DATA1 = 2,
+ IMX_IOMUXC_NAND_DATA00_ALT3_ECSPI5_MISO = 3,
+ IMX_IOMUXC_NAND_DATA00_ALT4_ESAI_RX_CLK = 4,
+ IMX_IOMUXC_NAND_DATA00_ALT5_GPIO4_IO04 = 5,
+ IMX_IOMUXC_NAND_DATA00_ALT6_EIM_AD00 = 6,
+} IMX_IOMUXC_NAND_DATA00_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_DATA01_ALT0_NAND_DATA01 = 0,
+ IMX_IOMUXC_NAND_DATA01_ALT1_SD1_DATA5 = 1,
+ IMX_IOMUXC_NAND_DATA01_ALT2_QSPI2B_DATA0 = 2,
+ IMX_IOMUXC_NAND_DATA01_ALT3_ECSPI5_MOSI = 3,
+ IMX_IOMUXC_NAND_DATA01_ALT4_ESAI_RX_FS = 4,
+ IMX_IOMUXC_NAND_DATA01_ALT5_GPIO4_IO05 = 5,
+ IMX_IOMUXC_NAND_DATA01_ALT6_EIM_AD01 = 6,
+} IMX_IOMUXC_NAND_DATA01_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_DATA02_ALT0_NAND_DATA02 = 0,
+ IMX_IOMUXC_NAND_DATA02_ALT1_SD1_DATA6 = 1,
+ IMX_IOMUXC_NAND_DATA02_ALT2_QSPI2B_SCLK = 2,
+ IMX_IOMUXC_NAND_DATA02_ALT3_ECSPI5_SCLK = 3,
+ IMX_IOMUXC_NAND_DATA02_ALT4_ESAI_TX_HF_CLK = 4,
+ IMX_IOMUXC_NAND_DATA02_ALT5_GPIO4_IO06 = 5,
+ IMX_IOMUXC_NAND_DATA02_ALT6_EIM_AD02 = 6,
+} IMX_IOMUXC_NAND_DATA02_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_DATA03_ALT0_NAND_DATA03 = 0,
+ IMX_IOMUXC_NAND_DATA03_ALT1_SD1_DATA7 = 1,
+ IMX_IOMUXC_NAND_DATA03_ALT2_QSPI2B_SS0_B = 2,
+ IMX_IOMUXC_NAND_DATA03_ALT3_ECSPI5_SS0 = 3,
+ IMX_IOMUXC_NAND_DATA03_ALT4_ESAI_RX_HF_CLK = 4,
+ IMX_IOMUXC_NAND_DATA03_ALT5_GPIO4_IO07 = 5,
+ IMX_IOMUXC_NAND_DATA03_ALT6_EIM_AD03 = 6,
+} IMX_IOMUXC_NAND_DATA03_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_DATA04_ALT0_NAND_DATA04 = 0,
+ IMX_IOMUXC_NAND_DATA04_ALT1_SD2_DATA4 = 1,
+ IMX_IOMUXC_NAND_DATA04_ALT2_QSPI2B_SS1_B = 2,
+ IMX_IOMUXC_NAND_DATA04_ALT3_UART3_RTS_B = 3,
+ IMX_IOMUXC_NAND_DATA04_ALT4_AUD4_RXFS = 4,
+ IMX_IOMUXC_NAND_DATA04_ALT5_GPIO4_IO08 = 5,
+ IMX_IOMUXC_NAND_DATA04_ALT6_EIM_AD04 = 6,
+} IMX_IOMUXC_NAND_DATA04_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_DATA05_ALT0_NAND_DATA05 = 0,
+ IMX_IOMUXC_NAND_DATA05_ALT1_SD2_DATA5 = 1,
+ IMX_IOMUXC_NAND_DATA05_ALT2_QSPI2B_DQS = 2,
+ IMX_IOMUXC_NAND_DATA05_ALT3_UART3_CTS_B = 3,
+ IMX_IOMUXC_NAND_DATA05_ALT4_AUD4_RXC = 4,
+ IMX_IOMUXC_NAND_DATA05_ALT5_GPIO4_IO09 = 5,
+ IMX_IOMUXC_NAND_DATA05_ALT6_EIM_AD05 = 6,
+} IMX_IOMUXC_NAND_DATA05_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_DATA06_ALT0_NAND_DATA06 = 0,
+ IMX_IOMUXC_NAND_DATA06_ALT1_SD2_DATA6 = 1,
+ IMX_IOMUXC_NAND_DATA06_ALT2_QSPI2A_SS1_B = 2,
+ IMX_IOMUXC_NAND_DATA06_ALT3_UART3_RX_DATA = 3,
+ IMX_IOMUXC_NAND_DATA06_ALT4_PWM3_OUT = 4,
+ IMX_IOMUXC_NAND_DATA06_ALT5_GPIO4_IO10 = 5,
+ IMX_IOMUXC_NAND_DATA06_ALT6_EIM_AD06 = 6,
+} IMX_IOMUXC_NAND_DATA06_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_DATA07_ALT0_NAND_DATA07 = 0,
+ IMX_IOMUXC_NAND_DATA07_ALT1_SD2_DATA7 = 1,
+ IMX_IOMUXC_NAND_DATA07_ALT2_QSPI2A_DQS = 2,
+ IMX_IOMUXC_NAND_DATA07_ALT3_UART3_TX_DATA = 3,
+ IMX_IOMUXC_NAND_DATA07_ALT4_PWM4_OUT = 4,
+ IMX_IOMUXC_NAND_DATA07_ALT5_GPIO4_IO11 = 5,
+ IMX_IOMUXC_NAND_DATA07_ALT6_EIM_AD07 = 6,
+} IMX_IOMUXC_NAND_DATA07_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_RE_B_ALT0_NAND_RE_B = 0,
+ IMX_IOMUXC_NAND_RE_B_ALT1_SD2_RESET_B = 1,
+ IMX_IOMUXC_NAND_RE_B_ALT2_QSPI2B_DATA3 = 2,
+ IMX_IOMUXC_NAND_RE_B_ALT3_AUD4_TXFS = 3,
+ IMX_IOMUXC_NAND_RE_B_ALT4_ESAI_TX_FS = 4,
+ IMX_IOMUXC_NAND_RE_B_ALT5_GPIO4_IO12 = 5,
+ IMX_IOMUXC_NAND_RE_B_ALT6_EIM_RW = 6,
+} IMX_IOMUXC_NAND_RE_B_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_READY_B_ALT0_NAND_READY_B = 0,
+ IMX_IOMUXC_NAND_READY_B_ALT1_SD1_VSELECT = 1,
+ IMX_IOMUXC_NAND_READY_B_ALT2_QSPI2A_DATA1 = 2,
+ IMX_IOMUXC_NAND_READY_B_ALT3_ECSPI2_MISO = 3,
+ IMX_IOMUXC_NAND_READY_B_ALT4_ESAI_TX1 = 4,
+ IMX_IOMUXC_NAND_READY_B_ALT5_GPIO4_IO13 = 5,
+ IMX_IOMUXC_NAND_READY_B_ALT6_EIM_EB1_B = 6,
+} IMX_IOMUXC_NAND_READY_B_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_WE_B_ALT0_NAND_WE_B = 0,
+ IMX_IOMUXC_NAND_WE_B_ALT1_SD4_VSELECT = 1,
+ IMX_IOMUXC_NAND_WE_B_ALT2_QSPI2B_DATA2 = 2,
+ IMX_IOMUXC_NAND_WE_B_ALT3_AUD4_RXD = 3,
+ IMX_IOMUXC_NAND_WE_B_ALT4_ESAI_TX5_RX0 = 4,
+ IMX_IOMUXC_NAND_WE_B_ALT5_GPIO4_IO14 = 5,
+ IMX_IOMUXC_NAND_WE_B_ALT6_EIM_WAIT = 6,
+} IMX_IOMUXC_NAND_WE_B_ALT;
+
+typedef enum {
+ IMX_IOMUXC_NAND_WP_B_ALT0_NAND_WP_B = 0,
+ IMX_IOMUXC_NAND_WP_B_ALT1_SD1_RESET_B = 1,
+ IMX_IOMUXC_NAND_WP_B_ALT2_QSPI2A_DATA0 = 2,
+ IMX_IOMUXC_NAND_WP_B_ALT3_ECSPI2_MOSI = 3,
+ IMX_IOMUXC_NAND_WP_B_ALT4_ESAI_TX4_RX1 = 4,
+ IMX_IOMUXC_NAND_WP_B_ALT5_GPIO4_IO15 = 5,
+ IMX_IOMUXC_NAND_WP_B_ALT6_EIM_EB0_B = 6,
+} IMX_IOMUXC_NAND_WP_B_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1A_DATA0_ALT0_QSPI1A_DATA0 = 0,
+ IMX_IOMUXC_QSPI1A_DATA0_ALT1_USB_OTG2_OC = 1,
+ IMX_IOMUXC_QSPI1A_DATA0_ALT2_ECSPI1_MOSI = 2,
+ IMX_IOMUXC_QSPI1A_DATA0_ALT3_ESAI_TX4_RX1 = 3,
+ IMX_IOMUXC_QSPI1A_DATA0_ALT4_CSI1_DATA14 = 4,
+ IMX_IOMUXC_QSPI1A_DATA0_ALT5_GPIO4_IO16 = 5,
+ IMX_IOMUXC_QSPI1A_DATA0_ALT6_EIM_DATA06 = 6,
+} IMX_IOMUXC_QSPI1A_DATA0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1A_DATA1_ALT0_QSPI1A_DATA1 = 0,
+ IMX_IOMUXC_QSPI1A_DATA1_ALT1_USB_OTG1_ID = 1,
+ IMX_IOMUXC_QSPI1A_DATA1_ALT2_ECSPI1_MISO = 2,
+ IMX_IOMUXC_QSPI1A_DATA1_ALT3_ESAI_TX1 = 3,
+ IMX_IOMUXC_QSPI1A_DATA1_ALT4_CSI1_DATA13 = 4,
+ IMX_IOMUXC_QSPI1A_DATA1_ALT5_GPIO4_IO17 = 5,
+ IMX_IOMUXC_QSPI1A_DATA1_ALT6_EIM_DATA05 = 6,
+} IMX_IOMUXC_QSPI1A_DATA1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1A_DATA2_ALT0_QSPI1A_DATA2 = 0,
+ IMX_IOMUXC_QSPI1A_DATA2_ALT1_USB_OTG1_PWR = 1,
+ IMX_IOMUXC_QSPI1A_DATA2_ALT2_ECSPI5_SS1 = 2,
+ IMX_IOMUXC_QSPI1A_DATA2_ALT3_ESAI_TX_CLK = 3,
+ IMX_IOMUXC_QSPI1A_DATA2_ALT4_CSI1_DATA12 = 4,
+ IMX_IOMUXC_QSPI1A_DATA2_ALT5_GPIO4_IO18 = 5,
+ IMX_IOMUXC_QSPI1A_DATA2_ALT6_EIM_DATA04 = 6,
+} IMX_IOMUXC_QSPI1A_DATA2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1A_DATA3_ALT0_QSPI1A_DATA3 = 0,
+ IMX_IOMUXC_QSPI1A_DATA3_ALT1_USB_OTG1_OC = 1,
+ IMX_IOMUXC_QSPI1A_DATA3_ALT2_ECSPI5_SS2 = 2,
+ IMX_IOMUXC_QSPI1A_DATA3_ALT3_ESAI_TX0 = 3,
+ IMX_IOMUXC_QSPI1A_DATA3_ALT4_CSI1_DATA11 = 4,
+ IMX_IOMUXC_QSPI1A_DATA3_ALT5_GPIO4_IO19 = 5,
+ IMX_IOMUXC_QSPI1A_DATA3_ALT6_EIM_DATA03 = 6,
+} IMX_IOMUXC_QSPI1A_DATA3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1A_DQS_ALT0_QSPI1A_DQS = 0,
+ IMX_IOMUXC_QSPI1A_DQS_ALT1_CAN2_TX = 1,
+ IMX_IOMUXC_QSPI1A_DQS_ALT3_ECSPI5_MOSI = 3,
+ IMX_IOMUXC_QSPI1A_DQS_ALT4_CSI1_DATA15 = 4,
+ IMX_IOMUXC_QSPI1A_DQS_ALT5_GPIO4_IO20 = 5,
+ IMX_IOMUXC_QSPI1A_DQS_ALT6_EIM_DATA07 = 6,
+} IMX_IOMUXC_QSPI1A_DQS_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1A_SCLK_ALT0_QSPI1A_SCLK = 0,
+ IMX_IOMUXC_QSPI1A_SCLK_ALT1_USB_OTG2_ID = 1,
+ IMX_IOMUXC_QSPI1A_SCLK_ALT2_ECSPI1_SCLK = 2,
+ IMX_IOMUXC_QSPI1A_SCLK_ALT3_ESAI_TX2_RX3 = 3,
+ IMX_IOMUXC_QSPI1A_SCLK_ALT4_CSI1_DATA01 = 4,
+ IMX_IOMUXC_QSPI1A_SCLK_ALT5_GPIO4_IO21 = 5,
+ IMX_IOMUXC_QSPI1A_SCLK_ALT6_EIM_DATA00 = 6,
+} IMX_IOMUXC_QSPI1A_SCLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1A_SS0_B_ALT0_QSPI1A_SS0_B = 0,
+ IMX_IOMUXC_QSPI1A_SS0_B_ALT1_USB_OTG2_PWR = 1,
+ IMX_IOMUXC_QSPI1A_SS0_B_ALT2_ECSPI1_SS0 = 2,
+ IMX_IOMUXC_QSPI1A_SS0_B_ALT3_ESAI_TX3_RX2 = 3,
+ IMX_IOMUXC_QSPI1A_SS0_B_ALT4_CSI1_DATA00 = 4,
+ IMX_IOMUXC_QSPI1A_SS0_B_ALT5_GPIO4_IO22 = 5,
+ IMX_IOMUXC_QSPI1A_SS0_B_ALT6_EIM_DATA01 = 6,
+} IMX_IOMUXC_QSPI1A_SS0_B_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1A_SS1_B_ALT0_QSPI1A_SS1_B = 0,
+ IMX_IOMUXC_QSPI1A_SS1_B_ALT1_CAN1_RX = 1,
+ IMX_IOMUXC_QSPI1A_SS1_B_ALT3_ECSPI5_MISO = 3,
+ IMX_IOMUXC_QSPI1A_SS1_B_ALT4_CSI1_DATA10 = 4,
+ IMX_IOMUXC_QSPI1A_SS1_B_ALT5_GPIO4_IO23 = 5,
+ IMX_IOMUXC_QSPI1A_SS1_B_ALT6_EIM_DATA02 = 6,
+} IMX_IOMUXC_QSPI1A_SS1_B_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1B_DATA0_ALT0_QSPI1B_DATA0 = 0,
+ IMX_IOMUXC_QSPI1B_DATA0_ALT1_UART3_CTS_B = 1,
+ IMX_IOMUXC_QSPI1B_DATA0_ALT2_ECSPI3_MOSI = 2,
+ IMX_IOMUXC_QSPI1B_DATA0_ALT3_ESAI_RX_FS = 3,
+ IMX_IOMUXC_QSPI1B_DATA0_ALT4_CSI1_DATA22 = 4,
+ IMX_IOMUXC_QSPI1B_DATA0_ALT5_GPIO4_IO24 = 5,
+ IMX_IOMUXC_QSPI1B_DATA0_ALT6_EIM_DATA14 = 6,
+} IMX_IOMUXC_QSPI1B_DATA0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1B_DATA1_ALT0_QSPI1B_DATA1 = 0,
+ IMX_IOMUXC_QSPI1B_DATA1_ALT1_UART3_RTS_B = 1,
+ IMX_IOMUXC_QSPI1B_DATA1_ALT2_ECSPI3_MISO = 2,
+ IMX_IOMUXC_QSPI1B_DATA1_ALT3_ESAI_RX_CLK = 3,
+ IMX_IOMUXC_QSPI1B_DATA1_ALT4_CSI1_DATA21 = 4,
+ IMX_IOMUXC_QSPI1B_DATA1_ALT5_GPIO4_IO25 = 5,
+ IMX_IOMUXC_QSPI1B_DATA1_ALT6_EIM_DATA13 = 6,
+} IMX_IOMUXC_QSPI1B_DATA1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1B_DATA2_ALT0_QSPI1B_DATA2 = 0,
+ IMX_IOMUXC_QSPI1B_DATA2_ALT1_I2C2_SDA = 1,
+ IMX_IOMUXC_QSPI1B_DATA2_ALT2_ECSPI5_RDY = 2,
+ IMX_IOMUXC_QSPI1B_DATA2_ALT3_ESAI_TX5_RX0 = 3,
+ IMX_IOMUXC_QSPI1B_DATA2_ALT4_CSI1_DATA20 = 4,
+ IMX_IOMUXC_QSPI1B_DATA2_ALT5_GPIO4_IO26 = 5,
+ IMX_IOMUXC_QSPI1B_DATA2_ALT6_EIM_DATA12 = 6,
+} IMX_IOMUXC_QSPI1B_DATA2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1B_DATA3_ALT0_QSPI1B_DATA3 = 0,
+ IMX_IOMUXC_QSPI1B_DATA3_ALT1_I2C2_SCL = 1,
+ IMX_IOMUXC_QSPI1B_DATA3_ALT2_ECSPI5_SS3 = 2,
+ IMX_IOMUXC_QSPI1B_DATA3_ALT3_ESAI_TX_FS = 3,
+ IMX_IOMUXC_QSPI1B_DATA3_ALT4_CSI1_DATA19 = 4,
+ IMX_IOMUXC_QSPI1B_DATA3_ALT5_GPIO4_IO27 = 5,
+ IMX_IOMUXC_QSPI1B_DATA3_ALT6_EIM_DATA11 = 6,
+} IMX_IOMUXC_QSPI1B_DATA3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1B_DQS_ALT0_QSPI1B_DQS = 0,
+ IMX_IOMUXC_QSPI1B_DQS_ALT1_CAN1_TX = 1,
+ IMX_IOMUXC_QSPI1B_DQS_ALT3_ECSPI5_SS0 = 3,
+ IMX_IOMUXC_QSPI1B_DQS_ALT4_CSI1_DATA23 = 4,
+ IMX_IOMUXC_QSPI1B_DQS_ALT5_GPIO4_IO28 = 5,
+ IMX_IOMUXC_QSPI1B_DQS_ALT6_EIM_DATA15 = 6,
+} IMX_IOMUXC_QSPI1B_DQS_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1B_SCLK_ALT0_QSPI1B_SCLK = 0,
+ IMX_IOMUXC_QSPI1B_SCLK_ALT1_UART3_RX_DATA = 1,
+ IMX_IOMUXC_QSPI1B_SCLK_ALT2_ECSPI3_SCLK = 2,
+ IMX_IOMUXC_QSPI1B_SCLK_ALT3_ESAI_RX_HF_CLK = 3,
+ IMX_IOMUXC_QSPI1B_SCLK_ALT4_CSI1_DATA16 = 4,
+ IMX_IOMUXC_QSPI1B_SCLK_ALT5_GPIO4_IO29 = 5,
+ IMX_IOMUXC_QSPI1B_SCLK_ALT6_EIM_DATA08 = 6,
+} IMX_IOMUXC_QSPI1B_SCLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1B_SS0_B_ALT0_QSPI1B_SS0_B = 0,
+ IMX_IOMUXC_QSPI1B_SS0_B_ALT1_UART3_TX_DATA = 1,
+ IMX_IOMUXC_QSPI1B_SS0_B_ALT2_ECSPI3_SS0 = 2,
+ IMX_IOMUXC_QSPI1B_SS0_B_ALT3_ESAI_TX_HF_CLK = 3,
+ IMX_IOMUXC_QSPI1B_SS0_B_ALT4_CSI1_DATA17 = 4,
+ IMX_IOMUXC_QSPI1B_SS0_B_ALT5_GPIO4_IO30 = 5,
+ IMX_IOMUXC_QSPI1B_SS0_B_ALT6_EIM_DATA09 = 6,
+} IMX_IOMUXC_QSPI1B_SS0_B_ALT;
+
+typedef enum {
+ IMX_IOMUXC_QSPI1B_SS1_B_ALT0_QSPI1B_SS1_B = 0,
+ IMX_IOMUXC_QSPI1B_SS1_B_ALT1_CAN2_RX = 1,
+ IMX_IOMUXC_QSPI1B_SS1_B_ALT3_ECSPI5_SCLK = 3,
+ IMX_IOMUXC_QSPI1B_SS1_B_ALT4_CSI1_DATA18 = 4,
+ IMX_IOMUXC_QSPI1B_SS1_B_ALT5_GPIO4_IO31 = 5,
+ IMX_IOMUXC_QSPI1B_SS1_B_ALT6_EIM_DATA10 = 6,
+} IMX_IOMUXC_QSPI1B_SS1_B_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII1_RD0_ALT0_ENET1_RX_DATA0 = 0,
+ IMX_IOMUXC_RGMII1_RD0_ALT5_GPIO5_IO00 = 5,
+ IMX_IOMUXC_RGMII1_RD0_ALT6_CSI2_DATA10 = 6,
+} IMX_IOMUXC_RGMII1_RD0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII1_RD1_ALT0_ENET1_RX_DATA1 = 0,
+ IMX_IOMUXC_RGMII1_RD1_ALT5_GPIO5_IO01 = 5,
+ IMX_IOMUXC_RGMII1_RD1_ALT6_CSI2_DATA11 = 6,
+} IMX_IOMUXC_RGMII1_RD1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII1_RD2_ALT0_ENET1_RX_DATA2 = 0,
+ IMX_IOMUXC_RGMII1_RD2_ALT5_GPIO5_IO02 = 5,
+ IMX_IOMUXC_RGMII1_RD2_ALT6_CSI2_DATA12 = 6,
+} IMX_IOMUXC_RGMII1_RD2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII1_RD3_ALT0_ENET1_RX_DATA3 = 0,
+ IMX_IOMUXC_RGMII1_RD3_ALT5_GPIO5_IO03 = 5,
+ IMX_IOMUXC_RGMII1_RD3_ALT6_CSI2_DATA13 = 6,
+} IMX_IOMUXC_RGMII1_RD3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII1_RX_CTL_ALT0_ENET1_RX_EN = 0,
+ IMX_IOMUXC_RGMII1_RX_CTL_ALT5_GPIO5_IO04 = 5,
+ IMX_IOMUXC_RGMII1_RX_CTL_ALT6_CSI2_DATA14 = 6,
+} IMX_IOMUXC_RGMII1_RX_CTL_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII1_RXC_ALT0_ENET1_RGMII_RXC = 0,
+ IMX_IOMUXC_RGMII1_RXC_ALT1_ENET1_RX_ER = 1,
+ IMX_IOMUXC_RGMII1_RXC_ALT5_GPIO5_IO05 = 5,
+ IMX_IOMUXC_RGMII1_RXC_ALT6_CSI2_DATA15 = 6,
+} IMX_IOMUXC_RGMII1_RXC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII1_TD0_ALT0_ENET1_TX_DATA0 = 0,
+ IMX_IOMUXC_RGMII1_TD0_ALT2_SAI2_RX_SYNC = 2,
+ IMX_IOMUXC_RGMII1_TD0_ALT5_GPIO5_IO06 = 5,
+ IMX_IOMUXC_RGMII1_TD0_ALT6_CSI2_DATA16 = 6,
+} IMX_IOMUXC_RGMII1_TD0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII1_TD1_ALT0_ENET1_TX_DATA1 = 0,
+ IMX_IOMUXC_RGMII1_TD1_ALT2_SAI2_RX_BCLK = 2,
+ IMX_IOMUXC_RGMII1_TD1_ALT5_GPIO5_IO07 = 5,
+ IMX_IOMUXC_RGMII1_TD1_ALT6_CSI2_DATA17 = 6,
+} IMX_IOMUXC_RGMII1_TD1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII1_TD2_ALT0_ENET1_TX_DATA2 = 0,
+ IMX_IOMUXC_RGMII1_TD2_ALT2_SAI2_TX_SYNC = 2,
+ IMX_IOMUXC_RGMII1_TD2_ALT5_GPIO5_IO08 = 5,
+ IMX_IOMUXC_RGMII1_TD2_ALT6_CSI2_DATA18 = 6,
+} IMX_IOMUXC_RGMII1_TD2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII1_TD3_ALT0_ENET1_TX_DATA3 = 0,
+ IMX_IOMUXC_RGMII1_TD3_ALT2_SAI2_TX_BCLK = 2,
+ IMX_IOMUXC_RGMII1_TD3_ALT5_GPIO5_IO09 = 5,
+ IMX_IOMUXC_RGMII1_TD3_ALT6_CSI2_DATA19 = 6,
+} IMX_IOMUXC_RGMII1_TD3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII1_TX_CTL_ALT0_ENET1_TX_EN = 0,
+ IMX_IOMUXC_RGMII1_TX_CTL_ALT2_SAI2_RX_DATA0 = 2,
+ IMX_IOMUXC_RGMII1_TX_CTL_ALT5_GPIO5_IO10 = 5,
+ IMX_IOMUXC_RGMII1_TX_CTL_ALT6_CSI2_DATA00 = 6,
+} IMX_IOMUXC_RGMII1_TX_CTL_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII1_TXC_ALT0_ENET1_RGMII_TXC = 0,
+ IMX_IOMUXC_RGMII1_TXC_ALT1_ENET1_TX_ER = 1,
+ IMX_IOMUXC_RGMII1_TXC_ALT2_SAI2_TX_DATA0 = 2,
+ IMX_IOMUXC_RGMII1_TXC_ALT5_GPIO5_IO11 = 5,
+ IMX_IOMUXC_RGMII1_TXC_ALT6_CSI2_DATA01 = 6,
+} IMX_IOMUXC_RGMII1_TXC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII2_RD0_ALT0_ENET2_RX_DATA0 = 0,
+ IMX_IOMUXC_RGMII2_RD0_ALT2_PWM4_OUT = 2,
+ IMX_IOMUXC_RGMII2_RD0_ALT5_GPIO5_IO12 = 5,
+ IMX_IOMUXC_RGMII2_RD0_ALT6_CSI2_DATA02 = 6,
+} IMX_IOMUXC_RGMII2_RD0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII2_RD1_ALT0_ENET2_RX_DATA1 = 0,
+ IMX_IOMUXC_RGMII2_RD1_ALT2_PWM3_OUT = 2,
+ IMX_IOMUXC_RGMII2_RD1_ALT5_GPIO5_IO13 = 5,
+ IMX_IOMUXC_RGMII2_RD1_ALT6_CSI2_DATA03 = 6,
+} IMX_IOMUXC_RGMII2_RD1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII2_RD2_ALT0_ENET2_RX_DATA2 = 0,
+ IMX_IOMUXC_RGMII2_RD2_ALT2_PWM2_OUT = 2,
+ IMX_IOMUXC_RGMII2_RD2_ALT5_GPIO5_IO14 = 5,
+ IMX_IOMUXC_RGMII2_RD2_ALT6_CSI2_DATA04 = 6,
+} IMX_IOMUXC_RGMII2_RD2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII2_RD3_ALT0_ENET2_RX_DATA3 = 0,
+ IMX_IOMUXC_RGMII2_RD3_ALT2_PWM1_OUT = 2,
+ IMX_IOMUXC_RGMII2_RD3_ALT5_GPIO5_IO15 = 5,
+ IMX_IOMUXC_RGMII2_RD3_ALT6_CSI2_DATA05 = 6,
+} IMX_IOMUXC_RGMII2_RD3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII2_RX_CTL_ALT0_ENET2_RX_EN = 0,
+ IMX_IOMUXC_RGMII2_RX_CTL_ALT5_GPIO5_IO16 = 5,
+ IMX_IOMUXC_RGMII2_RX_CTL_ALT6_CSI2_DATA06 = 6,
+} IMX_IOMUXC_RGMII2_RX_CTL_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII2_RXC_ALT0_ENET2_RGMII_RXC = 0,
+ IMX_IOMUXC_RGMII2_RXC_ALT1_ENET2_RX_ER = 1,
+ IMX_IOMUXC_RGMII2_RXC_ALT5_GPIO5_IO17 = 5,
+ IMX_IOMUXC_RGMII2_RXC_ALT6_CSI2_DATA07 = 6,
+} IMX_IOMUXC_RGMII2_RXC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII2_TD0_ALT0_ENET2_TX_DATA0 = 0,
+ IMX_IOMUXC_RGMII2_TD0_ALT2_SAI1_RX_SYNC = 2,
+ IMX_IOMUXC_RGMII2_TD0_ALT3_PWM8_OUT = 3,
+ IMX_IOMUXC_RGMII2_TD0_ALT5_GPIO5_IO18 = 5,
+ IMX_IOMUXC_RGMII2_TD0_ALT6_CSI2_DATA08 = 6,
+} IMX_IOMUXC_RGMII2_TD0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII2_TD1_ALT0_ENET2_TX_DATA1 = 0,
+ IMX_IOMUXC_RGMII2_TD1_ALT2_SAI1_RX_BCLK = 2,
+ IMX_IOMUXC_RGMII2_TD1_ALT3_PWM7_OUT = 3,
+ IMX_IOMUXC_RGMII2_TD1_ALT5_GPIO5_IO19 = 5,
+ IMX_IOMUXC_RGMII2_TD1_ALT6_CSI2_DATA09 = 6,
+} IMX_IOMUXC_RGMII2_TD1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII2_TD2_ALT0_ENET2_TX_DATA2 = 0,
+ IMX_IOMUXC_RGMII2_TD2_ALT2_SAI1_TX_SYNC = 2,
+ IMX_IOMUXC_RGMII2_TD2_ALT3_PWM6_OUT = 3,
+ IMX_IOMUXC_RGMII2_TD2_ALT5_GPIO5_IO20 = 5,
+ IMX_IOMUXC_RGMII2_TD2_ALT6_CSI2_VSYNC = 6,
+} IMX_IOMUXC_RGMII2_TD2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII2_TD3_ALT0_ENET2_TX_DATA3 = 0,
+ IMX_IOMUXC_RGMII2_TD3_ALT2_SAI1_TX_BCLK = 2,
+ IMX_IOMUXC_RGMII2_TD3_ALT3_PWM5_OUT = 3,
+ IMX_IOMUXC_RGMII2_TD3_ALT5_GPIO5_IO21 = 5,
+ IMX_IOMUXC_RGMII2_TD3_ALT6_CSI2_HSYNC = 6,
+} IMX_IOMUXC_RGMII2_TD3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII2_TX_CTL_ALT0_ENET2_TX_EN = 0,
+ IMX_IOMUXC_RGMII2_TX_CTL_ALT2_SAI1_RX_DATA0 = 2,
+ IMX_IOMUXC_RGMII2_TX_CTL_ALT5_GPIO5_IO22 = 5,
+ IMX_IOMUXC_RGMII2_TX_CTL_ALT6_CSI2_FIELD = 6,
+ IMX_IOMUXC_RGMII2_TX_CTL_ALT7_JTAG_DE_B = 7,
+} IMX_IOMUXC_RGMII2_TX_CTL_ALT;
+
+typedef enum {
+ IMX_IOMUXC_RGMII2_TXC_ALT0_ENET2_RGMII_TXC = 0,
+ IMX_IOMUXC_RGMII2_TXC_ALT1_ENET2_TX_ER = 1,
+ IMX_IOMUXC_RGMII2_TXC_ALT2_SAI1_TX_DATA0 = 2,
+ IMX_IOMUXC_RGMII2_TXC_ALT5_GPIO5_IO23 = 5,
+ IMX_IOMUXC_RGMII2_TXC_ALT6_CSI2_PIXCLK = 6,
+} IMX_IOMUXC_RGMII2_TXC_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_CLK_ALT0_SD1_CLK = 0,
+ IMX_IOMUXC_SD1_CLK_ALT1_AUD5_RXFS = 1,
+ IMX_IOMUXC_SD1_CLK_ALT2_WDOG2_B = 2,
+ IMX_IOMUXC_SD1_CLK_ALT3_GPT_CLK = 3,
+ IMX_IOMUXC_SD1_CLK_ALT4_WDOG2_RST_B_DEB = 4,
+ IMX_IOMUXC_SD1_CLK_ALT5_GPIO6_IO00 = 5,
+ IMX_IOMUXC_SD1_CLK_ALT6_ENET2_1588_EVENT1_OUT = 6,
+} IMX_IOMUXC_SD1_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_CMD_ALT0_SD1_CMD = 0,
+ IMX_IOMUXC_SD1_CMD_ALT1_AUD5_RXC = 1,
+ IMX_IOMUXC_SD1_CMD_ALT2_WDOG1_B = 2,
+ IMX_IOMUXC_SD1_CMD_ALT3_GPT_COMPARE1 = 3,
+ IMX_IOMUXC_SD1_CMD_ALT4_WDOG1_RST_B_DEB = 4,
+ IMX_IOMUXC_SD1_CMD_ALT5_GPIO6_IO01 = 5,
+ IMX_IOMUXC_SD1_CMD_ALT6_ENET2_1588_EVENT1_IN = 6,
+ IMX_IOMUXC_SD1_CMD_ALT7_CCM_CLKO1 = 7,
+} IMX_IOMUXC_SD1_CMD_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_DATA0_ALT0_SD1_DATA0 = 0,
+ IMX_IOMUXC_SD1_DATA0_ALT1_AUD5_RXD = 1,
+ IMX_IOMUXC_SD1_DATA0_ALT3_GPT_CAPTURE1 = 3,
+ IMX_IOMUXC_SD1_DATA0_ALT4_UART2_RX_DATA = 4,
+ IMX_IOMUXC_SD1_DATA0_ALT5_GPIO6_IO02 = 5,
+ IMX_IOMUXC_SD1_DATA0_ALT6_ENET1_1588_EVENT1_IN = 6,
+} IMX_IOMUXC_SD1_DATA0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_DATA1_ALT0_SD1_DATA1 = 0,
+ IMX_IOMUXC_SD1_DATA1_ALT1_AUD5_TXC = 1,
+ IMX_IOMUXC_SD1_DATA1_ALT2_PWM4_OUT = 2,
+ IMX_IOMUXC_SD1_DATA1_ALT3_GPT_CAPTURE2 = 3,
+ IMX_IOMUXC_SD1_DATA1_ALT4_UART2_TX_DATA = 4,
+ IMX_IOMUXC_SD1_DATA1_ALT5_GPIO6_IO03 = 5,
+ IMX_IOMUXC_SD1_DATA1_ALT6_ENET1_1588_EVENT1_OUT = 6,
+ IMX_IOMUXC_SD1_DATA1_ALT7_CCM_CLKO2 = 7,
+} IMX_IOMUXC_SD1_DATA1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_DATA2_ALT0_SD1_DATA2 = 0,
+ IMX_IOMUXC_SD1_DATA2_ALT1_AUD5_TXFS = 1,
+ IMX_IOMUXC_SD1_DATA2_ALT2_PWM3_OUT = 2,
+ IMX_IOMUXC_SD1_DATA2_ALT3_GPT_COMPARE2 = 3,
+ IMX_IOMUXC_SD1_DATA2_ALT4_UART2_CTS_B = 4,
+ IMX_IOMUXC_SD1_DATA2_ALT5_GPIO6_IO04 = 5,
+ IMX_IOMUXC_SD1_DATA2_ALT6_ECSPI4_RDY = 6,
+} IMX_IOMUXC_SD1_DATA2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD1_DATA3_ALT0_SD1_DATA3 = 0,
+ IMX_IOMUXC_SD1_DATA3_ALT1_AUD5_TXD = 1,
+ IMX_IOMUXC_SD1_DATA3_ALT2_AUD5_RXD = 2,
+ IMX_IOMUXC_SD1_DATA3_ALT3_GPT_COMPARE3 = 3,
+ IMX_IOMUXC_SD1_DATA3_ALT4_UART2_RTS_B = 4,
+ IMX_IOMUXC_SD1_DATA3_ALT5_GPIO6_IO05 = 5,
+ IMX_IOMUXC_SD1_DATA3_ALT6_ECSPI4_SS1 = 6,
+ IMX_IOMUXC_SD1_DATA3_ALT7_CCM_PMIC_READY = 7,
+} IMX_IOMUXC_SD1_DATA3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_CLK_ALT0_SD2_CLK = 0,
+ IMX_IOMUXC_SD2_CLK_ALT1_AUD6_RXFS = 1,
+ IMX_IOMUXC_SD2_CLK_ALT2_KPP_COL5 = 2,
+ IMX_IOMUXC_SD2_CLK_ALT3_ECSPI4_SCLK = 3,
+ IMX_IOMUXC_SD2_CLK_ALT4_MLB_SIG = 4,
+ IMX_IOMUXC_SD2_CLK_ALT5_GPIO6_IO06 = 5,
+ IMX_IOMUXC_SD2_CLK_ALT6_MQS_RIGHT = 6,
+ IMX_IOMUXC_SD2_CLK_ALT7_WDOG1_ANY = 7,
+} IMX_IOMUXC_SD2_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_CMD_ALT0_SD2_CMD = 0,
+ IMX_IOMUXC_SD2_CMD_ALT1_AUD6_RXC = 1,
+ IMX_IOMUXC_SD2_CMD_ALT2_KPP_ROW5 = 2,
+ IMX_IOMUXC_SD2_CMD_ALT3_ECSPI4_MOSI = 3,
+ IMX_IOMUXC_SD2_CMD_ALT4_MLB_CLK = 4,
+ IMX_IOMUXC_SD2_CMD_ALT5_GPIO6_IO07 = 5,
+ IMX_IOMUXC_SD2_CMD_ALT6_MQS_LEFT = 6,
+ IMX_IOMUXC_SD2_CMD_ALT7_WDOG3_B = 7,
+} IMX_IOMUXC_SD2_CMD_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_DATA0_ALT0_SD2_DATA0 = 0,
+ IMX_IOMUXC_SD2_DATA0_ALT1_AUD6_RXD = 1,
+ IMX_IOMUXC_SD2_DATA0_ALT2_KPP_ROW7 = 2,
+ IMX_IOMUXC_SD2_DATA0_ALT3_PWM1_OUT = 3,
+ IMX_IOMUXC_SD2_DATA0_ALT4_I2C4_SDA = 4,
+ IMX_IOMUXC_SD2_DATA0_ALT5_GPIO6_IO08 = 5,
+ IMX_IOMUXC_SD2_DATA0_ALT6_ECSPI4_SS3 = 6,
+ IMX_IOMUXC_SD2_DATA0_ALT7_UART4_RX_DATA = 7,
+} IMX_IOMUXC_SD2_DATA0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_DATA1_ALT0_SD2_DATA1 = 0,
+ IMX_IOMUXC_SD2_DATA1_ALT1_AUD6_TXC = 1,
+ IMX_IOMUXC_SD2_DATA1_ALT2_KPP_COL7 = 2,
+ IMX_IOMUXC_SD2_DATA1_ALT3_PWM2_OUT = 3,
+ IMX_IOMUXC_SD2_DATA1_ALT4_I2C4_SCL = 4,
+ IMX_IOMUXC_SD2_DATA1_ALT5_GPIO6_IO09 = 5,
+ IMX_IOMUXC_SD2_DATA1_ALT6_ECSPI4_SS2 = 6,
+ IMX_IOMUXC_SD2_DATA1_ALT7_UART4_TX_DATA = 7,
+} IMX_IOMUXC_SD2_DATA1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_DATA2_ALT0_SD2_DATA2 = 0,
+ IMX_IOMUXC_SD2_DATA2_ALT1_AUD6_TXFS = 1,
+ IMX_IOMUXC_SD2_DATA2_ALT2_KPP_ROW6 = 2,
+ IMX_IOMUXC_SD2_DATA2_ALT3_ECSPI4_SS0 = 3,
+ IMX_IOMUXC_SD2_DATA2_ALT4_SDMA_EXT_EVENT0 = 4,
+ IMX_IOMUXC_SD2_DATA2_ALT5_GPIO6_IO10 = 5,
+ IMX_IOMUXC_SD2_DATA2_ALT6_SPDIF_OUT = 6,
+ IMX_IOMUXC_SD2_DATA2_ALT7_UART6_RX_DATA = 7,
+} IMX_IOMUXC_SD2_DATA2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD2_DATA3_ALT0_SD2_DATA3 = 0,
+ IMX_IOMUXC_SD2_DATA3_ALT1_AUD6_TXD = 1,
+ IMX_IOMUXC_SD2_DATA3_ALT2_KPP_COL6 = 2,
+ IMX_IOMUXC_SD2_DATA3_ALT3_ECSPI4_MISO = 3,
+ IMX_IOMUXC_SD2_DATA3_ALT4_MLB_DATA = 4,
+ IMX_IOMUXC_SD2_DATA3_ALT5_GPIO6_IO11 = 5,
+ IMX_IOMUXC_SD2_DATA3_ALT6_SPDIF_IN = 6,
+ IMX_IOMUXC_SD2_DATA3_ALT7_UART6_TX_DATA = 7,
+} IMX_IOMUXC_SD2_DATA3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_CLK_ALT0_SD4_CLK = 0,
+ IMX_IOMUXC_SD4_CLK_ALT1_NAND_DATA15 = 1,
+ IMX_IOMUXC_SD4_CLK_ALT2_ECSPI2_MISO = 2,
+ IMX_IOMUXC_SD4_CLK_ALT3_AUD3_RXFS = 3,
+ IMX_IOMUXC_SD4_CLK_ALT4_LCD2_DATA13 = 4,
+ IMX_IOMUXC_SD4_CLK_ALT5_GPIO6_IO12 = 5,
+ IMX_IOMUXC_SD4_CLK_ALT6_ECSPI3_SS2 = 6,
+} IMX_IOMUXC_SD4_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_CMD_ALT0_SD4_CMD = 0,
+ IMX_IOMUXC_SD4_CMD_ALT1_NAND_DATA14 = 1,
+ IMX_IOMUXC_SD4_CMD_ALT2_ECSPI2_MOSI = 2,
+ IMX_IOMUXC_SD4_CMD_ALT3_AUD3_RXC = 3,
+ IMX_IOMUXC_SD4_CMD_ALT4_LCD2_DATA14 = 4,
+ IMX_IOMUXC_SD4_CMD_ALT5_GPIO6_IO13 = 5,
+ IMX_IOMUXC_SD4_CMD_ALT6_ECSPI3_SS1 = 6,
+} IMX_IOMUXC_SD4_CMD_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DATA0_ALT0_SD4_DATA0 = 0,
+ IMX_IOMUXC_SD4_DATA0_ALT1_NAND_DATA10 = 1,
+ IMX_IOMUXC_SD4_DATA0_ALT2_ECSPI2_SS0 = 2,
+ IMX_IOMUXC_SD4_DATA0_ALT3_AUD3_RXD = 3,
+ IMX_IOMUXC_SD4_DATA0_ALT4_LCD2_DATA12 = 4,
+ IMX_IOMUXC_SD4_DATA0_ALT5_GPIO6_IO14 = 5,
+ IMX_IOMUXC_SD4_DATA0_ALT6_ECSPI3_SS3 = 6,
+} IMX_IOMUXC_SD4_DATA0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DATA1_ALT0_SD4_DATA1 = 0,
+ IMX_IOMUXC_SD4_DATA1_ALT1_NAND_DATA11 = 1,
+ IMX_IOMUXC_SD4_DATA1_ALT2_ECSPI2_SCLK = 2,
+ IMX_IOMUXC_SD4_DATA1_ALT3_AUD3_TXC = 3,
+ IMX_IOMUXC_SD4_DATA1_ALT4_LCD2_DATA11 = 4,
+ IMX_IOMUXC_SD4_DATA1_ALT5_GPIO6_IO15 = 5,
+ IMX_IOMUXC_SD4_DATA1_ALT6_ECSPI3_RDY = 6,
+} IMX_IOMUXC_SD4_DATA1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DATA2_ALT0_SD4_DATA2 = 0,
+ IMX_IOMUXC_SD4_DATA2_ALT1_NAND_DATA12 = 1,
+ IMX_IOMUXC_SD4_DATA2_ALT2_I2C2_SDA = 2,
+ IMX_IOMUXC_SD4_DATA2_ALT3_AUD3_TXFS = 3,
+ IMX_IOMUXC_SD4_DATA2_ALT4_LCD2_DATA10 = 4,
+ IMX_IOMUXC_SD4_DATA2_ALT5_GPIO6_IO16 = 5,
+ IMX_IOMUXC_SD4_DATA2_ALT6_ECSPI2_SS3 = 6,
+} IMX_IOMUXC_SD4_DATA2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DATA3_ALT0_SD4_DATA3 = 0,
+ IMX_IOMUXC_SD4_DATA3_ALT1_NAND_DATA13 = 1,
+ IMX_IOMUXC_SD4_DATA3_ALT2_I2C2_SCL = 2,
+ IMX_IOMUXC_SD4_DATA3_ALT3_AUD3_TXD = 3,
+ IMX_IOMUXC_SD4_DATA3_ALT4_LCD2_DATA09 = 4,
+ IMX_IOMUXC_SD4_DATA3_ALT5_GPIO6_IO17 = 5,
+ IMX_IOMUXC_SD4_DATA3_ALT6_ECSPI2_RDY = 6,
+} IMX_IOMUXC_SD4_DATA3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DATA4_ALT0_SD4_DATA4 = 0,
+ IMX_IOMUXC_SD4_DATA4_ALT1_NAND_DATA09 = 1,
+ IMX_IOMUXC_SD4_DATA4_ALT2_UART5_RX_DATA = 2,
+ IMX_IOMUXC_SD4_DATA4_ALT3_ECSPI3_SCLK = 3,
+ IMX_IOMUXC_SD4_DATA4_ALT4_LCD2_DATA08 = 4,
+ IMX_IOMUXC_SD4_DATA4_ALT5_GPIO6_IO18 = 5,
+ IMX_IOMUXC_SD4_DATA4_ALT6_SPDIF_OUT = 6,
+} IMX_IOMUXC_SD4_DATA4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DATA5_ALT0_SD4_DATA5 = 0,
+ IMX_IOMUXC_SD4_DATA5_ALT1_NAND_CE2_B = 1,
+ IMX_IOMUXC_SD4_DATA5_ALT2_UART5_TX_DATA = 2,
+ IMX_IOMUXC_SD4_DATA5_ALT3_ECSPI3_MOSI = 3,
+ IMX_IOMUXC_SD4_DATA5_ALT4_LCD2_DATA07 = 4,
+ IMX_IOMUXC_SD4_DATA5_ALT5_GPIO6_IO19 = 5,
+ IMX_IOMUXC_SD4_DATA5_ALT6_SPDIF_IN = 6,
+} IMX_IOMUXC_SD4_DATA5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DATA6_ALT0_SD4_DATA6 = 0,
+ IMX_IOMUXC_SD4_DATA6_ALT1_NAND_CE3_B = 1,
+ IMX_IOMUXC_SD4_DATA6_ALT2_UART5_RTS_B = 2,
+ IMX_IOMUXC_SD4_DATA6_ALT3_ECSPI3_MISO = 3,
+ IMX_IOMUXC_SD4_DATA6_ALT4_LCD2_DATA06 = 4,
+ IMX_IOMUXC_SD4_DATA6_ALT5_GPIO6_IO20 = 5,
+ IMX_IOMUXC_SD4_DATA6_ALT6_SD4_WP = 6,
+} IMX_IOMUXC_SD4_DATA6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_DATA7_ALT0_SD4_DATA7 = 0,
+ IMX_IOMUXC_SD4_DATA7_ALT1_NAND_DATA08 = 1,
+ IMX_IOMUXC_SD4_DATA7_ALT2_UART5_CTS_B = 2,
+ IMX_IOMUXC_SD4_DATA7_ALT3_ECSPI3_SS0 = 3,
+ IMX_IOMUXC_SD4_DATA7_ALT4_LCD2_DATA15 = 4,
+ IMX_IOMUXC_SD4_DATA7_ALT5_GPIO6_IO21 = 5,
+ IMX_IOMUXC_SD4_DATA7_ALT6_SD4_CD_B = 6,
+} IMX_IOMUXC_SD4_DATA7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD4_RESET_B_ALT0_SD4_RESET_B = 0,
+ IMX_IOMUXC_SD4_RESET_B_ALT1_NAND_DQS = 1,
+ IMX_IOMUXC_SD4_RESET_B_ALT2_SD4_RESET = 2,
+ IMX_IOMUXC_SD4_RESET_B_ALT3_AUDIO_CLK_OUT = 3,
+ IMX_IOMUXC_SD4_RESET_B_ALT4_LCD2_RESET = 4,
+ IMX_IOMUXC_SD4_RESET_B_ALT5_GPIO6_IO22 = 5,
+ IMX_IOMUXC_SD4_RESET_B_ALT6_LCD2_CS = 6,
+} IMX_IOMUXC_SD4_RESET_B_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_CLK_ALT0_SD3_CLK = 0,
+ IMX_IOMUXC_SD3_CLK_ALT1_UART4_CTS_B = 1,
+ IMX_IOMUXC_SD3_CLK_ALT2_ECSPI4_SCLK = 2,
+ IMX_IOMUXC_SD3_CLK_ALT3_AUD6_RXFS = 3,
+ IMX_IOMUXC_SD3_CLK_ALT4_LCD2_VSYNC = 4,
+ IMX_IOMUXC_SD3_CLK_ALT5_GPIO7_IO00 = 5,
+ IMX_IOMUXC_SD3_CLK_ALT6_LCD2_BUSY = 6,
+} IMX_IOMUXC_SD3_CLK_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_CMD_ALT0_SD3_CMD = 0,
+ IMX_IOMUXC_SD3_CMD_ALT1_UART4_TX_DATA = 1,
+ IMX_IOMUXC_SD3_CMD_ALT2_ECSPI4_MOSI = 2,
+ IMX_IOMUXC_SD3_CMD_ALT3_AUD6_RXC = 3,
+ IMX_IOMUXC_SD3_CMD_ALT4_LCD2_HSYNC = 4,
+ IMX_IOMUXC_SD3_CMD_ALT5_GPIO7_IO01 = 5,
+ IMX_IOMUXC_SD3_CMD_ALT6_LCD2_RS = 6,
+} IMX_IOMUXC_SD3_CMD_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DATA0_ALT0_SD3_DATA0 = 0,
+ IMX_IOMUXC_SD3_DATA0_ALT1_I2C4_SCL = 1,
+ IMX_IOMUXC_SD3_DATA0_ALT2_ECSPI2_SS1 = 2,
+ IMX_IOMUXC_SD3_DATA0_ALT3_AUD6_RXD = 3,
+ IMX_IOMUXC_SD3_DATA0_ALT4_LCD2_DATA01 = 4,
+ IMX_IOMUXC_SD3_DATA0_ALT5_GPIO7_IO02 = 5,
+ IMX_IOMUXC_SD3_DATA0_ALT6_DCIC1_OUT = 6,
+} IMX_IOMUXC_SD3_DATA0_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DATA1_ALT0_SD3_DATA1 = 0,
+ IMX_IOMUXC_SD3_DATA1_ALT1_I2C4_SDA = 1,
+ IMX_IOMUXC_SD3_DATA1_ALT2_ECSPI2_SS2 = 2,
+ IMX_IOMUXC_SD3_DATA1_ALT3_AUD6_TXC = 3,
+ IMX_IOMUXC_SD3_DATA1_ALT4_LCD2_DATA00 = 4,
+ IMX_IOMUXC_SD3_DATA1_ALT5_GPIO7_IO03 = 5,
+ IMX_IOMUXC_SD3_DATA1_ALT6_DCIC2_OUT = 6,
+} IMX_IOMUXC_SD3_DATA1_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DATA2_ALT0_SD3_DATA2 = 0,
+ IMX_IOMUXC_SD3_DATA2_ALT1_UART4_RTS_B = 1,
+ IMX_IOMUXC_SD3_DATA2_ALT2_ECSPI4_SS0 = 2,
+ IMX_IOMUXC_SD3_DATA2_ALT3_AUD6_TXFS = 3,
+ IMX_IOMUXC_SD3_DATA2_ALT4_LCD2_CLK = 4,
+ IMX_IOMUXC_SD3_DATA2_ALT5_GPIO7_IO04 = 5,
+ IMX_IOMUXC_SD3_DATA2_ALT6_LCD2_WR_RWN = 6,
+} IMX_IOMUXC_SD3_DATA2_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DATA3_ALT0_SD3_DATA3 = 0,
+ IMX_IOMUXC_SD3_DATA3_ALT1_UART4_RX_DATA = 1,
+ IMX_IOMUXC_SD3_DATA3_ALT2_ECSPI4_MISO = 2,
+ IMX_IOMUXC_SD3_DATA3_ALT3_AUD6_TXD = 3,
+ IMX_IOMUXC_SD3_DATA3_ALT4_LCD2_ENABLE = 4,
+ IMX_IOMUXC_SD3_DATA3_ALT5_GPIO7_IO05 = 5,
+ IMX_IOMUXC_SD3_DATA3_ALT6_LCD2_RD_E = 6,
+} IMX_IOMUXC_SD3_DATA3_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DATA4_ALT0_SD3_DATA4 = 0,
+ IMX_IOMUXC_SD3_DATA4_ALT1_CAN2_RX = 1,
+ IMX_IOMUXC_SD3_DATA4_ALT3_UART3_RX_DATA = 3,
+ IMX_IOMUXC_SD3_DATA4_ALT4_LCD2_DATA03 = 4,
+ IMX_IOMUXC_SD3_DATA4_ALT5_GPIO7_IO06 = 5,
+ IMX_IOMUXC_SD3_DATA4_ALT6_ENET2_1588_EVENT0_IN = 6,
+} IMX_IOMUXC_SD3_DATA4_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DATA5_ALT0_SD3_DATA5 = 0,
+ IMX_IOMUXC_SD3_DATA5_ALT1_CAN1_TX = 1,
+ IMX_IOMUXC_SD3_DATA5_ALT3_UART3_TX_DATA = 3,
+ IMX_IOMUXC_SD3_DATA5_ALT4_LCD2_DATA02 = 4,
+ IMX_IOMUXC_SD3_DATA5_ALT5_GPIO7_IO07 = 5,
+ IMX_IOMUXC_SD3_DATA5_ALT6_ENET2_1588_EVENT0_OUT = 6,
+} IMX_IOMUXC_SD3_DATA5_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DATA6_ALT0_SD3_DATA6 = 0,
+ IMX_IOMUXC_SD3_DATA6_ALT1_CAN2_TX = 1,
+ IMX_IOMUXC_SD3_DATA6_ALT3_UART3_RTS_B = 3,
+ IMX_IOMUXC_SD3_DATA6_ALT4_LCD2_DATA04 = 4,
+ IMX_IOMUXC_SD3_DATA6_ALT5_GPIO7_IO08 = 5,
+ IMX_IOMUXC_SD3_DATA6_ALT6_ENET1_1588_EVENT0_OUT = 6,
+} IMX_IOMUXC_SD3_DATA6_ALT;
+
+typedef enum {
+ IMX_IOMUXC_SD3_DATA7_ALT0_SD3_DATA7 = 0,
+ IMX_IOMUXC_SD3_DATA7_ALT1_CAN1_RX = 1,
+ IMX_IOMUXC_SD3_DATA7_ALT3_UART3_CTS_B = 3,
+ IMX_IOMUXC_SD3_DATA7_ALT4_LCD2_DATA05 = 4,
+ IMX_IOMUXC_SD3_DATA7_ALT5_GPIO7_IO09 = 5,
+ IMX_IOMUXC_SD3_DATA7_ALT6_ENET1_1588_EVENT0_IN = 6,
+} IMX_IOMUXC_SD3_DATA7_ALT;
+
+typedef enum {
+ IMX_IOMUXC_USB_H_DATA_ALT0_USB_H_DATA = 0,
+ IMX_IOMUXC_USB_H_DATA_ALT1_PWM2_OUT = 1,
+ IMX_IOMUXC_USB_H_DATA_ALT2_XTALOSC_REF_CLK_24M = 2,
+ IMX_IOMUXC_USB_H_DATA_ALT3_I2C4_SDA = 3,
+ IMX_IOMUXC_USB_H_DATA_ALT4_WDOG3_B = 4,
+ IMX_IOMUXC_USB_H_DATA_ALT5_GPIO7_IO10 = 5,
+} IMX_IOMUXC_USB_H_DATA_ALT;
+
+typedef enum {
+ IMX_IOMUXC_USB_H_STROBE_ALT0_USB_H_STROBE = 0,
+ IMX_IOMUXC_USB_H_STROBE_ALT1_PWM1_OUT = 1,
+ IMX_IOMUXC_USB_H_STROBE_ALT2_XTALOSC_REF_CLK_32K = 2,
+ IMX_IOMUXC_USB_H_STROBE_ALT3_I2C4_SCL = 3,
+ IMX_IOMUXC_USB_H_STROBE_ALT4_WDOG3_RST_B_DEB = 4,
+ IMX_IOMUXC_USB_H_STROBE_ALT5_GPIO7_IO11 = 5,
+} IMX_IOMUXC_USB_H_STROBE_ALT;
+
+#endif // _IMX6_IOMUX_SX_H_
diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6UsbPhy.h b/Silicon/NXP/iMX6Pkg/Include/iMX6UsbPhy.h
new file mode 100644
index 000000000000..d88108227589
--- /dev/null
+++ b/Silicon/NXP/iMX6Pkg/Include/iMX6UsbPhy.h
@@ -0,0 +1,20 @@
+/** @file
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef _IMX6_USB_PHY_H_
+#define _IMX6_USB_PHY_H_
+
+EFI_STATUS ImxUsbPhyInit (IMX_USBPHY_ID ImxUsbPhyId);
+
+#endif // _IMX6_USB_PHY_H_
diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6_DQ.h b/Silicon/NXP/iMX6Pkg/Include/iMX6_DQ.h
new file mode 100644
index 000000000000..f1c5574f968e
--- /dev/null
+++ b/Silicon/NXP/iMX6Pkg/Include/iMX6_DQ.h
@@ -0,0 +1,1686 @@
+/** @file
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __IMX6_DQ_H__
+#define __IMX6_DQ_H__
+
+#pragma pack(push, 1)
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+// Boot DRAM region (kernel.img & boot working DRAM)
+#define FRAME_BUFFER_BASE 0x10000000
+#define FRAME_BUFFER_SIZE 0x00800000 // 8MB
+
+#define BOOT_IMAGE_PHYSICAL_BASE 0x10800000
+#define BOOT_IMAGE_PHYSICAL_LENGTH 0x001D0000 // 1.8MB
+#define BOOT_IMAGE_ATTRIBUTES CacheAttributes
+
+// The region of registers from 0x00100000 to 0x00D00000
+#define SOC_REGISTERS_PHYSICAL_BASE1 0x00100000
+#define SOC_REGISTERS_PHYSICAL_LENGTH1 0x00C00000
+#define SOC_REGISTERS_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
+
+// PCIE registers and configuration space (0x01000000 - 0x02000000)
+#define PCIE_REGISTERS_PHYSICAL_BASE 0x01000000
+#define PCIE_REGISTERS_PHYSICAL_LENGTH 0x01000000
+
+// The region of registers from 0x02000000 to 0x02A00000
+#define SOC_REGISTERS_PHYSICAL_BASE2 0x02000000
+#define SOC_REGISTERS_PHYSICAL_LENGTH2 0x00A00000
+
+// Main system DRAM as defined by the PCD definitions of system memory.
+
+// MPPP definitions
+#define CPU0_MPPP_PHYSICAL_BASE 0x1080F000
+#define CPU1_MPPP_PHYSICAL_BASE 0x10810000
+#define CPU2_MPPP_PHYSICAL_BASE 0x10811000
+#define CPU3_MPPP_PHYSICAL_BASE 0x10812000
+
+// Interrupt controller
+#define CSP_BASE_REG_PA_IC_IFC 0x00A00100
+#define CSP_BASE_REG_PA_IC_DIST 0x00A01000
+
+// L2 cache controller
+#define CSP_BASE_REG_PA_PL310 0x00A02000
+
+// Timers
+#define CSP_BASE_REG_PA_GPT 0x02098000
+#define CSP_BASE_REG_PA_EPIT1 0x020D0000
+#define CSP_BASE_REG_PA_EPIT2 0x020D4000
+
+// Timers IRQs
+#define IC_DIST_VECTOR_BASE 0
+#define IRQ_EPIT1 88
+#define IRQ_EPIT2 89
+
+// SDMA (Smart DMA) controller
+#define CSP_BASE_REG_PA_SDMA 0x020EC000
+#define IRQ_SDMA 34
+
+// SOC peripherals
+#define CSP_BASE_REG_PA_UART1 0x02020000
+#define CSP_BASE_REG_PA_UART2 0x021e8000
+#define CSP_BASE_REG_PA_UART3 0x021EC000
+#define CSP_BASE_REG_PA_UART4 0x021F0000
+#define CSP_BASE_REG_PA_UART5 0x021F4000
+#define CSP_BASE_REG_PA_ESDHC2 0x02194000
+#define CSP_BASE_REG_PA_ESDHC3 0x02198000
+
+#define DBG_PORT_SUBTYPE_IMX6 0x000C
+
+// Timers clock sources
+#define SOC_OSC_FREQUENCY_REF_HZ 24000000 // Oscillator frequency 24Mhz
+#define SOC_HIGH_FREQUENCY_REF_HZ 66000000 // High Frequency reference clock 66Mhz
+#define SOC_LOW_FREQ_REF_HZ 32768 // SNVS RTC frequency 32kHz
+
+#define IMX_GPU3D_BASE 0x00130000
+#define IMX_GPU3D_LENGTH 0x4000
+
+#define IMX_GPU2D_BASE 0x00134000
+#define IMX_GPU2D_LENGTH 0x4000
+
+//
+// IOMUX Controller (IOMUXC)
+//
+
+#define IMX_IOMUXC_BASE 0x020E0000
+#define IMX_IOMUXC_LENGTH 0x4000
+
+#define IMX_IOMUXC_TZASC1_BYP 0x1
+#define IMX_IOMUXC_TZASC2_BYP 0x2
+
+//
+// Secure Nonvolatile Storage (SNVS)
+//
+
+#define IMX_SNVS_BASE 0x020CC000
+#define IMX_SNVS_LENGTH 0x4000
+#define IMX_SNVS_IP_ID 0x3E
+#define IMX_SNVS_IRQ 51 // SNVS consolidated interrupt
+
+//
+// IOMUXC Registers
+//
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x020E01F8
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x020E01FC
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x020E0200
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x020E0204
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x020E0208
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x020E020C
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x020E0210
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x020E0214
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 0x020E0218
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 0x020E021C
+
+// define base address of Select Input registers to be one word
+// less than the minimum value so that a valid Select Input value
+// is non-zero.
+#define IOMUXC_SELECT_INPUT_BASE_ADDRESS 0x20E07AC
+
+typedef enum {
+ IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT = 0x20E07B0,
+ IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT = 0x20E07B4,
+ IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT = 0x20E07B8,
+ IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT = 0x20E07BC,
+ IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT = 0x20E07C0,
+ IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT = 0x20E07C4,
+ IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT = 0x20E07C8,
+ IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT = 0x20E07CC,
+ IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT = 0x20E07D0,
+ IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT = 0x20E07D4,
+ IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT = 0x20E07D8,
+ IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT = 0x20E07DC,
+ IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT = 0x20E07E0,
+ IOMUXC_FLEXCAN1_RX_SELECT_INPUT = 0x20E07E4,
+ IOMUXC_FLEXCAN2_RX_SELECT_INPUT = 0x20E07E8,
+ IOMUXC_CCM_PMIC_READY_SELECT_INPUT = 0x20E07F0,
+ IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT = 0x20E07F4,
+ IOMUXC_ECSPI1_MISO_SELECT_INPUT = 0x20E07F8,
+ IOMUXC_ECSPI1_MOSI_SELECT_INPUT = 0x20E07FC,
+ IOMUXC_ECSPI1_SS0_SELECT_INPUT = 0x20E0800,
+ IOMUXC_ECSPI1_SS1_SELECT_INPUT = 0x20E0804,
+ IOMUXC_ECSPI1_SS2_SELECT_INPUT = 0x20E0808,
+ IOMUXC_ECSPI1_SS3_SELECT_INPUT = 0x20E080C,
+ IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT = 0x20E0810,
+ IOMUXC_ECSPI2_MISO_SELECT_INPUT = 0x20E0814,
+ IOMUXC_ECSPI2_MOSI_SELECT_INPUT = 0x20E0818,
+ IOMUXC_ECSPI2_SS0_SELECT_INPUT = 0x20E081C,
+ IOMUXC_ECSPI2_SS1_SELECT_INPUT = 0x20E0820,
+ IOMUXC_ECSPI4_SS0_SELECT_INPUT = 0x20E0824,
+ IOMUXC_ECSPI5_CSPI_CLK_IN_SELECT_INPUT = 0x20E0828,
+ IOMUXC_ECSPI5_MISO_SELECT_INPUT = 0x20E082C,
+ IOMUXC_ECSPI5_MOSI_SELECT_INPUT = 0x20E0830,
+ IOMUXC_ECSPI5_SS0_SELECT_INPUT = 0x20E0834,
+ IOMUXC_ECSPI5_SS1_SELECT_INPUT = 0x20E0838,
+ IOMUXC_ENET_REF_CLK_SELECT_INPUT = 0x20E083C,
+ IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT = 0x20E0840,
+ IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT = 0x20E0844,
+ IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT = 0x20E0848,
+ IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT = 0x20E084C,
+ IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT = 0x20E0850,
+ IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT = 0x20E0854,
+ IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT = 0x20E0858,
+ IOMUXC_ESAI_RX_FS_SELECT_INPUT = 0x20E085C,
+ IOMUXC_ESAI_TX_FS_SELECT_INPUT = 0x20E0860,
+ IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT = 0x20E0864,
+ IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT = 0x20E0868,
+ IOMUXC_ESAI_RX_CLK_SELECT_INPUT = 0x20E086C,
+ IOMUXC_ESAI_TX_CLK_SELECT_INPUT = 0x20E0870,
+ IOMUXC_ESAI_SDO0_SELECT_INPUT = 0x20E0874,
+ IOMUXC_ESAI_SDO1_SELECT_INPUT = 0x20E0878,
+ IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT = 0x20E087C,
+ IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT = 0x20E0880,
+ IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT = 0x20E0884,
+ IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT = 0x20E0888,
+ IOMUXC_HDMI_ICECIN_SELECT_INPUT = 0x20E088C,
+ IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT = 0x20E0890,
+ IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT = 0x20E0894,
+ IOMUXC_I2C1_SCL_IN_SELECT_INPUT = 0x20E0898,
+ IOMUXC_I2C1_SDA_IN_SELECT_INPUT = 0x20E089C,
+ IOMUXC_I2C2_SCL_IN_SELECT_INPUT = 0x20E08A0,
+ IOMUXC_I2C2_SDA_IN_SELECT_INPUT = 0x20E08A4,
+ IOMUXC_I2C3_SCL_IN_SELECT_INPUT = 0x20E08A8,
+ IOMUXC_I2C3_SDA_IN_SELECT_INPUT = 0x20E08AC,
+ IOMUXC_IPU2_SENS1_DATA10_SELECT_INPUT = 0x20E08B0,
+ IOMUXC_IPU2_SENS1_DATA11_SELECT_INPUT = 0x20E08B4,
+ IOMUXC_IPU2_SENS1_DATA12_SELECT_INPUT = 0x20E08B8,
+ IOMUXC_IPU2_SENS1_DATA13_SELECT_INPUT = 0x20E08BC,
+ IOMUXC_IPU2_SENS1_DATA14_SELECT_INPUT = 0x20E08C0,
+ IOMUXC_IPU2_SENS1_DATA15_SELECT_INPUT = 0x20E08C4,
+ IOMUXC_IPU2_SENS1_DATA16_SELECT_INPUT = 0x20E08C8,
+ IOMUXC_IPU2_SENS1_DATA17_SELECT_INPUT = 0x20E08CC,
+ IOMUXC_IPU2_SENS1_DATA18_SELECT_INPUT = 0x20E08D0,
+ IOMUXC_IPU2_SENS1_DATA19_SELECT_INPUT = 0x20E08D4,
+ IOMUXC_IPU2_SENS1_DATA_EN_SELECT_INPUT = 0x20E08D8,
+ IOMUXC_IPU2_SENS1_HSYNC_SELECT_INPUT = 0x20E08DC,
+ IOMUXC_IPU2_SENS1_PIX_CLK_SELECT_INPUT = 0x20E08E0,
+ IOMUXC_IPU2_SENS1_VSYNC_SELECT_INPUT = 0x20E08E4,
+ IOMUXC_KEY_COL5_SELECT_INPUT = 0x20E08E8,
+ IOMUXC_KEY_COL6_SELECT_INPUT = 0x20E08EC,
+ IOMUXC_KEY_COL7_SELECT_INPUT = 0x20E08F0,
+ IOMUXC_KEY_ROW5_SELECT_INPUT = 0x20E08F4,
+ IOMUXC_KEY_ROW6_SELECT_INPUT = 0x20E08F8,
+ IOMUXC_KEY_ROW7_SELECT_INPUT = 0x20E08FC,
+ IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT = 0x20E0900,
+ IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT = 0x20E0904,
+ IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT = 0x20E0908,
+ IOMUXC_SDMA_EVENTS14_SELECT_INPUT = 0x20E090C,
+ IOMUXC_SDMA_EVENTS47_SELECT_INPUT = 0x20E0910,
+ IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 0x20E0914,
+ IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT = 0x20E0918,
+ IOMUXC_UART1_UART_RTS_B_SELECT_INPUT = 0x20E091C,
+ IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT = 0x20E0920,
+ IOMUXC_UART2_UART_RTS_B_SELECT_INPUT = 0x20E0924,
+ IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT = 0x20E0928,
+ IOMUXC_UART3_UART_RTS_B_SELECT_INPUT = 0x20E092C,
+ IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT = 0x20E0930,
+ IOMUXC_UART4_UART_RTS_B_SELECT_INPUT = 0x20E0934,
+ IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT = 0x20E0938,
+ IOMUXC_UART5_UART_RTS_B_SELECT_INPUT = 0x20E093C,
+ IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT = 0x20E0940,
+ IOMUXC_USB_OTG_OC_SELECT_INPUT = 0x20E0944,
+ IOMUXC_USB_H1_OC_SELECT_INPUT = 0x20E0948,
+ IOMUXC_USDHC1_WP_ON_SELECT_INPUT = 0x20E094C,
+ IOMUXC_SELECT_INPUT_UPPER_BOUND = IOMUXC_USDHC1_WP_ON_SELECT_INPUT,
+} IMX_INPUT_SELECT;
+
+#define IOMUXC_GPR_BASE_ADDRESS 0x020E0000
+
+typedef struct{
+ UINT32 GPR0; // 0x00 IOMUXC_GPR0
+ UINT32 GPR1; // 0x04 IOMUXC_GPR1
+ UINT32 GPR2; // 0x08 IOMUXC_GPR2
+ UINT32 GPR3; // 0x0C IOMUXC_GPR3
+ UINT32 GPR4; // 0x10 IOMUXC_GPR4
+ UINT32 GPR5; // 0x14 IOMUXC_GPR5
+ UINT32 GPR6; // 0x18 IOMUXC_GPR6
+ UINT32 GPR7; // 0x1C IOMUXC_GPR7
+ UINT32 GPR8; // 0x20 IOMUXC_GPR8
+ UINT32 GPR9; // 0x24 IOMUXC_GPR9
+ UINT32 GPR10; // 0x28 IOMUXC_GPR10
+ UINT32 GPR11; // 0x2c IOMUXC_GPR11
+ UINT32 GPR12; // 0x30 IOMUXC_GPR12
+ UINT32 GPR13; // 0x34 IOMUXC_GPR13
+ UINT32 Reserved; // 0x38 Reserved
+ UINT32 GPR14; // 0x3C IOMUXC_GPR14; see ERR006687
+} IMX_IOMUXC_GPR_REGISTERS;
+
+typedef enum {
+ IMX_IOMUXC_GPR1_USB_OTG_ID_SEL_ENET_RX_ER,
+ IMX_IOMUXC_GPR1_USB_OTG_ID_SEL_GPIO_1,
+} IMX_IOMUXC_GPR1_USB_OTG_ID_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ACT_CS0 : 1; // 0
+ UINT32 ADDRS0_10 : 2; // 1-2
+ UINT32 ACT_CS1 : 1; // 3
+ UINT32 ADDRS1_10 : 2; // 4-5
+ UINT32 ACT_CS2 : 1; // 6
+ UINT32 ADDRS2_10 : 2; // 7-8
+ UINT32 ACT_CS3 : 1; // 9
+ UINT32 ADDRS3_10 : 2; // 10-11 Active Chip Select and Address Space
+ UINT32 GINT : 1; // 12 Global interrupt "0" bit (connected to ARM IRQ#0 and GPC)
+ UINT32 USB_OTG_ID_SEL : 1; // 13 ''usb_otg_id' pin iomux select control.
+ UINT32 SYS_INT : 1; // 14 PCIe_CTL
+ UINT32 USB_EXP_MODE : 1; // 15 USB Exposure mode
+ UINT32 REF_SSP_EN : 1; // 16 PCIe_PHY - Reference Clock Enable for SS function.
+ UINT32 PU_VPU_MUX : 1; // 17 IPU-1/IPU-2 to VPU signals control.
+ UINT32 TEST_POWERDOWN : 1; // 18 PCIe_PHY - All Circuits Power-Down Control Function.
+ UINT32 MIPI_IPU1_MUX : 1; // 19 MIPI sensor to IPU-1 mux control.
+ UINT32 MIPI_IPU2_MUX : 1; // 20 MIPI sensor to IPU-2 mux control
+ UINT32 ENET_CLK_SEL : 1; // 21 ENET TX reference clock
+ UINT32 EXC_MON : 1; // 22 Exclusive monitor response select of illegal command
+ UINT32 reserved1 : 1; // 23
+ UINT32 MIPI_DPI_OFF : 1; // 24 MIPI DPI shutdown request
+ UINT32 MIPI_COLOR_SW : 1; // 25 MIPI color switch control
+ UINT32 APP_REQ_ENTR_L1 : 1; // 26 PCIe_CTL - Application Request to Enter L1
+ UINT32 APP_READY_ENTR_L23 : 1; // 27 PCIe_CTL - Application Ready to Enter L23
+ UINT32 APP_REQ_EXIT_L1 : 1; // 28 PCIe_CTL - Application Request to Exit L1
+ UINT32 reserved2 : 1; // 29
+ UINT32 APP_CLK_REQ_N : 1; // 30 PCIe_CTL (CLK LOGIC CONTROLLER GLUE) - Indicates that application logic is ready to have reference clock removed.
+ UINT32 CFG_L1_CLK_REMOVAL_EN : 1; // 31 PCIe_CTL (CLK LOGIC CONTROLLER GLUE) - Enable the reference clock removal in L1 state.
+ // MSB
+ };
+} IMX_IOMUXC_GPR1_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 PCS_TX_DEEMPH_GEN1 : 6; // 0-5 PCIe_PHY - This static value sets the launch amplitude of the transmitter when pipe0_tx_swing is set to 1'b0 (default state).
+ UINT32 PCS_TX_DEEMPH_GEN2_3P5DB : 6;// 6-11 PCIe_PHY - This static value sets the Tx driver SWING_FULL value.
+ UINT32 PCS_TX_DEEMPH_GEN2_6DB : 6; // 12-17 PCIe_PHY - This static value sets the Tx driver de-emphasis value in the case where pipe0_tx_deemph is set to 1'b0 and the PHY is running at the Gen2 (6db) rate.
+ UINT32 PCS_TX_SWING_FULL : 7; // 18-24 PCIe_PHY - This static value sets the Tx driver de-emphasis value in the case where pipe0_tx_deemph is set to 1'b1 (the default setting) and the PHY is running at the Gen2 (3p5db) rate.
+ UINT32 PCS_TX_SWING_LOW : 7; // 25-31 PCIe_PHY - This static value sets the Tx driver de-emphasis value in the case where pipe0_tx_deemph is set to 1'b1 (the default setting) and the PHY is running at the Gen1 rate.
+ // MSB
+ };
+} IMX_IOMUXC_GPR8_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 reserved0 : 2; // 0-1
+ UINT32 uSDHC_DBG_MUX : 2; // 2-3 uSDHC debug bus IO mux control
+ UINT32 LOS_LEVEL : 5; // 4-8 PCIe_PHY - Loss-of-Signal Detector Sensitivity Level Control Function: Sets the sensitivity level for the Loss - of - Signal detector.This signal must be set to 0x9
+ UINT32 APPS_PM_XMT_PME : 1; // 9 PCIe_CTL - Wake Up. Used by application logic to wake up the PMC state machine from a D1, D2 or D3 power state.Upon wake - up, the core sends a PM_PME Message
+ UINT32 APP_LTSSM_ENABLE : 1; // 10 PCIe_CTL Driven low by the application after reset to hold the LTSSM in the Detect state until the application is ready.When the application has finished initializing the core configuration registers, it asserts app_ltssm_enable to allow the LTSSM to continue Link establishment.
+ UINT32 APP_INIT_RST : 1; // 11 PCIe_PHY - PCIe_CTL - Request from the application to send a Hot Reset to the downstream device.
+ UINT32 DEVICE_TYPE : 4; // 12-15 PCIe_CTL - Device/Port Type. 0000 PCIE_EP EP Mode 0010 PCIE_RC RC Mode
+ UINT32 APPS_PM_XMT_TURNOFF : 1; // 16 PCIe_CTL - Request from the application to generate a PM_Turn_Off Message.
+ UINT32 DIA_STATUS_BUS_SELECT : 4; // 17-20 PCIe_CTL - used for debug to select what part of diag_status_bus will be reflected on the 32 bits of the iomux
+ UINT32 PCIe_CTL_7 : 3; // 21-23 PCIe control of diagnostic bus select
+ UINT32 ARMP_APB_CLK_EN : 1; // 24 ARM platform APB clock enable
+ UINT32 ARMP_ATB_CLK_EN : 1; // 25 ARM platform ATB clock enable
+ UINT32 ARMP_AHB_CLK_EN : 1; // 26 ARM platform AHB clock enable
+ UINT32 ARMP_IPG_CLK_EN : 1; // 27 ARM platform IPG clock enable
+ UINT32 reserved1 : 4; // 28-31
+ // MSB
+ };
+} IMX_IOMUXC_GPR12_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 reserved1 : 1; // 0
+ UINT32 reserved2 : 1; // 1
+ UINT32 MC_ENV : 1; // 2 Monotonic Counter Enable and Valid
+ UINT32 reserved3 : 1; // 3
+ UINT32 reserved4 : 1; // 4
+ UINT32 DP_EN : 1; // 5 Dumb PMIC Enabled
+ UINT32 TOP : 1; // 6 Turn off System Power
+ UINT32 PWR_GLITCH_EN : 1; // 7 Power Glitch Detection Enable
+ UINT32 reserved5 : 1; // 8
+ UINT32 reserved6 : 1; // 9
+ UINT32 reserved7 : 5; // 10-14
+ UINT32 reserved8 : 1; // 15
+ UINT32 BTN_PRESS_TIME : 2; // 16-17 Button press time out values for PMIC Logic.
+ UINT32 DEBOUNCE : 2; // 18-19 debounce time for the BTN input signal
+ UINT32 ON_TIME : 2; // 20-21 Time after BTN is asserted before pmic_en_b is asserted
+ UINT32 PK_EN : 1; // 22 PMIC On Request Enable
+ UINT32 PK_OVERRIDE : 1; // 23 PMIC On Request Override
+ UINT32 reserved9 : 8; // 24-31
+ // MSB
+ };
+} IMX_SNVS_LPCR_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 MINOR_REV : 8; // 0-7 SNVS block minor version number
+ UINT32 MAJOR_REV : 8; // 8-15 SNVS block major version number
+ UINT32 IP_ID : 16; // 16-31 SNVS block ID (IMX_SNVS_IP_ID)
+ // MSB
+ };
+} IMX_SNVS_HPVIDR1_REG;
+
+typedef struct {
+ UINT32 HPLR; // 0x000 SNVS_HP Lock Register (SNVS_HPLR)
+ UINT32 HPCOMR; // 0x004 SNVS_HP Command Register (SNVS_HPCOMR)
+ UINT32 HPCR; // 0x008 SNVS_HP Control Register (SNVS_HPCR)
+ UINT32 reserved1[2];
+ UINT32 HPSR; // 0x014 SNVS_HP Status Register (SNVS_HPSR)
+ UINT32 reserved2[3];
+ UINT32 HPRTCMR; // 0x024 SNVS_HP Real Time Counter MSB Register (SNVS_HPRTCMR
+ UINT32 HPRTCLR; // 0x028 SNVS_HP Real Time Counter LSB Register (SNVS_HPRTCLR)
+ UINT32 HPTAMR; // 0x02C SNVS_HP Time Alarm MSB Register (SNVS_HPTAMR)
+ UINT32 HPTALR; // 0x030 SNVS_HP Time Alarm LSB Register (SNVS_HPTALR)
+ UINT32 LPLR; // 0x034 SNVS_LP Lock Register (SNVS_LPLR)
+ UINT32 LPCR; // 0x038 SNVS_LP Control Register (SNVS_LPCR)
+ UINT32 reserved3[4];
+ UINT32 LPSR; // 0x04C SNVS_LP Status Register (SNVS_LPSR)
+ UINT32 reserved4[3];
+ UINT32 LPSMCMR; // 0x05C SNVS_LP Secure Monotonic Counter MSB Register (SNVS_LPSMCMR)
+ UINT32 LPSMCLR; // 0x060 SNVS_LP Secure Monotonic Counter LSB Register (SNVS_LPSMCLR)
+ UINT32 reserved5[1];
+ UINT32 LPGPR; // 0x068 SNVS_LP General Purpose Register (SNVS_LPGPR)
+ UINT32 reserved6[739];
+ UINT32 HPVIDR1; // 0xBF8 SNVS_HP Version ID Register 1 (SNVS_HPVIDR1)
+ UINT32 HPVIDR2; // 0xBFC SNVS_HP Version ID Register 2 (SNVS_HPVIDR2)
+} IMX_SNVS_REGISTERS;
+
+//
+// System Reset Controller (SRC)
+//
+
+#define IMX_SRC_BASE 0x020D8000
+#define IMX_SRC_LENGTH 0x4000
+
+//
+// SCR Register Definition
+//
+
+typedef enum {
+ IMX_SCR_WARM_RST_BYPASS_COUNT_DISABLED,
+ IMX_SCR_WARM_RST_BYPASS_COUNT_16,
+ IMX_SCR_WARM_RST_BYPASS_COUNT_32,
+ IMX_SCR_WARM_RST_BYPASS_COUNT_64,
+} IMX_SCR_WARM_RST_BYPASS_COUNT;
+
+typedef enum {
+ IMX_SRC_MASK_WDOG_RST_B_MASKED = 0x5,
+ IMX_SRC_MASK_WDOG_RST_B_NOT_MASKED = 0xA,
+} IMX_SRC_MASK_WDOG_RST;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 warm_reset_enable : 1; // 0 WARM reset enable bit
+ UINT32 sw_gpu_rst : 1; // 1 Software reset for GPU
+ UINT32 sw_vpu_rst : 1; // 2 Software reset for VPU
+ UINT32 sw_ipu1_rst : 1; // 3 Software reset for IPU1
+ UINT32 sw_open_vg_rst : 1; // 4 Software reset for open_vg
+ UINT32 warm_rst_bypass_count : 2; // 5-6 Defines the XTALI cycles to count before bypassing the MMDC acknowledge for WARM reset (IMX_SCR_WARM_RST_BYPASS_COUNT)
+ UINT32 mask_wdog_rst : 4; // 7-10 Mask wdog_rst_b source (IMX_SRC_MASK_WDOG_RST)
+ UINT32 eim_rst : 1; // 11 EIM reset is needed in order to reconfigure the eim chip select.
+ UINT32 sw_ipu2_rst : 1; // 12 Software reset for ipu2
+ UINT32 core0_rst : 1; // 13 Software reset for core0 only.
+ UINT32 core1_rst : 1; // 14 Software reset for core1 only.
+ UINT32 core2_rst : 1; // 15 Software reset for core2 only
+ UINT32 core3_rst : 1; // 16 Software reset for core3 only.
+ UINT32 core0_dbg_rst : 1; // 17 Software reset for core0 debug only.
+ UINT32 core1_dbg_rst : 1; // 18 Software reset for core1 debug only.
+ UINT32 core2_dbg_rst : 1; // 19 Software reset for core2 debug only.
+ UINT32 core3_dbg_rst : 1; // 20 Software reset for core3 debug only.
+ UINT32 cores_dbg_rst : 1; // 21 Software reset for debug of arm platform only.
+ UINT32 core1_enable : 1; // 22 core1 enable
+ UINT32 core2_enable : 1; // 23 core2 enable
+ UINT32 core3_enable : 1; // 24 core3 enable
+ UINT32 dbg_rst_msk_pg : 1; // 25 Do not assert debug resets after power gating event of core
+ UINT32 reserved : 6; // 26-31 reserved
+ // MSB
+ };
+} IMX_SRC_SCR_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 BOOT_CFG1 : 8; // 0-7
+ UINT32 BOOT_CFG2 : 8; // 8-15
+ UINT32 BOOT_CFG3 : 8; // 16-23
+ UINT32 BOOT_CFG4 : 8; // 24-31
+ // MSB
+ };
+} IMX_SRC_SBMR1_REG;
+
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 SEC_COFNIG : 2; // 0-1
+ UINT32 reserved1 : 1; // 2
+ UINT32 DIR_BT_DIS : 1; // 3
+ UINT32 BT_FUSE_SEL : 1; // 4
+ UINT32 reserved2 : 19; // 5-23
+ UINT32 BMOD : 2; // 24-25
+ UINT32 reserved3 : 6; // 26-31
+ // MSB
+ };
+} IMX_SRC_SBMR2_REG;
+
+typedef struct {
+ UINT32 SCR; // 0x00 SRC Control Register (SRC_SCR)
+ UINT32 SBMR1; // 0x04 SRC Boot Mode Register 1 (SRC_SBMR1)
+ UINT32 SRSR; // 0x08 SRC Reset Status Register (SRC_SRSR)
+ UINT32 reserved1[2];
+ UINT32 SISR; // 0x14 SRC Interrupt Status Register (SRC_SISR)
+ UINT32 SIMR; // 0x18 SRC Interrupt Mask Register (SRC_SIMR)
+ UINT32 SBMR2; // 0x1C SRC Boot Mode Register 2 (SRC_SBMR2)
+ UINT32 GPR1; // 0x20 SRC General Purpose Register 1 (SRC_GPR1)
+ UINT32 GPR2; // 0x24 SRC General Purpose Register 2 (SRC_GPR2)
+ UINT32 GPR3; // 0x28 SRC General Purpose Register 3 (SRC_GPR3)
+ UINT32 GPR4; // 0x2C SRC General Purpose Register 4 (SRC_GPR4)
+ UINT32 GPR5; // 0x30 SRC General Purpose Register 4 (SRC_GPR5)
+ UINT32 GPR6; // 0x34 SRC General Purpose Register 4 (SRC_GPR6)
+ UINT32 GPR7; // 0x38 SRC General Purpose Register 4 (SRC_GPR7)
+ UINT32 GPR8; // 0x3C SRC General Purpose Register 4 (SRC_GPR8)
+ UINT32 GPR9; // 0x40 SRC General Purpose Register 4 (SRC_GPR9)
+ UINT32 GPR10; // 0x44 SRC General Purpose Register 4 (SRC_GPR10)
+} IMX_SRC_REGISTERS;
+
+
+//
+// Watchdog (WDOG)
+//
+
+#define IMX_WDOG1_BASE 0x020BC000
+#define IMX_WDOG2_BASE 0x020C0000
+#define IMX_WDOG_LENGTH 0x4000
+
+#define IMX_WDOG_WSR_FEED1 0x5555
+#define IMX_WDOG_WSR_FEED2 0xAAAA
+
+typedef union {
+ UINT16 AsUint16;
+ struct {
+ // LSB
+ UINT16 WDZST : 1; // 0 Watchdog Low Power
+ UINT16 WDBG : 1; // 1 Watchdog DEBUG Enable
+ UINT16 WDE : 1; // 2 Watchdog Enable
+ UINT16 WDT : 1; // 3 WDOG_B Time-out assertion.
+ UINT16 SRS : 1; // 4 Software Reset Signal
+ UINT16 WDA : 1; // 5 WDOG_B assertion
+ UINT16 reserved1 : 1; // 6
+ UINT16 WDW : 1; // 7 Watchdog Disable for Wait
+ UINT16 WT : 8; // 8-15 Watchdog Time-out Field
+ // MSB
+ };
+} IMX_WDOG_WCR_REG;
+
+typedef struct {
+ UINT16 WCR; // 0x0 Watchdog Control Register (WDOG1_WCR)
+ UINT16 WSR; // 0x2 Watchdog Service Register (WDOG1_WSR)
+ UINT16 WRSR; // 0x4 Watchdog Reset Status Register (WDOG1_WRSR)
+ UINT16 WICR; // 0x6 Watchdog Interrupt Control Register (WDOG1_WICR)
+ UINT16 WMCR; // 0x8 Watchdog Miscellaneous Control Register (WDOG1_WMCR)
+} IMX_WDOG_REGISTERS;
+
+//
+// Clock Control Module (CCM)
+//
+
+#define IMX_CCM_BASE 0x020C4000
+#define IMX_CCM_LENGTH 0x4000
+#define IMX_CCM_ANALOG_BASE 0x020C8000
+#define IMX_CCM_ANALOG_LENGTH 0x1000
+
+#define IMX_GPU2D_CORE_CLK_MAX 532000000 // 532Mhz
+#define IMX_GPU3D_CORE_CLK_MAX 540000000 // 540Mhz
+#define IMX_GPU3D_SHADER_CLK_MAX 660000000 // 660Mhz
+
+#define IMX_REF_CLK_24M_FREQ 24000000
+
+typedef enum {
+ IMX_CCM_PLL3_SW_CLK_SEL_PLL3_MAIN_CLK,
+ IMX_CCM_PLL3_SW_CLK_SEL_PLL3_BYPASS_CLK,
+} IMX_CCM_PLL3_SW_CLK_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 pll3_sw_clk_sel : 1; // 0 Selects source to generate pll3_sw_clk
+ UINT32 reserved1 : 1; // 1 reserved
+ UINT32 pll1_sw_clk_sel : 1; // 2 Selects source to generate pll1_sw_clk.
+ UINT32 reserved2 : 5; // 3-7
+ UINT32 step_sel : 1; // 8 Selects the option to be chosen for the step frequency
+ UINT32 pfd_396m_dis_mask : 1; // 9 Mask of 396M PFD auto-disable
+ UINT32 pfd_352m_dis_mask : 1; // 10 Mask of 352M PFD auto-disable.
+ UINT32 pfd_594_dis_mask : 1; // 11 Mask of 594M PFD auto-disable.
+ UINT32 pfd_508m_dis_mask : 1; // 12 Mask of 508M PFD auto-disable
+ UINT32 pfd_454m_dis_mask : 1; // 13 Mask of 454M PFD auto-disable.
+ UINT32 pfd_720m_dis_mask : 1; // 14 Mask of 720M PFD auto-disable.
+ UINT32 pfd_540m_dis_mask : 1; // 15 Mask of 540M PFD auto-disable.
+ UINT32 reserved3 : 16; // 16-31
+ // MSB
+ };
+} IMX_CCM_CCSR_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 arm_podf : 3; // 0-3 Divider for ARM clock root
+ UINT32 reserved : 29; // 3-31
+ // MSB
+ };
+} IMX_CCM_CACRR_REG;
+
+// CBCMR.gpu2d_axi_clk_sel
+typedef enum {
+ IMX_CCM_GPU2D_AXI_CLK_SEL_AXI,
+ IMX_CCM_GPU2D_AXI_CLK_SEL_AHB,
+} IMX_CCM_GPU2D_AXI_CLK_SEL;
+
+// CBCMR.gpu3d_axi_clk_sel
+typedef enum {
+ IMX_CCM_GPU3D_AXI_CLK_SEL_AXI,
+ IMX_CCM_GPU3D_AXI_CLK_SEL_AHB,
+} IMX_CCM_GPU3D_AXI_CLK_SEL;
+
+// CBCMR.gpu2d_core_clk_sel
+typedef enum {
+ IMX_CCM_GPU2D_CORE_CLK_SEL_AXI,
+ IMX_CCM_GPU2D_CORE_CLK_SEL_PLL3_SW,
+ IMX_CCM_GPU2D_CORE_CLK_SEL_PLL2_PFD0,
+ IMX_CCM_GPU2D_CORE_CLK_SEL_PLL2_PFD2,
+} IMX_CCM_GPU2D_CORE_CLK_SEL;
+
+// CBCMR.pre_periph_clk_sel
+typedef enum {
+ IMX_CCM_PRE_PERIPH_CLK_SEL_PLL2,
+ IMX_CCM_PRE_PERIPH_CLK_SEL_PLL2_PFD2,
+ IMX_CCM_PRE_PERIPH_CLK_SEL_PLL2_PFD0,
+ IMX_CCM_PRE_PERIPH_CLK_SEL_PLL2_PFD2_DIV2,
+} IMX_CCM_PRE_PERIPH_CLK_SEL;
+
+// CBCMR.gpu3d_core_clk_sel
+typedef enum {
+ IMX_CCM_GPU3D_CORE_CLK_SEL_MMDC_CH0_AXI,
+ IMX_CCM_GPU3D_CORE_CLK_SEL_PLL3_SW,
+ IMX_CCM_GPU3D_CORE_CLK_SEL_PLL2_PFD1,
+ IMX_CCM_GPU3D_CORE_CLK_SEL_PLL2_PFD2,
+} IMX_CCM_GPU3D_CORE_CLK_SEL;
+
+// CBCMR.gpu3d_shader_clk_sel
+typedef enum {
+ IMX_CCM_GPU3D_SHADER_CLK_SEL_MMDC_CH0_AXI,
+ IMX_CCM_GPU3D_SHADER_CLK_SEL_PLL3_SW,
+ IMX_CCM_GPU3D_SHADER_CLK_SEL_PLL2_PFD1,
+ IMX_CCM_GPU3D_SHADER_CLK_SEL_PLL3_PFD0,
+} IMX_CCM_GPU3D_SHADER_CLK_SEL;
+
+// CBCMR.periph_clk2_sel
+typedef enum {
+ IMX_CCM_PERIPH_CLK2_SEL_PLL3_SW_CLK,
+ IMX_CCM_PERIPH_CLK2_SEL_OSC_CLK,
+ IMX_CCM_PERIPH_CLK2_SEL_PLL2,
+} IMX_CCM_PERIPH_CLK2_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 gpu2d_axi_clk_sel : 1; // 0 Selector for gpu2d_axi clock multiplexer (IMX_CCM_GPU2D_AXI_CLK_SEL)
+ UINT32 gpu3d_axi_clk_sel : 1; // 1 Selector for gpu3d_axi clock multiplexer (IMX_CCM_GPU3D_AXI_CLK_SEL)
+ UINT32 reserved1 : 2; // 2-3
+ UINT32 gpu3d_core_clk_sel : 2; // 4-5 Selector for gpu3d_core clock multiplexer (IMX_CCM_GPU3D_CORE_CLK_SEL)
+ UINT32 reserved2 : 2; // 6-7
+ UINT32 gpu3d_shader_clk_sel : 2; // 8-9 Selector for gpu3d_shader clock multiplexer (IMX_CCM_GPU3D_SHADER_CLK_SEL)
+ UINT32 pcie_axi_clk_sel : 1; // 10 Selector for pcie_axi clock multiplexer
+ UINT32 vdoaxi_clk_sel : 1; // 11 Selector for vdoaxi clock multiplexer
+ UINT32 periph_clk2_sel : 2; // 12-13 Selector for peripheral clk2 clock multiplexer
+ UINT32 vpu_axi_clk_sel : 2; // 14-15 Selector for VPU axi clock multiplexer
+ UINT32 gpu2d_core_clk_sel : 2; // 16-17 Selector for open vg (GPU2D Core) clock multiplexer (IMX_CCM_GPU2D_CORE_CLK_SEL)
+ UINT32 pre_periph_clk_sel : 2; // 18-19 Selector for pre_periph clock multiplexer
+ UINT32 periph2_clk2_sel : 1; // 20 Selector for periph2_clk2 clock multiplexer
+ UINT32 pre_periph2_clk_sel : 2; // 21-22 Selector for pre_periph2 clock multiplexer
+ UINT32 gpu2d_core_clk_podf : 3; // 23-25 Divider for gpu2d_core clock.
+ UINT32 gpu3d_core_podf : 3; // 26-28 Divider for gpu3d_core clock
+ UINT32 gpu3d_shader_podf : 3; // 29-31 Divider for gpu3d_shader clock.
+ // MSB
+ };
+} IMX_CCM_CBCMR_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ssi1_clk_podf : 6; // 0-5 Divider for ssi1 clock podf
+ UINT32 ssi1_clk_pred : 3; // 6-8 Divider for ssi1 clock pred
+ UINT32 esai_clk_pred : 3; // 9-11 Divider for esai clock pred
+ UINT32 reserved1 : 4; // 12-15 Reserved
+ UINT32 ssi3_clk_podf : 6; // 16-21 Divider for ssi3 clock podf
+ UINT32 ssi3_clk_pred : 3; // 22-24 Divider for ssi3 clock pred
+ UINT32 esai_clk_podf : 3; // 25-27 Divider for esai clock podf
+ UINT32 reserved2 : 4; // 28-31 Reserved
+ // MSB
+ };
+} IMX_CCM_CS1CDR_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ssi2_clk_podf : 6; // 0-5 Divider for ssi2 clock podf
+ UINT32 ssi2_clk_pred : 3; // 6-8 Divider for ssi2 clock pred
+ UINT32 ldb_di0_clk_sel : 3; // 9-11 Selector for ldb_di0 clock multiplexer
+ UINT32 ldb_di1_clk_sel : 3; // 12-14 Selector for ldb_di1 clock multiplexer
+ UINT32 reserved1 : 1; // 15 Reserved
+ UINT32 enfc_clk_sel : 2; // 16-17 Selector for enfc clock multiplexer
+ UINT32 enfc_clk_pred : 3; // 18-20 Divider for enfc clock pred divider
+ UINT32 esai_clk_podf : 6; // 21-26 Divider for enfc clock divider
+ UINT32 reserved2 : 5; // 27-31 Reserved
+ // MSB
+ };
+} IMX_CCM_CS2CDR_REG;
+
+typedef enum {
+ IMX_CCM_CCGR_OFF = 0x0, // Clock is off during all modes. Stop enter hardware handshake is disabled.
+ IMX_CCM_CCGR_ON_RUN = 0x1, // Clock is on in run mode, but off in WAIT and STOP modes
+ IMX_CCM_CCGR_ON = 0x3, // Clock is on during all modes, except STOP mode.
+} IMX_CCM_CCGR;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 aips_tz1_clk_enable : 2; // 0-1 aips_tz1 clocks (aips_tz1_clk_enable)
+ UINT32 aips_tz2_clk_enable : 2; // 2-3 aips_tz2 clocks (aips_tz2_clk_enable)
+ UINT32 apbhdma_hclk_enable : 2; // 4-5 apbhdma hclk clock (apbhdma_hclk_enable)
+ UINT32 asrc_clk_enable : 2; // 6-7 asrc clock (asrc_clk_enable)
+ UINT32 caam_secure_mem_clk_enable : 2; // 8-9 caam_secure_mem clock (caam_secure_mem_clk_enable)
+ UINT32 caam_wrapper_aclk_enable : 2; // 10-11 caam_wrapper_aclk clock (caam_wrapper_aclk_enable)
+ UINT32 caam_wrapper_ipg_enable : 2; // 12-13 caam_wrapper_ipg clock (caam_wrapper_ipg_enable)
+ UINT32 can1_clk_enable : 2; // 14-15 can1 clock (can1_clk_enable)
+ UINT32 can1_serial_clk_enable : 2; // 16-17 can1_serial clock (can1_serial_clk_enable)
+ UINT32 can2_clk_enable : 2; // 18-19 can2 clock (can2_clk_enable)
+ UINT32 can2_serial_clk_enable : 2; // 20-21 can2_serial clock (can2_serial_clk_enable)
+ UINT32 arm_dbg_clk_enable : 2; // 22-23 CPU debug clocks (arm_dbg_clk_enable)
+ UINT32 dcic1_clk_enable : 2; // 24-25 dcic 1 clocks (dcic1_clk_enable)
+ UINT32 dcic2_clk_enable : 2; // 26-27 dcic2 clocks (dcic2_clk_enable)
+ UINT32 dtcp_clk_enable : 2; // 28-29 dtcp clocks (dtcp_clk_enable)
+ UINT32 reserved : 2; // 30-31
+ // MSB
+ };
+} IMX_CCM_CCGR0_REG;
+
+// CHSCCDR.ipu1_di0_clk_sel
+typedef enum {
+ IMX_CHSCCDR_IPU1_DI0_CLK_SEL_PREMUX,
+ IMX_CHSCCDR_IPU1_DI0_CLK_SEL_IPP_DI0_CLK,
+ IMX_CHSCCDR_IPU1_DI0_CLK_SEL_IPP_DI1_CLK,
+ IMX_CHSCCDR_IPU1_DI0_CLK_SEL_LDB_DI0_CLK,
+ IMX_CHSCCDR_IPU1_DI0_CLK_SEL_LDB_DI1_CLK,
+} IMX_CHSCCDR_IPU1_DI0_CLK_SEL;
+
+// CHSCCDR.ipu1_di0_podf
+typedef enum {
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_1,
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_2,
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_3,
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_4,
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_5,
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_6,
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_7,
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_8,
+} IMX_CHSCCDR_IPU1_DI0_PODF;
+
+// CHSCCDR.ipu1_di0_pre_clk_sel
+typedef enum {
+ IMX_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MMDC_CH0,
+ IMX_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL3_SW_CLK,
+ IMX_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL5,
+ IMX_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL2_PFD0,
+ IMX_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL2_PFD2,
+ IMX_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL3_PFD1,
+} IMX_CHSCCDR_IPU1_DI0_PRE_CLK_SEL;
+
+// CHSCCDR.ipu1_di1_clk_sel
+typedef enum {
+ IMX_CHSCCDR_IPU1_DI1_CLK_SEL_PREMUX,
+ IMX_CHSCCDR_IPU1_DI1_CLK_SEL_IPP_DI0_CLK,
+ IMX_CHSCCDR_IPU1_DI1_CLK_SEL_IPP_DI1_CLK,
+ IMX_CHSCCDR_IPU1_DI1_CLK_SEL_LDB_DI0_CLK,
+ IMX_CHSCCDR_IPU1_DI1_CLK_SEL_LDB_DI1_CLK,
+} IMX_CHSCCDR_IPU1_DI1_CLK_SEL;
+
+// CHSCCDR.ipu1_di1_podf
+typedef enum {
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_1,
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_2,
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_3,
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_4,
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_5,
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_6,
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_7,
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_8,
+} IMX_CHSCCDR_IPU1_DI1_PODF;
+
+// CHSCCDR.ipu1_di1_pre_clk_sel
+typedef enum {
+ IMX_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MMDC_CH0,
+ IMX_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_PLL3_SW_CLK,
+ IMX_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_PLL5,
+ IMX_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_PLL2_PFD0,
+ IMX_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_PLL2_PFD2,
+ IMX_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_PLL3_PFD1,
+} IMX_CHSCCDR_IPU1_DI1_PRE_CLK_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ipu1_di0_clk_sel : 3; // 0-2 Selector for ipu1 di0 root clock multiplexer
+ UINT32 ipu1_di0_podf : 3; // 3-5 Divider for ipu1_di0 clock divider
+ UINT32 ipu1_di0_pre_clk_sel : 3; // 6-8 Selector for ipu1 di0 root clock pre-multiplexer
+ UINT32 ipu1_di1_clk_sel : 3; // 9-11 Selector for ipu1 di1 root clock multiplexer
+ UINT32 ipu1_di1_podf : 3; // 12-14 Divider for ipu1_di clock divider
+ UINT32 ipu1_di1_pre_clk_sel : 3; // 15-17 Selector for ipu1 di1 root clock pre-multiplexer
+ UINT32 reserved : 14; // 18-31
+ // MSB
+ };
+} IMX_CCM_CHSCCDR_REG;
+
+//
+// NOTE: OPENVG clock cannot be gated without gating GPU2D clock as well.
+// Configure both CG bits (CCM_ANALOG_CCGR1[CG12] and
+// CCM_ANALOG_CCGR3[CG15]) to gate OPENVG.
+//
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ecspi1_clk_enable : 2; // 0-1 ecspi1 clocks (ecspi1_clk_enable)
+ UINT32 ecspi2_clk_enable : 2; // 2-3 ecspi2 clocks (ecspi2_clk_enable)
+ UINT32 ecspi3_clk_enable : 2; // 4-5 ecspi3 clocks (ecspi3_clk_enable)
+ UINT32 ecspi4_clk_enable : 2; // 6-7 ecspi4 clocks (ecspi4_clk_enable)
+ UINT32 ecspi5_clk_enable : 2; // 8-9 ecspi5 clocks (ecspi5_clk_enable)
+ UINT32 enet_clk_enable : 2; // 10-11 enet clock (enet_clk_enable)
+ UINT32 epit1_clk_enable : 2; // 12-13 epit1 clocks (epit1_clk_enable)
+ UINT32 epit2_clk_enable : 2; // 14-15 epit2 clocks (epit2_clk_enable)
+ UINT32 esai_clk_enable : 2; // 16-17 esai clocks (esai_clk_enable)
+ UINT32 reserved1 : 2; // 18-19
+ UINT32 gpt_clk_enable : 2; // 20-21 gpt bus clock (gpt_clk_enable)
+ UINT32 gpt_serial_clk_enable : 2; // 22-23 gpt serial clock (gpt_serial_clk_enable)
+ UINT32 gpu2d_clk_enable : 2; // 24-25 gpu2d clock (gpu2d_clk_enable)
+ UINT32 gpu3d_clk_enable : 2; // 26-27 gpu3d clock (gpu3d_clk_enable)
+ UINT32 reserved2 : 4; // 28-31
+ // MSB
+ };
+} IMX_CCM_CCGR1_REG;
+
+// CBCDR.axi_sel
+typedef enum {
+ IMX_CCM_AXI_SEL_PERIPH_CLK,
+ IMX_CCM_AXI_SEL_AXI_ALT,
+} IMX_CCM_AXI_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 periph2_clk2_podf : 3; // 0-2 Divider for periph2_clk2 podf
+ UINT32 mmdc_ch1_axi_podf : 3; // 3-5 Divider for mmdc_ch1_axi podf
+ UINT32 axi_sel : 1; // 6 AXI clock source select (IMX_CCM_AXI_SEL)
+ UINT32 axi_alt_sel : 1; // 7 AXI alternative clock select
+ UINT32 ipg_podf : 2; // 8-9 Divider for ipg podf.
+ UINT32 ahb_podf : 3; // 10-12 Divider for AHB PODF.
+ UINT32 reserved1 : 3; // 13-15
+ UINT32 axi_podf : 3; // 16-18 Divider for axi podf
+ UINT32 mmdc_ch0_axi_podf : 3; // 19-21 Divider for mmdc_ch0_axi podf.
+ UINT32 reserved2 : 3; // 22-24
+ UINT32 periph_clk_sel : 1; // 25 Selector for peripheral main clock (source of MMDC_CH0_CLK_ROOT).
+ UINT32 periph2_clk_sel : 1; // 16 Selector for peripheral2 main clock (source of mmdc_ch1_clk_root
+ UINT32 periph_clk2_podf : 3; // 27-29 Divider for periph2 clock podf.
+ UINT32 reserved3 : 2; // 30-31
+ // MSB
+ };
+} IMX_CCM_CBCDR_REG;
+
+// CCOSR.CLKO1_SEL
+typedef enum {
+ IMX_CCM_CLKO1_SEL_PLL3_SW_CLK_2,
+ IMX_CCM_CLKO1_SEL_PLL2_MAIN_CLK_2,
+ IMX_CCM_CLKO1_SEL_PLL1_MAIN_CLK_2,
+ IMX_CCM_CLKO1_SEL_PLL5_MAIN_CLK_2,
+ IMX_CCM_CLKO1_SEL_VIDEO_27M_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_AXI_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_ENFC_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_IPU1_DI0_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_IPU1_DI1_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_IPU2_DI0_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_IPU2_DI1_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_AHB_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_IPG_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_PERCLK_ROOT,
+ IMX_CCM_CLKO1_SEL_CKIL_SYNC_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_PLL4_MAIN_CLK,
+} IMX_CCM_CLKO1_SEL;
+
+// CCOSR.CLK_OUT_SEL
+typedef enum {
+ IMX_CCM_CLK_OUT_SEL_CCM_CLKO1,
+ IMX_CCM_CLK_OUT_SEL_CCM_CLKO2,
+} IMX_CCM_CLK_OUT_SEL;
+
+// CCOSR.CLKO2_SEL
+typedef enum {
+ IMX_CCM_CLKO2_SEL_MMDC_CH0_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_MMDC_CH1_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_USDHC4_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_USDHC1_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_GPU2D_AXI_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_WRCK_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_ECSPI_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_GPU3D_AXI_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_USDHC3_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_125M_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_ARM_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_IPU1_HSP_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_IPU2_HSP_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_VDO_AXI_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_OSC_CLK,
+ IMX_CCM_CLKO2_SEL_GPU2D_CORE_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_GPU3D_CORE_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_USDHC2_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_SSI1_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_SSI2_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_SSI3_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_GPU3D_SHADER_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_VPU_AXI_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_CAN_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_LDB_DI0_SERIAL_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_LDB_DI1_SERIAL_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_ESAI_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_ACLK_EIM_SLOW_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_UART_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_SPDIF0_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_SPDIF1_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_HSI_TX_CLK_ROOT,
+} IMX_CCM_CLKO2_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 CLKO1_SEL : 4; // 0-3 Selection of the clock to be generated on CCM_CLKO1 (IMX_CCM_CLKO1_SEL)
+ UINT32 CLKO1_DIV : 3; // 4-6 Setting the divider of CCM_CLKO1
+ UINT32 CLKO1_EN : 1; // 7 Enable of CCM_CLKO1 clock
+ UINT32 CLK_OUT_SEL : 1; // 8 CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks
+ UINT32 reserved1 : 7; // 9-15
+ UINT32 CLKO2_SEL : 5; // 16-20 Selection of the clock to be generated on CCM_CLKO2 (IMX_CCM_CLKO2_SEL)
+ UINT32 CLKO2_DIV : 3; // 21-23 Setting the divider of CCM_CLKO2
+ UINT32 CLKO2_EN : 1; // 24 Enable of CCM_CLKO2 clock
+ UINT32 reserved2 : 7; // 25-31
+ // MSB
+ };
+} IMX_CCM_CCOSR_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ipu1_ipu_clk_enable : 2; // 0-1 ipu1_ipu clock (ipu1_ipu_clk_enable)
+ UINT32 ipu1_ipu_di0_clk_enable : 2; // 2-3 ipu1_di0 clock and pre-clock (ipu1_ipu_di0_clk_enable)
+ UINT32 ipu1_ipu_di1_clk_enable : 2; // 4-5 ipu1_di1 clock and pre-clock (ipu1_ipu_di1_clk_enable)
+ UINT32 ipu2_ipu_clk_enable : 2; // 6-7 ipu2_ipu clock (ipu2_ipu_clk_enable)
+ UINT32 ipu2_ipu_di0_clk_enable : 2; // 8-9 ipu2_di0 clock and pre-clock (ipu2_ipu_di0_clk_enable)
+ UINT32 ipu2_ipu_di1_clk_enable : 2; // 10-11 ipu2_di1 clock and pre-clock (ipu2_ipu_di1_clk_enable)
+ UINT32 ldb_di0_clk_enable : 2; // 12-13 ldb_di0 clock (ldb_di0_clk_enable)
+ UINT32 ldb_di1_clk_enable : 2; // 14-15 ldb_di1 clock (ldb_di1_clk_enable)
+ UINT32 mipi_core_cfg_clk_enable : 2; // 16-17 mipi_core_cfg clock (mipi_core_cfg_clk_enable)
+ UINT32 mlb_clk_enable : 2; // 18-19 mlb clock (mlb_clk_enable)
+ UINT32 mmdc_core_aclk_fast_core_p0_enable : 2; // 20-21 mmdc_core_aclk_fast_core_p0 clock (mmdc_core_aclk_fast_core_p0_enable)
+ UINT32 reserved1 : 2; // 22-23
+ UINT32 mmdc_core_ipg_clk_p0_enable : 2; // 24-25 mmdc_core_ipg_clk_p0 clock (mmdc_core_ipg_clk_p0_enable)
+ UINT32 reserved2 : 2; // 26-27
+ UINT32 ocram_clk_enable : 2; // 28-29 ocram clock (ocram_clk_enable)
+ UINT32 openvgaxiclk_clk_root_enable : 2; // 30-31 openvgaxiclk clock (openvgaxiclk_clk_root_enable)
+ // MSB
+ };
+} IMX_CCM_CCGR3_REG;
+
+typedef struct {
+ UINT32 CCR; // 0x00 CCM Control Register (CCM_CCR)
+ UINT32 CCDR; // 0x04 CCM Control Divider Register (CCM_CCDR)
+ UINT32 CSR; // 0x08 CCM Status Register (CCM_CSR)
+ UINT32 CCSR; // 0x0C CCM Clock Switcher Register (CCM_CCSR)
+ UINT32 CACRR; // 0x10 CCM Arm Clock Root Register (CCM_CACRR)
+ UINT32 CBCDR; // 0x14 CCM Bus Clock Divider Register (CCM_CBCDR)
+ UINT32 CBCMR; // 0x18 CCM Bus Clock Multiplexer Register (CCM_CBCMR)
+ UINT32 CSCMR1; // 0x1C CCM Serial Clock Multiplexer Register 1 (CCM_CSCMR1)
+ UINT32 CSCMR2; // 0x20 CCM Serial Clock Multiplexer Register 2 (CCM_CSCMR2)
+ UINT32 CSCDR1; // 0x24 CCM Serial Clock Divider Register 1 (CCM_CSCDR1)
+ UINT32 CS1CDR; // 0x28 CCM SSI1 Clock Divider Register (CCM_CS1CDR)
+ UINT32 CS2CDR; // 0x2C CCM SSI2 Clock Divider Register (CCM_CS2CDR)
+ UINT32 CDCDR; // 0x30 CCM D1 Clock Divider Register (CCM_CDCDR)
+ UINT32 CHSCCDR; // 0x34 CCM HSC Clock Divider Register (CCM_CHSCCDR)
+ UINT32 CSCDR2; // 0x38 CCM Serial Clock Divider Register 2 (CCM_CSCDR2)
+ UINT32 CSCDR3; // 0x3C CCM Serial Clock Divider Register 3 (CCM_CSCDR3)
+ UINT32 reserved1[2];
+ UINT32 CDHIPR; // 0x48 CCM Divider Handshake In-Process Register (CCM_CDHIPR)
+ UINT32 reserved2[2];
+ UINT32 CLPCR; // 0x54 CCM Low Power Control Register (CCM_CLPCR)
+ UINT32 CISR; // 0x58 CCM Interrupt Status Register (CCM_CISR)
+ UINT32 CIMR; // 0x5C CCM Interrupt Mask Register (CCM_CIMR)
+ UINT32 CCOSR; // 0x60 CCM Clock Output Source Register (CCM_CCOSR)
+ UINT32 CGPR; // 0x64 CCM General Purpose Register (CCM_CGPR)
+ UINT32 CCGR[7]; // 0x68-7C CCM Clock Gating Register 0-6 (CCM_CCGR0-CCM_CCGR6)
+ UINT32 reserved3[1];
+ UINT32 CMEOR; // 0x88 CCM Module Enable Override Register (CCM_CMEOR)
+} IMX_CCM_REGISTERS;
+
+//
+// CCM Analog
+//
+
+typedef enum {
+ IMX_PLL_BYPASS_CLK_SRC_REF_CLK_24M,
+ IMX_PLL_BYPASS_CLK_SRC_CLK1,
+ IMX_PLL_BYPASS_CLK_SRC_CLK2,
+ IMX_PLL_BYPASS_CLK_SRC_XOR,
+} IMX_PLL_BYPASS_CLK_SRC;
+
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 DIV_SELECT : 7; // 0-6 Valid range for divider value: 54-108. Fout = Fin * div_select/2.0
+ UINT32 reserved1 : 5; // 7-11
+ UINT32 POWERDOWN : 1; // 12 Powers down the PLL.
+ UINT32 ENABLE: 1; // 13 Enable the clock output.
+ UINT32 BYPASS_CLK_SRC : 2; // 14-15 Determines the bypass and PLL reference clock source.
+ UINT32 BYPASS : 1; // 16 Bypass the PLL.
+ UINT32 LVDS_SEL : 1; // 17 Analog Debug Bit
+ UINT32 LVDS_24MHZ_SEL : 1; // 18 Analog Debug Bit
+ UINT32 reserved2 : 1; // 19 PLL_SEL (Reserved)
+ UINT32 reserved3 : 11; // 20-30
+ UINT32 LOCK : 1; // 31 1 - PLL is currently locked. 0 - PLL is not currently locked.
+ // MSB
+ };
+} IMX_CCM_ANALOG_PLL_ARM_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 DIV_SELECT : 1; // 0 0 - Fout=Fref*20; 1 - Fout=Fref*22.
+ UINT32 reserved1 : 11; // 1-11
+ UINT32 POWERDOWN : 1; // 12 Powers down the PLL.
+ UINT32 ENABLE : 1; // 13 Enable PLL output
+ UINT32 BYPASS_CLK_SRC : 2; // 14-15 Determines the bypass source.
+ UINT32 BYPASS : 1; // 16 Bypass the PLL.
+ UINT32 reserved2 : 1; // 17
+ UINT32 PFD_OFFSET_EN : 1; // 18 Enables an offset in the phase frequency detector
+ UINT32 reserved3 : 12; // 19-30
+ UINT32 LOCK : 1; // 31 1 - PLL is currently locked; 0 - PLL is not currently locked.
+ // MSB
+ };
+} IMX_CCM_ANALOG_PLL_SYS_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 DIV_SELECT : 2; // 0-1 - Fout=Fref*20; 1 - Fout=Fref*22.
+ UINT32 reserved1 : 4; // 2-5
+ UINT32 EN_USB_CLKS : 1; // 6 Powers the 9-phase PLL outputs for USBPHYn
+ UINT32 reserved2 : 5; // 7-11
+ UINT32 POWER : 1; // 12 Powers up the PLL.
+ UINT32 ENABLE : 1; // 13 Enable the PLL clock output
+ UINT32 BYPASS_CLK_SRC : 2; // 14-15 Determines the bypass source
+ UINT32 BYPASS : 1; // 16 Bypass the PLL.
+ UINT32 reserved3 : 14; // 17-30
+ UINT32 LOCK : 1; // 31 1 - PLL is currently locked
+ // MSB
+ };
+} IMX_CCM_ANALOG_PLL_USB1_REG;
+
+typedef enum {
+ IMX_POST_DIV_SELECT_DIVIDE_4,
+ IMX_POST_DIV_SELECT_DIVIDE_2,
+ IMX_POST_DIV_SELECT_DIVIDE_1,
+} IMX_CCM_PLL_VIDEO_CTRL_POST_DIV_SELECT;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 DIV_SELECT : 7; // 0-6 This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54
+ UINT32 Reserved1 : 5; // 7-11
+ UINT32 POWERDOWN : 1; // 12 Powers down the PLL
+ UINT32 ENABLE : 1; // 13 Enalbe PLL output
+ UINT32 BYPASS_CLK_SRC : 2; // 14-15 Determines the bypass source
+ UINT32 BYPASS : 1; // 16 Bypass the PLL
+ UINT32 Reserved2 : 1; // 17
+ UINT32 PFD_OFFSET_EN : 1; // 18 Enables an offset in the phase frequency detector
+ UINT32 POST_DIV_SELECT : 2; // 19-20 These bits implement a divider after the PLL, but before the enable and bypass mux.
+ UINT32 Reserved3 : 1; // 21
+ UINT32 Reserved4 : 9; // 22-30 Always set to zero
+ UINT32 LOCK : 1; // 31 PLL is/not currently locked
+ // MSB
+ };
+} IMX_CCM_PLL_VIDEO_CTRL_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 PFD0_FRAC : 6; // 0-5 fractional divide value. The resulting frequency shall be 528*18/PFD0_FRAC where PFD0_FRAC is in the range 12-35.
+ UINT32 PFD0_STABLE : 1; // 6
+ UINT32 PFD0_CLKGATE : 1; // 7 Set to 1 to gate ref_pfd0
+ UINT32 PFD1_FRAC : 6; // 8-13 fractional divide value
+ UINT32 PFD1_STABLE : 1; // 14
+ UINT32 PFD1_CLKGATE : 1; // 15 Set to 1 to gate ref_pfd1
+ UINT32 PFD2_FRAC : 6; // 16-21 fractional divide value
+ UINT32 PFD2_STABLE : 1; // 22
+ UINT32 PFD2_CLKGATE : 1; // 23 Set to 1 to gate ref_pfd2
+ UINT32 PFD3_FRAC : 6; // 24-29 fractional divide value
+ UINT32 PFD3_STABLE : 1; // 30
+ UINT32 PFD3_CLKGATE : 1; // 31 Set to 1 to gate ref_pfd3
+ // MSB
+ };
+} IMX_CCM_PFD_480_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 PFD0_FRAC : 6; // 0-5 fractional divide value. The resulting frequency shall be 528*18/PFD0_FRAC where PFD0_FRAC is in the range 12-35.
+ UINT32 PFD0_STABLE : 1; // 6
+ UINT32 PFD0_CLKGATE : 1; // 7 Set to 1 to gate ref_pfd0
+ UINT32 PFD1_FRAC : 6; // 8-13 fractional divide value
+ UINT32 PFD1_STABLE : 1; // 14
+ UINT32 PFD1_CLKGATE : 1; // 15 Set to 1 to gate ref_pfd1
+ UINT32 PFD2_FRAC : 6; // 16-21 fractional divide value
+ UINT32 PFD2_STABLE : 1; // 22
+ UINT32 PFD2_CLKGATE : 1; // 23 Set to 1 to gate ref_pfd2
+ UINT32 reserved : 8; // 24-31
+ // MSB
+ };
+} IMX_CCM_PFD_528_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 REG0_TARG : 5; // 0-4 target voltage for the ARM core power domain
+ UINT32 reserved1 : 4; // 5-8
+ UINT32 REG1_TARG : 5; // 9-13 target voltage for the VPU/GPU power domain
+ UINT32 reserved2 : 4; // 14-17
+ UINT32 REG2_TARG : 5; // 18-22 target voltage for the SOC power domain
+ UINT32 reserved3 : 6; // 23-28
+ UINT32 FET_ODRIVE : 1; // 29 increases the gate drive on power gating FET
+ UINT32 reserved4 : 2; // 30-31
+ // MSB
+ };
+} IMX_PMU_REG_CORE_REG;
+
+typedef enum {
+ PLL_ENET_DIV_SELECT_25MHZ = 0,
+ PLL_ENET_DIV_SELECT_50MHZ = 1,
+ PLL_ENET_DIV_SELECT_100MHZ = 2,
+ PLL_ENET_DIV_SELECT_125MHZ = 3,
+} CCM_ANALOG_PLL_ENET_DIV_SELECT;
+
+//
+// CCM ANALOG PLL Ethernet(n) register
+//
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ unsigned DIV_SELECT : 2; // 0-1
+ unsigned Zero1 : 5; // 2-6
+ unsigned Reserved1 : 5; // 7-11
+ unsigned POWERDOWN : 1; // 12
+ unsigned ENABLE : 1; // 13
+ unsigned BYPASS_CLK_SRC : 2; // 14-15
+ unsigned BYPASS : 1; // 16
+ unsigned Reserved2 : 1; // 17
+ unsigned PFD_OFFSET_EN : 1; // 18
+ unsigned ENABLE_125M : 1; // 19
+ unsigned ENABLE_100M : 1; // 20
+ unsigned Zero2 : 10; // 21-30
+ unsigned LOCK : 1; // 31
+ // MSB
+ };
+} IMX_CCM_ANALOG_PLL_ENET_REG;
+
+//
+// CCM ANALOG PLL Ethernet(n) register
+//
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ unsigned LVDS1_CLK_SEL : 5; // 0-4
+ unsigned LVDS2_CLK_SEL : 5; // 5-9
+ unsigned LVDSCLK1_OBEN : 1; // 10
+ unsigned LVDSCLK2_OBEN : 1; // 11
+ unsigned LVDSCLK1_IBEN : 1; // 12
+ unsigned LVDSCLK2_IBEN : 1; // 13
+ unsigned Reserved0 : 15; // 14-28
+ unsigned IRQ_TEMPSENSE : 1; // 29
+ unsigned IRQ_ANA_BO : 1; // 30
+ unsigned IRQ_DIG_BO : 1; // 31
+ // MSB
+ };
+} IMX_CCM_ANALOG_MISC1_REG;
+
+typedef struct {
+ UINT32 PLL_ARM; // 0x000 Analog ARM PLL control Register (CCM_ANALOG_PLL_ARM)
+ UINT32 PLL_ARM_SET; // 0x004 Analog ARM PLL control Register (CCM_ANALOG_PLL_ARM_SET)
+ UINT32 PLL_ARM_CLR; // 0x008 Analog ARM PLL control Register (CCM_ANALOG_PLL_ARM_CLR)
+ UINT32 PLL_ARM_TOG; // 0x00C Analog ARM PLL control Register (CCM_ANALOG_PLL_ARM_TOG)
+ UINT32 PLL_USB1; // 0x010 Analog USB1 480MHz PLL Control Register (CCM_ANALOG_PLL_USB1)
+ UINT32 PLL_USB1_SET; // 0x014 Analog USB1 480MHz PLL Control Register (CCM_ANALOG_PLL_USB1_SET)
+ UINT32 PLL_USB1_CLR; // 0x018 Analog USB1 480MHz PLL Control Register (CCM_ANALOG_PLL_USB1_CLR)
+ UINT32 PLL_USB1_TOG; // 0x01C Analog USB1 480MHz PLL Control Register (CCM_ANALOG_PLL_USB1_TOG)
+ UINT32 PLL_USB2; // 0x020 Analog USB2 480MHz PLL Control Register (CCM_ANALOG_PLL_USB2)
+ UINT32 PLL_USB2_SET; // 0x024 Analog USB2 480MHz PLL Control Register (CCM_ANALOG_PLL_USB2_SET)
+ UINT32 PLL_USB2_CLR; // 0x028 Analog USB2 480MHz PLL Control Register (CCM_ANALOG_PLL_USB2_CLR)
+ UINT32 PLL_USB2_TOG; // 0x02C Analog USB2 480MHz PLL Control Register (CCM_ANALOG_PLL_USB2_TOG)
+ UINT32 PLL_SYS; // 0x030 Analog System PLL Control Register (CCM_ANALOG_PLL_SYS)
+ UINT32 PLL_SYS_SET; // 0x034 Analog System PLL Control Register (CCM_ANALOG_PLL_SYS_SET)
+ UINT32 PLL_SYS_CLR; // 0x038 Analog System PLL Control Register (CCM_ANALOG_PLL_SYS_CLR)
+ UINT32 PLL_SYS_TOG; // 0x03C Analog System PLL Control Register (CCM_ANALOG_PLL_SYS_CLR)
+ UINT32 PLL_SYS_SS; // 0x040 528MHz System PLL Spread Spectrum Register (CCM_ANALOG_PLL_SYS_SS)
+ UINT32 reserved1[3];
+ UINT32 PLL_SYS_NUM; // 0x050 Numerator of 528MHz System PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_SYS_NUM)
+ UINT32 reserved2[3];
+ UINT32 PLL_SYS_DENOM; // 0x060 Denominator of 528MHz System PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_SYS_DENOM)
+ UINT32 reserved3[3];
+ UINT32 PLL_AUDIO; // 0x070 Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIO)
+ UINT32 PLL_AUDIO_SET; // 0x074 Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIO_SET)
+ UINT32 PLL_AUDIO_CLR; // 0x078 Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIO_CLR)
+ UINT32 PLL_AUDIO_TOG; // 0x07C Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIO_TOG)
+ UINT32 PLL_AUDIO_NUM; // 0x080 Numerator of Audio PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_AUDIO_NUM)
+ UINT32 reserved4[3];
+ UINT32 PLL_AUDIO_DENOM; // 0x090 Denominator of Audio PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_AUDIO_DENOM)
+ UINT32 reserved5[3];
+ UINT32 PLL_VIDEO; // 0x0A0 Analog Video PLL control Register (CCM_ANALOG_PLL_VIDEO)
+ UINT32 PLL_VIDEO_SET; // 0x0A4 Analog Video PLL control Register (CCM_ANALOG_PLL_VIDEO_SET)
+ UINT32 PLL_VIDEO_CLR; // 0x0A8 Analog Video PLL control Register (CCM_ANALOG_PLL_VIDEO_CLR)
+ UINT32 PLL_VIDEO_TOG; // 0x0AC Analog Video PLL control Register (CCM_ANALOG_PLL_VIDEO_TOG)
+ UINT32 PLL_VIDEO_NUM; // 0x0B0 Numerator of Video PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_VIDEO_NUM)
+ UINT32 reserved6[3];
+ UINT32 PLL_VIDEO_DENOM; // 0x0C0 Denominator of Video PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_VIDEO_DENOM)
+ UINT32 reserved7[3];
+ UINT32 PLL_MLB; // 0x0D0 MLB PLL Control Register (CCM_ANALOG_PLL_MLB)
+ UINT32 PLL_MLB_SET; // 0x0D4 MLB PLL Control Register (CCM_ANALOG_PLL_MLB_SET)
+ UINT32 PLL_MLB_CLR; // 0x0D8 MLB PLL Control Register (CCM_ANALOG_PLL_MLB_CLR)
+ UINT32 PLL_MLB_TOG; // 0x0DC MLB PLL Control Register (CCM_ANALOG_PLL_MLB_TOG)
+ UINT32 PLL_ENET; // 0x0E0 Analog ENET PLL Control Register (CCM_ANALOG_PLL_ENET)
+ UINT32 PLL_ENET_SET; // 0x0E4 Analog ENET PLL Control Register (CCM_ANALOG_PLL_ENET_SET)
+ UINT32 PLL_ENET_CLR; // 0x0E8 Analog ENET PLL Control Register (CCM_ANALOG_PLL_ENET_CLR)
+ UINT32 PLL_ENET_TOG; // 0x0EC Analog ENET PLL Control Register (CCM_ANALOG_PLL_ENET_TOG)
+ UINT32 PFD_480; // 0x0F0 480MHz Clock (PLL3) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_480)
+ UINT32 PFD_480_SET; // 0x0F4 480MHz Clock (PLL3) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_480_SET)
+ UINT32 PFD_480_CLR; // 0x0F8 480MHz Clock (PLL3) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_480_CLR)
+ UINT32 PFD_480_TOG; // 0x0FC 480MHz Clock (PLL3) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_480_TOG)
+ UINT32 PFD_528; // 0x100 528MHz Clock (PLL2) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_528)
+ UINT32 PFD_528_SET; // 0x104 528MHz Clock (PLL2) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_528_SET)
+ UINT32 PFD_528_CLR; // 0x108 528MHz Clock (PLL2) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_528_CLR)
+ UINT32 PFD_528_TOG; // 0x10C 528MHz Clock (PLL2) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_528_TOG)
+ UINT32 PMU_REG_1P1; // 0x110 Regulator 1P1 Register (PMU_REG_1P1)
+ UINT32 PMU_REG_1P1_SET; // 0x114
+ UINT32 PMU_REG_1P1_CLR; // 0x118
+ UINT32 PMU_REG_1P1_TOG; // 0x11C
+ UINT32 PMU_REG_3P0; // 0X120 Regulator 3P0 Register (PMU_REG_3P0)
+ UINT32 PMU_REG_3P0_SET; // 0x124
+ UINT32 PMU_REG_3P0_CLR; // 0x128
+ UINT32 PMU_REG_3P0_TOG; // 0x12C
+ UINT32 PMU_REG_2P5; // 0x130 Regulator 2P5 Register (PMU_REG_2P5)
+ UINT32 PMU_REG_2P5_SET; // 0x134
+ UINT32 PMU_REG_2P5_CLR; // 0x138
+ UINT32 PMU_REG_2P5_TOG; // 0x13C
+ UINT32 PMU_REG_CORE; // 0x140 Digital Regulator Core Register (PMU_REG_CORE)
+ UINT32 PMU_REG_CORE_SET; // 0x144
+ UINT32 PMU_REG_CORE_CLR; // 0x148
+ UINT32 PMU_REG_CORE_TOG; // 0x14C
+ UINT32 MISC0; // 0x150 Miscellaneous Register 0 (CCM_ANALOG_MISC0)
+ UINT32 MISC0_SET; // 0x154 Miscellaneous Register 0 (CCM_ANALOG_MISC0_SET)
+ UINT32 MISC0_CLR; // 0x158 Miscellaneous Register 0 (CCM_ANALOG_MISC0_CLR)
+ UINT32 MISC0_TOG; // 0x15C Miscellaneous Register 0 (CCM_ANALOG_MISC0_TOG)
+ UINT32 MISC1; // 0x160 Miscellaneous Register 1 (CCM_ANALOG_MISC1)
+ UINT32 MISC1_SET; // 0x164 Miscellaneous Register 1 (CCM_ANALOG_MISC1_SET)
+ UINT32 MISC1_CLR; // 0x168 Miscellaneous Register 1 (CCM_ANALOG_MISC1_CLR)
+ UINT32 MISC1_TOG; // 0x16C Miscellaneous Register 1 (CCM_ANALOG_MISC1_TOG)
+ UINT32 MISC2; // 0x170 Miscellaneous Register 2 (CCM_ANALOG_MISC2)
+ UINT32 MISC2_SET; // 0x174 Miscellaneous Register 2 (CCM_ANALOG_MISC2_SET)
+ UINT32 MISC2_CLR; // 0x178 Miscellaneous Register 2 (CCM_ANALOG_MISC2_CLR)
+ UINT32 MISC2_TOG; // 0x17C Miscellaneous Register 2 (CCM_ANALOG_MISC2_TOG)
+} IMX_CCM_ANALOG_REGISTERS;
+
+//
+// General Power Controller (GPC)
+//
+
+#define IMX_GPC_BASE 0x020DC000
+#define IMX_GPC_LENGTH 0x1000
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 PCR : 1; // 0 Power Control
+ UINT32 reserved : 31; // 1-31
+ // MSB
+ };
+} IMX_GPC_PGC_PGCR_REG;
+
+#define IMX_GPC_PGC_PUPSCR_SW_DEFAULT 1
+#define IMX_GPC_PGC_PUPSCR_SW2ISO_DEFAULT 0xf
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 SW : 6; // 0-5 number of IPG clock cycles before asserting power toggle on/off signal (switch_b)
+ UINT32 reserved1 : 2; // 6-7
+ UINT32 SW2ISO : 6; // 8-13 IPG clock cycles before negating isolation
+ UINT32 reserved2 : 18; // 14-31
+ // MSB
+ };
+} IMX_GPC_PGC_PUPSCR_REG;
+
+#define IMX_GPC_PGC_PDNSCR_ISO_DEFAULT 1
+#define IMX_GPC_PGC_PDNSCR_ISO2SW_DEFAULT 1
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ISO : 6; // 0-5 number of IPG clocks before isolation
+ UINT32 reserved1 : 2; // 6-7
+ UINT32 ISO2SW : 6; // 8-13 number of IPG clocks before negating power toggle on/off signal (switch_b)
+ UINT32 reserved2 : 18; // 14-31
+ // MSB
+ };
+} IMX_GPC_PGC_PDNSCR_REG;
+
+typedef struct {
+ UINT32 CTRL; // 0x0 PGC Control Register (PGC_GPU/CPU_CTRL)
+ UINT32 PUPSCR; // 0x4 Power Up Sequence Control Register (PGC_GPU/CPU_PUPSCR)
+ UINT32 PDNSCR; // 0x8 Pull Down Sequence Control Register (PGC_GPU/CPU_PDNSCR)
+ UINT32 SR; // 0xC Power Gating Controller Status Register (PGC_GPU/CPU_SR)
+} IMX_GPC_PGC_REGISTERS;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 gpu_vpu_pdn_req : 1; // 0 GPU/VPU Power Down request. Self-cleared bit.
+ UINT32 gpu_vpu_pup_req : 1; // 1 GPU/VPU Power Up request. Self-cleared bit.
+ UINT32 reserved1 : 14; // 2-15
+ UINT32 DVFS0CR : 1; // 16 DVFS0 (ARM) Change request (bit is read-only)
+ UINT32 reserved2 : 4; // 17-20
+ UINT32 GPCIRQM : 1; // 21 GPC interrupt/event masking
+ UINT32 reserved3 : 10; // 22-31
+ // MSB
+ };
+} IMX_GPC_CNTR_REG;
+
+typedef struct {
+ UINT32 CNTR; // 0x000 GPC Interface control register (GPC_CNTR)
+ UINT32 PGR; // 0x004 GPC Power Gating Register (GPC_PGR)
+ UINT32 IMR1; // 0x008 IRQ masking register 1 (GPC_IMR1)
+ UINT32 IMR2; // 0x00C IRQ masking register 2 (GPC_IMR2)
+ UINT32 IMR3; // 0x010 IRQ masking register 3 (GPC_IMR3)
+ UINT32 IMR4; // 0x014 IRQ masking register 4 (GPC_IMR4)
+ UINT32 ISR1; // 0x018 IRQ status resister 1 (GPC_ISR1)
+ UINT32 ISR2; // 0x01C IRQ status resister 2 (GPC_ISR2)
+ UINT32 ISR3; // 0x020 IRQ status resister 3 (GPC_ISR3)
+ UINT32 ISR4; // 0x024 IRQ status resister 4 (GPC_ISR4)
+ UINT32 reserved1[142];
+ IMX_GPC_PGC_REGISTERS PGC_GPU; // 0x260-0x26C GPU PGC Control
+ UINT32 reserved2[12];
+ IMX_GPC_PGC_REGISTERS PGC_CPU; // 0x2A0-0x2AC CPU PGC Control
+} IMX_GPC_REGISTERS;
+
+//
+// Ethernet controller (ENET)
+//
+
+#define IMX_ENET_BASE 0x02188000
+#define IMX_ENET_LENGTH 0x4000
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 RESET : 1; // 0 Ethernet MAC Reset
+ UINT32 ETHEREN : 1; // 1 Ethernet Enable
+ UINT32 MAGICEN : 1; // 2 Magic Packet Detection Enable
+ UINT32 SLEEP : 1; // 3 Sleep Mode Enable
+ UINT32 EN1588 : 1; // 4 EN1588 Enable
+ UINT32 SPEED : 1; // 5 Selects between 10/100 and 1000 Mbps modes of operation
+ UINT32 DBGEN : 1; // 6 Debug Enable
+ UINT32 STOPEN : 1; // 7 STOPEN Signal Control
+ UINT32 DBSWP : 1; // 8 Descriptor Byte Swapping Enable
+ UINT32 reserved1 : 3; // 9-11
+ UINT32 reserved2 : 20; // 12-31 This field must be set to F_0000h
+ // MSB
+ };
+} IMX_ENET_ECR_REG;
+
+typedef struct {
+ UINT32 reserved0; // 0
+ UINT32 EIR; // 4
+ UINT32 EIMR; // 8
+ UINT32 reserved1; // Ch
+ UINT32 RDAR; // 10h
+ UINT32 TDAR; // 14h
+ UINT32 reserved2[3]; // 18h - 20h
+ UINT32 ECR; // 24h Ethernet Control Register (ENET_ECR)
+ UINT32 reserved3[6]; // 28h - 3Ch
+ UINT32 MMFR; // 40h
+ UINT32 MSCR; // 44h
+ UINT32 reserved4[7]; // 48h - 60h
+ UINT32 MIBC; // 64h
+ UINT32 reserved5[7]; //
+ UINT32 RCR; // 84h
+ UINT32 reserved6[15]; //
+ UINT32 TCR; // C4h
+ UINT32 reserved7[7];
+ UINT32 PALR; // E4h
+ UINT32 PAUR; // E8h
+ UINT32 OPD; // ECh
+ UINT32 reserved8[322];
+} IMX_ENET_REGISTERS;
+
+//
+// GPIO Controller (GPIO)
+//
+
+#define IMX_GPIO_BASE 0x0209C000
+#define IMX_GPIO_LENGTH (7 * 0x4000)
+
+//
+// USB CORE (EHCI)
+//
+
+#define IMX_USBCORE_BASE 0x02184000
+#define IMX_USBCORE_LENGTH 0x200
+#define IMX_USBCMD_OFFSET 0x140
+#define IMX_USBMODE_OFFSET 0x1A8
+
+//
+// To do:
+// - Add the USB Core register file
+//
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 RS : 1; // 0 Run/Stop (RS) . Read/Write. Default 0b. 1=Run. 0=Stop.
+ UINT32 RST : 1; // 1 Controller Reset (RESET) - Read/Write.
+ UINT32 FS_1 : 2; // 2-3 Frame List Size (Read/Write or Read Only). Default 000b.
+ UINT32 PSE : 1; // 4 Periodic Schedule Enable- Read/Write. Default 0b.
+ UINT32 ASE : 1; // 5 Asynchronous Schedule Enable Read/Write. Default 0b.
+ UINT32 IAA : 1; // 6 Interrupt on Async Advance Doorbell Read/Write.
+ UINT32 reserved1 : 1; // 7
+ UINT32 ASP : 2; // 8-9 Asynchronous Schedule Park Mode Count (OPTIONAL) . Read/Write.
+ UINT32 reserved2 : 1; // 10 Reserved. These bits are reserved and should be set to zero.
+ UINT32 ASPE : 1; // 11 Asynchronous Schedule Park Mode Enable (OPTIONAL) . Read/Write.
+ UINT32 ATDTW : 1; // 12 Add dTD TripWire C Read/Write. [device mode only]
+ UINT32 SUTW : 1; // 13 Setup TripWire C Read/Write. [device mode only]
+ UINT32 reserved3 : 1; // 14
+ UINT32 FS2 : 1; // 15 Frame List Size - (Read/Write or Read Only). [host mode only]
+ UINT32 ITC : 8; // 16-23 Interrupt Threshold Control Read/Write. Default 08h.
+ UINT32 reserved : 8; // 24-31 Reserved. These bits are reserved and should be set to zero.
+ // LSB
+ };
+} USB_USBCMD_REG;
+
+typedef enum {
+ IMX_USBMODE_IDLE = 0,
+ IMX_USBMODE_DEVICE = 2,
+ IMX_USBMODE_HOST = 3,
+} IMX_USBMODE_CM;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 CM : 2; // 0-1 Controller Mode.
+ UINT32 ES : 1; // 1 Endian Select (0- Little, 1-Big)
+ UINT32 SLOM : 1; // 3 Setup Lockout Mode
+ UINT32 SDIS : 1; // 4 Stream Disable Mode
+ UINT32 reserved : 26; // 5-31
+ // LSB
+ };
+} USB_USBMODE_REG;
+
+//
+// USB Non-CORE
+//
+
+#define IMX_USBNONCORE_BASE 0x02184800
+#define IMX_USBNONCORE_LENGTH 0x20
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 reserved1 : 7; // 0-6
+ UINT32 OVER_CUR_DIS : 1; // 7 Disable Overcurrent Detection
+ UINT32 OVER_CUR_POL : 1; // 8 Polarity of Overcurrent (1-active low, 0-active high)
+ UINT32 PWR_POL : 1; // 9 Power Polarity (1-active high, 0-active low)
+ UINT32 WIE : 1; // 10 Wake-up Interrupt Enable
+ UINT32 RESET : 1; // 11 Force Host 1 UTMI PHY Reset.
+ UINT32 SUSPENDM : 1; // 12 Force Host 1 UTMI PHY Suspend.
+ UINT32 UTMI_ON_CLOCK : 1; // 13 Force UTMI PHY clock output on even if in low-power suspend mode.
+ UINT32 WKUP_SW_EN : 1; // 14 Software Wake-up Enable
+ UINT32 WKUP_SW : 1; // 15 Software Wake-up
+ UINT32 WKUP_ID_EN : 1; // 16 Wake-up on ID change enable
+ UINT32 WKUP_VBUS_EN : 1; // 17 wake-up on VBUS change enable
+ UINT32 reserved2 : 13; // 18-30
+ UINT32 WIR : 1; // 31 Wake-up Interrupt Request
+ // LSB
+ };
+} USBNC_USB_UH_CTRL_REG;
+
+typedef struct {
+ UINT32 USBNC_USB_OTG_CTRL; // 0x00 USB OTG Control Register (USBNC_USB_OTG_CTRL)
+ UINT32 USBNC_USB_UH1_CTRL; // 0x04 USB Host1 Control Register (USBNC_USB_UH1_CTRL)
+ UINT32 USBNC_USB_UH2_CTRL; // 0x08 USB Host2 Control Register (USBNC_USB_UH2_CTRL)
+ UINT32 USBNC_USB_UH3_CTRL; // 0x0C USB Host3 Control Register (USBNC_USB_UH3_CTRL)
+ UINT32 USBNC_USB_UH2_HSIC_CTRL; // 0x10 USB Host2 HSIC Control Register (USBNC_USB_UH2_HSIC_CTRL)
+ UINT32 USBNC_USB_UH3_HSIC_CTRL; // 0x14 USB Host3 HSIC Control Register (USBNC_USB_UH3_HSIC_CTRL)
+ UINT32 USBNC_USB_OTG_PHY_CTRL_0; // 0x18 OTG UTMI PHY Control 0 Register (USBNC_USB_OTG_PHY_CTRL_0)
+ UINT32 USBNC_USB_UH1_PHY_CTRL_0; // 0x1C Host1 UTMI PHY Control 0 Register (USBNC_USB_UH1_PHY_CTRL_0)
+} IMX_USBNONCORE_REGISTERS;
+
+
+//
+// USB PHY
+//
+
+#define IMX_USBPHY1_BASE 0x020C9000
+#define IMX_USBPHY2_BASE 0x020CA000
+#define IMX_USBPHY_LENGTH 0x1000
+
+typedef enum {
+ IMX_USBPHY0, // OTG
+ IMX_USBPHY1,
+
+ IMX_USBPHY_COUNT
+} IMX_USBPHY_ID;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ENOTG_ID_CHG_IRQ : 1; // 0 Enable OTG_ID_CHG_IRQ.
+ UINT32 ENHOSTDISCONDETECT : 1; // 1 For host mode, enables high-speed disconnect detector.
+ UINT32 ENIRQHOSTDISCON : 1; // 2 Enables interrupt for detection of disconnection to Device when in high-speed host mode.
+ UINT32 HOSTDISCONDETECT_IRQ : 1; // 3 Indicates that the device has disconnected in high-speed mode.
+ UINT32 ENDEVPLUGINDETECT : 1; // 4 For device mode, enables 200-KOhm pullups for detecting connectivity to the host.
+ UINT32 DEVPLUGIN_POLARITY : 1; // 5 For device mode interrupt generation polarity
+ UINT32 OTG_ID_CHG_IRQ : 1; // 6 OTG ID change interrupt. Indicates the value of ID pin changed.
+ UINT32 ENOTGIDDETECT : 1; // 7 Enables circuit to detect resistance of MiniAB ID pin.
+ UINT32 RESUMEIRQSTICKY : 1; // 8 1 makes RESUME_IRQ bit a sticky bit.
+ UINT32 ENIRQRESUMEDETECT : 1; // 9 Enables interrupt for detection of a non-J state on the USB line.
+ UINT32 RESUME_IRQ : 1; // 10 Indicates that the host is sending a wake-up after suspend
+ UINT32 ENIRQDEVPLUGIN : 1; // 11 Enables interrupt for the detection of connectivity to the USB line.
+ UINT32 DEVPLUGIN_IRQ : 1; // 12 Indicates that the device is connected
+ UINT32 DATA_ON_LRADC : 1; // 13 Enables the LRADC to monitor USB_DP and USB_DM.
+ UINT32 ENUTMILEVEL2 : 1; // 14 Enables UTMI+ Level2.
+ UINT32 ENUTMILEVEL3 : 1; // 15 Enables UTMI+ Level3.
+ UINT32 ENIRQWAKEUP : 1; // 16 Enables interrupt for the wakeup events
+ UINT32 WAKEUP_IRQ : 1; // 17 Indicates that there is a wakeup event.
+ UINT32 ENAUTO_PWRON_PLL : 1; // 18
+ UINT32 ENAUTOCLR_CLKGATE : 1; // 19 Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended.
+ UINT32 ENAUTOCLR_PHY_PWD : 1; // 20 Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended
+ UINT32 ENDPDMCHG_WKUP : 1; // 21 Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended
+ UINT32 ENIDCHG_WKUP : 1; // 22 Enables the feature to wakeup USB if ID is toggled when USB is suspended
+ UINT32 ENVBUSCHG_WKUP : 1; // 23 Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.
+ UINT32 FSDLL_RST_EN : 1; // 24 Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.
+ UINT32 ENAUTOCLR_USBCLKGATE : 1; // 25
+ UINT32 ENAUTOSET_USBCLKS : 1; // 26
+ UINT32 OTG_ID_VALUE : 1; // 27
+ UINT32 HOST_FORCE_LS_SE0 : 1; // 28 Forces the next FS packet that is transmitted to have a EOP with LS timing.
+ UINT32 UTMI_SUSPENDM : 1; // 29 Used by the PHY to indicate a powered-down state.
+ UINT32 CLKGATE : 1; // 30 Gate UTMI Clocks. Clear to 0 to run clocks.
+ UINT32 SFTRST : 1; // 31 Soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, Set to 0 to release the PHY from reset.
+ // MSB
+ };
+} USBPHYx_CTRL_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 STEP : 16; // 0-15 Fixed read-only value reflecting the stepping of the RTL version.
+ UINT32 MINOR : 8; // 16-23 Fixed read-only value reflecting the MINOR field of the RTL version.
+ UINT32 MAJOR : 8; // 24-31 Fixed read-only value reflecting the MAJOR field of the RTL version
+ // MSB
+ };
+} USBPHYx_VERSION_REG;
+
+typedef struct {
+ UINT32 USBPHY_PWD; // 0x00 USB PHY Power-Down Register (USBPHY_PWD)
+ UINT32 USBPHY_PWD_SET; // 0x04 USB PHY Power-Down Register (USBPHY_PWD_SET)
+ UINT32 USBPHY_PWD_CLR; // 0x08 USB PHY Power-Down Register (USBPHY_PWD_CLR)
+ UINT32 USBPHY_PWD_TOG; // 0x0C USB PHY Power-Down Register (USBPHY_PWD_TOG)
+ UINT32 USBPHY_TX; // 0x10 USB PHY Transmitter Control Register (USBPHY_TX)
+ UINT32 USBPHY_TX_SET; // 0x14 USB PHY Transmitter Control Register (USBPHY_TX_SET)
+ UINT32 USBPHY_TX_CLR; // 0x18 USB PHY Transmitter Control Register (USBPHY_TX_CLR)
+ UINT32 USBPHY_TX_TOG; // 0x1C USB PHY Transmitter Control Register (USBPHY_TX_TOG)
+ UINT32 USBPHY_RX; // 0x20 USB PHY Receiver Control Register (USBPHY_RX)
+ UINT32 USBPHY_RX_SET; // 0x24 USB PHY Receiver Control Register(USBPHY_RX_SET)
+ UINT32 USBPHY_RX_CLR; // 0x28 USB PHY Receiver Control Register (USBPHY_RX_CLR)
+ UINT32 USBPHY_RX_TOG; // 0x2C USB PHY Receiver Control Register (USBPHY_RX_TOG)
+ UINT32 USBPHY_CTRL; // 0x30 USB PHY General Control Register (USBPHY_CTRL)
+ UINT32 USBPHY_CTRL_SET; // 0x34 USB PHY General Control Register (USBPHY_CTRL_SET)
+ UINT32 USBPHY_CTRL_CLR; // 0x38 USB PHY General Control Register (USBPHY_CTRL_CLR)
+ UINT32 USBPHY_CTRL_TOG; // 0x3C USB PHY General Control Register (USBPHY_CTRL_TOG)
+ UINT32 USBPHY_STATUS; // 0x40 USB PHY Status Register (USBPHY_STATUS)
+ UINT32 reserved1[3];
+ UINT32 USBPHY_DEBUG; // 0x50 USB PHY Debug Register (USBPHY_DEBUG)
+ UINT32 USBPHY_DEBUG_SET; // 0x54 USB PHY Debug Register(USBPHY_DEBUG_SET)
+ UINT32 USBPHY_DEBUG_CLR; // 0x58 USB PHY Debug Register (USBPHY_DEBUG_CLR)
+ UINT32 USBPHY_DEBUG_TOG; // 0x5C USB PHY Debug Register(USBPHY_DEBUG_TOG)
+ UINT32 USBPHY_DEBUG0_STATUS; // 0x60 UTMI Debug Status Register 0 (USBPHY_DEBUG0_STATUS)
+ UINT32 reserved2[3];
+ UINT32 USBPHY_DEBUG1; // 0x70 UTMI Debug Status Register 1 (USBPHY_DEBUG1)
+ UINT32 USBPHY_DEBUG1_SET; // 0x74 UTMI Debug Status Register 1 (USBPHY_DEBUG1_SET)
+ UINT32 USBPHY_DEBUG1_CLR; // 0x78 UTMI Debug Status Register 1 (USBPHY_DEBUG1_CLR)
+ UINT32 USBPHY_DEBUG1_TOG; // 0x7C UTMI Debug Status Register 1 (USBPHY_DEBUG1_TOG)
+ UINT32 USBPHY_VERSION; // 0x80 UTMI RTL Version (USBPHYx_VERSION)
+ UINT32 reserved3[3];
+ UINT32 USBPHY_IP; // 0x90
+ UINT32 USBPHY_IP_SET; // 0x94
+ UINT32 USBPHY_IP_CLR; // 0x98
+ UINT32 USBPHY_IP_TOG; // 0x9C
+} IMX_USBPHY_REGISTERS;
+
+#define IMX_USBPHY_IP_FIX ((1 << 17) | (1 << 18))
+
+//
+// USB Analog
+//
+
+#define IMX_USBANA_BASE 0x020C81A0
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 reserved1 : 18; // 0-17
+ UINT32 CHK_CONTACT : 1; // 18
+ UINT32 CHK_CHRG_B : 1; // 19
+ UINT32 EN_B : 1; // 20
+ UINT32 reserved2 : 11; // 21-31
+ // MSB
+ };
+} USB_ANALOG_USB_CHRG_DETECT_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 HS_USE_EXTERNAL_R : 1; // 0 Use external resistor to generate the current bias for the high speed transmitter.
+ UINT32 EN_DEGLITCH : 1; // 1 Enable the deglitching circuit of the USB PLL output.
+ UINT32 reserved1 : 28; // 2-29
+ UINT32 EN_CLK_UTMI : 1; // Enables the clk to the UTMI block.
+ UINT32 reserved2 : 1; // 31
+ // MSB
+ };
+} USB_ANALOG_USB_MISC_REG;
+
+typedef struct {
+ UINT32 USB_ANALOG_USB_VBUS_DETECT; // 0x00 USB VBUS Detect Register (USB_ANALOG_USB_VBUS_DETECT)
+ UINT32 USB_ANALOG_USB_VBUS_DETECT_SET; // 0x04 USB VBUS Detect Register (USB_ANALOG_USB_VBUS_DETECT_SET)
+ UINT32 USB_ANALOG_USB_VBUS_DETECT_CLR; // 0x08 USB VBUS Detect Register (USB_ANALOG_USB_VBUS_DETECT_CLR)
+ UINT32 USB_ANALOG_USB_VBUS_DETECT_TOG; // 0x0C USB VBUS Detect Register (USB_ANALOG_USB_VBUS_DETECT_TOG)
+ UINT32 USB_ANALOG_USB_CHRG_DETECT; // 0x10 USB Charger Detect Register (USB_ANALOG_USB_CHRG_DETECT)
+ UINT32 USB_ANALOG_USB_CHRG_DETECT_SET; // 0x14 USB Charger Detect Register (USB_ANALOG_USB_CHRG_DETECT_SET)
+ UINT32 USB_ANALOG_USB_CHRG_DETECT_CLR; // 0x18 USB Charger Detect Register (USB_ANALOG_USB_CHRG_DETECT_CLR)
+ UINT32 USB_ANALOG_USB_CHRG_DETECT_TOG; // 0x1C USB Charger Detect Register (USB_ANALOG_USB_CHRG_DETECT_TOG)
+ UINT32 USB_ANALOG_USB_VBUS_DETECT_STAT; // 0x20 USB VBUS Detect Status Register (USB_ANALOG_USB_VBUS_DETECT_STAT)
+ UINT32 reserved1[3];
+ UINT32 USB_ANALOG_USB_CHRG_DETECT_STAT; // 0x30 USB Charger Detect Status Register (USB_ANALOG_USB_CHRG_DETECT_STAT)
+ UINT32 reserved2[7];
+ UINT32 USB_ANALOG_USB_MISC; // 0x50 USB Misc Register (USB_ANALOG_USB_MISC)
+ UINT32 USB_ANALOG_USB_MISC_SET; // 0x54 USB Misc Register (USB_ANALOG_USB_MISC_SET)
+ UINT32 USB_ANALOG_USB_MISC_CLR; // 0x58 USB Misc Register (USB_ANALOG_USB_MISC_CLR)
+ UINT32 USB_ANALOG_USB_MISC_TOG; // 0x5C USB Misc Register (USB_ANALOG_USB_MISC_TOG)
+} IMX_USBANA_USB_REGISTERS;
+
+typedef struct {
+ IMX_USBANA_USB_REGISTERS USBANA[IMX_USBPHY_COUNT];
+ UINT32 USB_ANALOG_DIGPROG; // 0xC0 Chip Silicon Version (USB_ANALOG_DIGPROG)
+} IMX_USBANA_REGISTERS;
+
+#pragma pack(pop)
+
+#endif // __IMX6_DQ_H__
diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6_SDL.h b/Silicon/NXP/iMX6Pkg/Include/iMX6_SDL.h
new file mode 100644
index 000000000000..a0e4e79208f9
--- /dev/null
+++ b/Silicon/NXP/iMX6Pkg/Include/iMX6_SDL.h
@@ -0,0 +1,1657 @@
+/** @file
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __IMX6_SDL_H__
+#define __IMX6_SDL_H__
+
+#pragma pack(push, 1)
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+// Boot DRAM region (kernel.img & boot working DRAM)
+#define FRAME_BUFFER_BASE 0x10000000
+#define FRAME_BUFFER_SIZE 0x00800000 // 8MB
+
+#define BOOT_IMAGE_PHYSICAL_BASE 0x10800000
+#define BOOT_IMAGE_PHYSICAL_LENGTH 0x001D0000 // 1.8MB
+#define BOOT_IMAGE_ATTRIBUTES CacheAttributes
+
+// The region of registers from 0x00100000 to 0x00D00000
+#define SOC_REGISTERS_PHYSICAL_BASE1 0x00100000
+#define SOC_REGISTERS_PHYSICAL_LENGTH1 0x00C00000
+#define SOC_REGISTERS_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
+
+// PCIE registers and configuration space (0x01000000 - 0x02000000)
+#define PCIE_REGISTERS_PHYSICAL_BASE 0x01000000
+#define PCIE_REGISTERS_PHYSICAL_LENGTH 0x01000000
+
+// The region of registers from 0x02000000 to 0x02A00000
+#define SOC_REGISTERS_PHYSICAL_BASE2 0x02000000
+#define SOC_REGISTERS_PHYSICAL_LENGTH2 0x00A00000
+
+// Main system DRAM as defined by the PCD definitions of system memory.
+
+// MPPP definitions
+#define CPU0_MPPP_PHYSICAL_BASE 0x1080F000
+#define CPU1_MPPP_PHYSICAL_BASE 0x10810000
+#define CPU2_MPPP_PHYSICAL_BASE 0x10811000
+#define CPU3_MPPP_PHYSICAL_BASE 0x10812000
+
+// Interrupt controller
+#define CSP_BASE_REG_PA_IC_IFC 0x00A00100
+#define CSP_BASE_REG_PA_IC_DIST 0x00A01000
+
+// L2 cache controller
+#define CSP_BASE_REG_PA_PL310 0x00A02000
+
+// Timers
+#define CSP_BASE_REG_PA_GPT 0x02098000
+#define CSP_BASE_REG_PA_EPIT1 0x020D0000
+#define CSP_BASE_REG_PA_EPIT2 0x020D4000
+
+// Timers IRQs
+#define IC_DIST_VECTOR_BASE 0
+#define IRQ_EPIT1 88
+#define IRQ_EPIT2 89
+
+// SDMA (Smart DMA) controller
+#define CSP_BASE_REG_PA_SDMA 0x020EC000
+#define IRQ_SDMA 34
+
+// SOC peripherals
+#define CSP_BASE_REG_PA_UART1 0x02020000
+#define CSP_BASE_REG_PA_UART2 0x021E8000
+#define CSP_BASE_REG_PA_UART3 0x021EC000
+#define CSP_BASE_REG_PA_UART4 0x021F0000
+#define CSP_BASE_REG_PA_UART5 0x021F4000
+
+#define CSP_BASE_REG_PA_ESDHC1 0x02190000
+#define CSP_BASE_REG_PA_ESDHC2 0x02194000
+#define CSP_BASE_REG_PA_ESDHC3 0x02198000
+#define CSP_BASE_REG_PA_ESDHC4 0x0219C000
+
+#define DBG_PORT_SUBTYPE_IMX6 0x000C
+
+// Timers clock sources
+#define SOC_OSC_FREQUENCY_REF_HZ 24000000 // Oscillator frequency 24Mhz
+#define SOC_HIGH_FREQUENCY_REF_HZ 66000000 // High Frequency reference clock 66Mhz
+#define SOC_LOW_FREQ_REF_HZ 32768 // SNVS RTC frequency 32kHz
+
+#define IMX_GPU3D_BASE 0x00130000
+#define IMX_GPU3D_LENGTH 0x4000
+
+#define IMX_GPU2D_BASE 0x00134000
+#define IMX_GPU2D_LENGTH 0x4000
+
+//
+// IOMUX Controller (IOMUXC)
+//
+
+#define IMX_IOMUXC_BASE 0x020E0000
+#define IMX_IOMUXC_LENGTH 0x4000
+
+//
+// Secure Nonvolatile Storage (SNVS)
+//
+
+#define IMX_SNVS_BASE 0x020CC000
+#define IMX_SNVS_LENGTH 0x4000
+#define IMX_SNVS_IP_ID 0x3E
+#define IMX_SNVS_IRQ 51 // SNVS consolidated interrupt
+
+//
+// IOMUXC Registers
+//
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x020E0244
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x020E0258
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x020E0248
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x020E025C
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x020E024C
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x020E0260
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x020E0250
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x020E0264
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 0x020E0254
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 0x020E0268
+
+// define base address of Select Input registers IMX6SDL to be one word
+// less than the minimum value so that a valid Select Input value
+// is non-zero.
+#define IOMUXC_SELECT_INPUT_BASE_ADDRESS 0x20E0790
+
+typedef enum {
+ IOMUXC_ASRC_ASRCK_CLOCK_6_SELECT_INPUT = 0x20E0794,
+ IOMUXC_AUD4_INPUT_DA_AMX_SELECT_INPUT = 0x20E0798,
+ IOMUXC_AUD4_INPUT_DB_AMX_SELECT_INPUT = 0x20E079C,
+ IOMUXC_AUD4_INPUT_RXCLK_AMX_SELECT_INPUT = 0x20E07A0,
+ IOMUXC_AUD4_INPUT_RXFS_AMX_SELECT_INPUT = 0x20E07C0,
+ IOMUXC_AUD4_INPUT_TXCLK_AMX_SELECT_INPUT = 0x20E07A8,
+ IOMUXC_AUD4_INPUT_TXFS_AMX_SELECT_INPUT = 0x20E07AC,
+ IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT = 0x20E07B0,
+ IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT = 0x20E07B4,
+ IOMUXC_AUD5_INPUT_RXCLK_AMX_SELECT_INPUT = 0x20E07B8,
+ IOMUXC_AUD5_INPUT_RXFS_AMX_SELECT_INPUT = 0x20E07BC,
+ IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT = 0x20E07C0,
+ IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT = 0x20E07C4,
+ IOMUXC_FLEXCAN1_RX_SELECT_INPUT = 0x20E07C8,
+ IOMUXC_FLEXCAN2_RX_SELECT_INPUT = 0x20E07CC,
+ IOMUXC_CCM_PMIC_READY_SELECT_INPUT = 0x20E07D4,
+ IOMUXC_ECSPI1_CSPI_CLK_IN_SELECT_INPUT = 0x20E07D8,
+ IOMUXC_ECSPI1_MISO_SELECT_INPUT = 0x20E07DC,
+ IOMUXC_ECSPI1_MOSI_SELECT_INPUT = 0x20E07E0,
+ IOMUXC_ECSPI1_SS0_SELECT_INPUT = 0x20E07E4,
+ IOMUXC_ECSPI1_SS1_SELECT_INPUT = 0x20E07E8,
+ IOMUXC_ECSPI1_SS2_SELECT_INPUT = 0x20E07EC,
+ IOMUXC_ECSPI1_SS3_SELECT_INPUT = 0x20E07F0,
+ IOMUXC_ECSPI2_CSPI_CLK_IN_SELECT_INPUT = 0x20E07F4,
+ IOMUXC_ECSPI2_MISO_SELECT_INPUT = 0x20E07F8,
+ IOMUXC_ECSPI2_MOSI_SELECT_INPUT = 0x20E07FC,
+ IOMUXC_ECSPI2_SS0_SELECT_INPUT = 0x20E0800,
+ IOMUXC_ECSPI2_SS1_SELECT_INPUT = 0x20E0804,
+ IOMUXC_ECSPI4_SS0_SELECT_INPUT = 0x20E0808,
+ IOMUXC_ENET_REF_CLK_SELECT_INPUT = 0x20E080C,
+ IOMUXC_ENET_MAC0_MDIO_SELECT_INPUT = 0x20E0810,
+ IOMUXC_ENET_MAC0_RX_CLK_SELECT_INPUT = 0x20E0814,
+ IOMUXC_ENET_MAC0_RX_DATA0_SELECT_INPUT = 0x20E0818,
+ IOMUXC_ENET_MAC0_RX_DATA1_SELECT_INPUT = 0x20E081C,
+ IOMUXC_ENET_MAC0_RX_DATA2_SELECT_INPUT = 0x20E0820,
+ IOMUXC_ENET_MAC0_RX_DATA3_SELECT_INPUT = 0x20E0824,
+ IOMUXC_ENET_MAC0_RX_EN_SELECT_INPUT = 0x20E0828,
+ IOMUXC_ESAI_RX_FS_SELECT_INPUT = 0x20E082C,
+ IOMUXC_ESAI_TX_FS_SELECT_INPUT = 0x20E0830,
+ IOMUXC_ESAI_RX_HF_CLK_SELECT_INPUT = 0x20E0834,
+ IOMUXC_ESAI_TX_HF_CLK_SELECT_INPUT = 0x20E0838,
+ IOMUXC_ESAI_RX_CLK_SELECT_INPUT = 0x20E083C,
+ IOMUXC_ESAI_TX_CLK_SELECT_INPUT = 0x20E0840,
+ IOMUXC_ESAI_SDO0_SELECT_INPUT = 0x20E0844,
+ IOMUXC_ESAI_SDO1_SELECT_INPUT = 0x20E0848,
+ IOMUXC_ESAI_SDO2_SDI3_SELECT_INPUT = 0x20E084C,
+ IOMUXC_ESAI_SDO3_SDI2_SELECT_INPUT = 0x20E0850,
+ IOMUXC_ESAI_SDO4_SDI1_SELECT_INPUT = 0x20E0854,
+ IOMUXC_ESAI_SDO5_SDI0_SELECT_INPUT = 0x20E0858,
+ IOMUXC_HDMI_ICECIN_SELECT_INPUT = 0x20E085C,
+ IOMUXC_HDMI_II2C_CLKIN_SELECT_INPUT = 0x20E0860,
+ IOMUXC_HDMI_II2C_DATAIN_SELECT_INPUT = 0x20E0864,
+ IOMUXC_I2C1_SCL_IN_SELECT_INPUT = 0x20E0868,
+ IOMUXC_I2C1_SDA_IN_SELECT_INPUT = 0x20E086C,
+ IOMUXC_I2C2_SCL_IN_SELECT_INPUT = 0x20E0870,
+ IOMUXC_I2C2_SDA_IN_SELECT_INPUT = 0x20E0874,
+ IOMUXC_I2C3_SCL_IN_SELECT_INPUT = 0x20E0878,
+ IOMUXC_I2C3_SDA_IN_SELECT_INPUT = 0x20E087C,
+ IOMUXC_I2C4_SCL_IN_SELECT_INPUT = 0x20E0880,
+ IOMUXC_I2C4_SDA_IN_SELECT_INPUT = 0x20E0884,
+ IOMUXC_KEY_COL5_SELECT_INPUT = 0x20E08C0,
+ IOMUXC_KEY_COL6_SELECT_INPUT = 0x20E08C4,
+ IOMUXC_KEY_COL7_SELECT_INPUT = 0x20E08C8,
+ IOMUXC_KEY_ROW5_SELECT_INPUT = 0x20E08CC,
+ IOMUXC_KEY_ROW6_SELECT_INPUT = 0x20E08D0,
+ IOMUXC_KEY_ROW7_SELECT_INPUT = 0x20E08D4,
+ IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT = 0x20E08DC,
+ IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT = 0x20E08E0,
+ IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT = 0x20E08E4,
+ IOMUXC_SDMA_EVENTS14_SELECT_INPUT = 0x20E08E8,
+ IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 0x20E08F0,
+ IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT = 0x20E08F4,
+ IOMUXC_UART1_UART_RTS_B_SELECT_INPUT = 0x20E08F8,
+ IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT = 0x20E08FC,
+ IOMUXC_UART2_UART_RTS_B_SELECT_INPUT = 0x20E00900,
+ IOMUXC_UART2_UART_RX_DATA_SELECT_INPUT = 0x20E0904,
+ IOMUXC_UART3_UART_RTS_B_SELECT_INPUT = 0x20E908,
+ IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT = 0x20E090C,
+ IOMUXC_UART4_UART_RTS_B_SELECT_INPUT = 0x20E0910,
+ IOMUXC_UART4_UART_RX_DATA_SELECT_INPUT = 0x20E0914,
+ IOMUXC_UART5_UART_RTS_B_SELECT_INPUT = 0x20E0918,
+ IOMUXC_UART5_UART_RX_DATA_SELECT_INPUT = 0x20E091C,
+ IOMUXC_USB_OTG_OC_SELECT_INPUT = 0x20E0920,
+ IOMUXC_USB_H1_OC_SELECT_INPUT = 0x20E0924,
+ IOMUXC_USDHC1_WP_ON_SELECT_INPUT = 0x20E092C,
+ IOMUXC_SELECT_INPUT_UPPER_BOUND = IOMUXC_USDHC1_WP_ON_SELECT_INPUT,
+} IMX_INPUT_SELECT;
+
+#define IOMUXC_GPR_BASE_ADDRESS 0x020E0000
+
+typedef struct{
+ UINT32 GPR0; // 0x00 IOMUXC_GPR0
+ UINT32 GPR1; // 0x04 IOMUXC_GPR1
+ UINT32 GPR2; // 0x08 IOMUXC_GPR2
+ UINT32 GPR3; // 0x0C IOMUXC_GPR3
+ UINT32 GPR4; // 0x10 IOMUXC_GPR4
+ UINT32 GPR5; // 0x14 IOMUXC_GPR5
+ UINT32 GPR6; // 0x18 IOMUXC_GPR6
+ UINT32 GPR7; // 0x1C IOMUXC_GPR7
+ UINT32 GPR8; // 0x20 IOMUXC_GPR8
+ UINT32 GPR9; // 0x24 IOMUXC_GPR9
+ UINT32 GPR10; // 0x28 IOMUXC_GPR10
+ UINT32 GPR11; // 0x2c IOMUXC_GPR11
+ UINT32 GPR12; // 0x30 IOMUXC_GPR12
+ UINT32 GPR13; // 0x34 IOMUXC_GPR13
+} IMX_IOMUXC_GPR_REGISTERS;
+
+typedef enum {
+ IMX_IOMUXC_GPR1_USB_OTG_ID_SEL_ENET_RX_ER,
+ IMX_IOMUXC_GPR1_USB_OTG_ID_SEL_GPIO_1,
+} IMX_IOMUXC_GPR1_USB_OTG_ID_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ACT_CS0 : 1; // 0
+ UINT32 ADDRS0_10 : 2; // 1-2
+ UINT32 ACT_CS1 : 1; // 3
+ UINT32 ADDRS1_10 : 2; // 4-5
+ UINT32 ACT_CS2 : 1; // 6
+ UINT32 ADDRS2_10 : 2; // 7-8
+ UINT32 ACT_CS3 : 1; // 9
+ UINT32 ADDRS3_10 : 2; // 10-11 Active Chip Select and Address Space
+ UINT32 GINT : 1; // 12 Global interrupt "0" bit (connected to ARM IRQ#0 and GPC)
+ UINT32 USB_OTG_ID_SEL : 1; // 13 ''usb_otg_id' pin iomux select control.
+ UINT32 SYS_INT : 1; // 14 PCIe_CTL
+ UINT32 USB_EXP_MODE : 1; // 15 USB Exposure mode
+ UINT32 REF_SSP_EN : 1; // 16 PCIe_PHY - Reference Clock Enable for SS function.
+ UINT32 PU_VPU_MUX : 1; // 17 IPU-1/IPU-2 to VPU signals control.
+ UINT32 TEST_POWERDOWN : 1; // 18 PCIe_PHY - All Circuits Power-Down Control Function.
+ UINT32 MIPI_IPU1_MUX : 1; // 19 MIPI sensor to IPU-1 mux control.
+ UINT32 MIPI_IPU2_MUX : 1; // 20 MIPI sensor to IPU-2 mux control
+ UINT32 ENET_CLK_SEL : 1; // 21 ENET TX reference clock
+ UINT32 EXC_MON : 1; // 22 Exclusive monitor response select of illegal command
+ UINT32 reserved1 : 1; // 23
+ UINT32 MIPI_DPI_OFF : 1; // 24 MIPI DPI shutdown request
+ UINT32 MIPI_COLOR_SW : 1; // 25 MIPI color switch control
+ UINT32 APP_REQ_ENTR_L1 : 1; // 26 PCIe_CTL - Application Request to Enter L1
+ UINT32 APP_READY_ENTR_L23 : 1; // 27 PCIe_CTL - Application Ready to Enter L23
+ UINT32 APP_REQ_EXIT_L1 : 1; // 28 PCIe_CTL - Application Request to Exit L1
+ UINT32 reserved2 : 1; // 29
+ UINT32 APP_CLK_REQ_N : 1; // 30 PCIe_CTL (CLK LOGIC CONTROLLER GLUE) - Indicates that application logic is ready to have reference clock removed.
+ UINT32 CFG_L1_CLK_REMOVAL_EN : 1; // 31 PCIe_CTL (CLK LOGIC CONTROLLER GLUE) - Enable the reference clock removal in L1 state.
+ // MSB
+ };
+} IMX_IOMUXC_GPR1_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 PCS_TX_DEEMPH_GEN1 : 6; // 0-5 PCIe_PHY - This static value sets the launch amplitude of the transmitter when pipe0_tx_swing is set to 1'b0 (default state).
+ UINT32 PCS_TX_DEEMPH_GEN2_3P5DB : 6;// 6-11 PCIe_PHY - This static value sets the Tx driver SWING_FULL value.
+ UINT32 PCS_TX_DEEMPH_GEN2_6DB : 6; // 12-17 PCIe_PHY - This static value sets the Tx driver de-emphasis value in the case where pipe0_tx_deemph is set to 1'b0 and the PHY is running at the Gen2 (6db) rate.
+ UINT32 PCS_TX_SWING_FULL : 7; // 18-24 PCIe_PHY - This static value sets the Tx driver de-emphasis value in the case where pipe0_tx_deemph is set to 1'b1 (the default setting) and the PHY is running at the Gen2 (3p5db) rate.
+ UINT32 PCS_TX_SWING_LOW : 7; // 25-31 PCIe_PHY - This static value sets the Tx driver de-emphasis value in the case where pipe0_tx_deemph is set to 1'b1 (the default setting) and the PHY is running at the Gen1 rate.
+ // MSB
+ };
+} IMX_IOMUXC_GPR8_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 reserved0 : 2; // 0-1
+ UINT32 uSDHC_DBG_MUX : 2; // 2-3 uSDHC debug bus IO mux control
+ UINT32 LOS_LEVEL : 5; // 4-8 PCIe_PHY - Loss-of-Signal Detector Sensitivity Level Control Function: Sets the sensitivity level for the Loss - of - Signal detector.This signal must be set to 0x9
+ UINT32 APPS_PM_XMT_PME : 1; // 9 PCIe_CTL - Wake Up. Used by application logic to wake up the PMC state machine from a D1, D2 or D3 power state.Upon wake - up, the core sends a PM_PME Message
+ UINT32 APP_LTSSM_ENABLE : 1; // 10 PCIe_CTL Driven low by the application after reset to hold the LTSSM in the Detect state until the application is ready.When the application has finished initializing the core configuration registers, it asserts app_ltssm_enable to allow the LTSSM to continue Link establishment.
+ UINT32 APP_INIT_RST : 1; // 11 PCIe_PHY - PCIe_CTL - Request from the application to send a Hot Reset to the downstream device.
+ UINT32 DEVICE_TYPE : 4; // 12-15 PCIe_CTL - Device/Port Type. 0000 PCIE_EP EP Mode 0010 PCIE_RC RC Mode
+ UINT32 APPS_PM_XMT_TURNOFF : 1; // 16 PCIe_CTL - Request from the application to generate a PM_Turn_Off Message.
+ UINT32 DIA_STATUS_BUS_SELECT : 4; // 17-20 PCIe_CTL - used for debug to select what part of diag_status_bus will be reflected on the 32 bits of the iomux
+ UINT32 PCIe_CTL_7 : 3; // 21-23 PCIe control of diagnostic bus select
+ UINT32 ARMP_APB_CLK_EN : 1; // 24 ARM platform APB clock enable
+ UINT32 ARMP_ATB_CLK_EN : 1; // 25 ARM platform ATB clock enable
+ UINT32 ARMP_AHB_CLK_EN : 1; // 26 ARM platform AHB clock enable
+ UINT32 ARMP_IPG_CLK_EN : 1; // 27 ARM platform IPG clock enable
+ UINT32 reserved1 : 4; // 28-31
+ // MSB
+ };
+} IMX_IOMUXC_GPR12_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 reserved1 : 1; // 0
+ UINT32 reserved2 : 1; // 1
+ UINT32 MC_ENV : 1; // 2 Monotonic Counter Enable and Valid
+ UINT32 reserved3 : 1; // 3
+ UINT32 reserved4 : 1; // 4
+ UINT32 DP_EN : 1; // 5 Dumb PMIC Enabled
+ UINT32 TOP : 1; // 6 Turn off System Power
+ UINT32 PWR_GLITCH_EN : 1; // 7 Power Glitch Detection Enable
+ UINT32 reserved5 : 1; // 8
+ UINT32 reserved6 : 1; // 9
+ UINT32 reserved7 : 5; // 10-14
+ UINT32 reserved8 : 1; // 15
+ UINT32 BTN_PRESS_TIME : 2; // 16-17 Button press time out values for PMIC Logic.
+ UINT32 DEBOUNCE : 2; // 18-19 debounce time for the BTN input signal
+ UINT32 ON_TIME : 2; // 20-21 Time after BTN is asserted before pmic_en_b is asserted
+ UINT32 PK_EN : 1; // 22 PMIC On Request Enable
+ UINT32 PK_OVERRIDE : 1; // 23 PMIC On Request Override
+ UINT32 reserved9 : 8; // 24-31
+ // MSB
+ };
+} IMX_SNVS_LPCR_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 MINOR_REV : 8; // 0-7 SNVS block minor version number
+ UINT32 MAJOR_REV : 8; // 8-15 SNVS block major version number
+ UINT32 IP_ID : 16; // 16-31 SNVS block ID (IMX_SNVS_IP_ID)
+ // MSB
+ };
+} IMX_SNVS_HPVIDR1_REG;
+
+typedef struct {
+ UINT32 HPLR; // 0x000 SNVS_HP Lock Register (SNVS_HPLR)
+ UINT32 HPCOMR; // 0x004 SNVS_HP Command Register (SNVS_HPCOMR)
+ UINT32 HPCR; // 0x008 SNVS_HP Control Register (SNVS_HPCR)
+ UINT32 reserved1[2];
+ UINT32 HPSR; // 0x014 SNVS_HP Status Register (SNVS_HPSR)
+ UINT32 reserved2[3];
+ UINT32 HPRTCMR; // 0x024 SNVS_HP Real Time Counter MSB Register (SNVS_HPRTCMR
+ UINT32 HPRTCLR; // 0x028 SNVS_HP Real Time Counter LSB Register (SNVS_HPRTCLR)
+ UINT32 HPTAMR; // 0x02C SNVS_HP Time Alarm MSB Register (SNVS_HPTAMR)
+ UINT32 HPTALR; // 0x030 SNVS_HP Time Alarm LSB Register (SNVS_HPTALR)
+ UINT32 LPLR; // 0x034 SNVS_LP Lock Register (SNVS_LPLR)
+ UINT32 LPCR; // 0x038 SNVS_LP Control Register (SNVS_LPCR)
+ UINT32 reserved3[4];
+ UINT32 LPSR; // 0x04C SNVS_LP Status Register (SNVS_LPSR)
+ UINT32 reserved4[3];
+ UINT32 LPSMCMR; // 0x05C SNVS_LP Secure Monotonic Counter MSB Register (SNVS_LPSMCMR)
+ UINT32 LPSMCLR; // 0x060 SNVS_LP Secure Monotonic Counter LSB Register (SNVS_LPSMCLR)
+ UINT32 reserved5[1];
+ UINT32 LPGPR; // 0x068 SNVS_LP General Purpose Register (SNVS_LPGPR)
+ UINT32 reserved6[739];
+ UINT32 HPVIDR1; // 0xBF8 SNVS_HP Version ID Register 1 (SNVS_HPVIDR1)
+ UINT32 HPVIDR2; // 0xBFC SNVS_HP Version ID Register 2 (SNVS_HPVIDR2)
+} IMX_SNVS_REGISTERS;
+
+//
+// System Reset Controller (SRC)
+//
+
+#define IMX_SRC_BASE 0x020D8000
+#define IMX_SRC_LENGTH 0x4000
+
+//
+// SCR Register Definition
+//
+
+typedef enum {
+ IMX_SCR_WARM_RST_BYPASS_COUNT_DISABLED,
+ IMX_SCR_WARM_RST_BYPASS_COUNT_16,
+ IMX_SCR_WARM_RST_BYPASS_COUNT_32,
+ IMX_SCR_WARM_RST_BYPASS_COUNT_64,
+} IMX_SCR_WARM_RST_BYPASS_COUNT;
+
+typedef enum {
+ IMX_SRC_MASK_WDOG_RST_B_MASKED = 0x5,
+ IMX_SRC_MASK_WDOG_RST_B_NOT_MASKED = 0xA,
+} IMX_SRC_MASK_WDOG_RST;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 warm_reset_enable : 1; // 0 WARM reset enable bit
+ UINT32 sw_gpu_rst : 1; // 1 Software reset for GPU
+ UINT32 sw_vpu_rst : 1; // 2 Software reset for VPU
+ UINT32 sw_ipu1_rst : 1; // 3 Software reset for IPU1
+ UINT32 sw_open_vg_rst : 1; // 4 Software reset for open_vg
+ UINT32 warm_rst_bypass_count : 2; // 5-6 Defines the XTALI cycles to count before bypassing the MMDC acknowledge for WARM reset (IMX_SCR_WARM_RST_BYPASS_COUNT)
+ UINT32 mask_wdog_rst : 4; // 7-10 Mask wdog_rst_b source (IMX_SRC_MASK_WDOG_RST)
+ UINT32 eim_rst : 1; // 11 EIM reset is needed in order to reconfigure the eim chip select.
+ UINT32 sw_ipu2_rst : 1; // 12 Software reset for ipu2
+ UINT32 core0_rst : 1; // 13 Software reset for core0 only.
+ UINT32 core1_rst : 1; // 14 Software reset for core1 only.
+ UINT32 core2_rst : 1; // 15 Software reset for core2 only
+ UINT32 core3_rst : 1; // 16 Software reset for core3 only.
+ UINT32 core0_dbg_rst : 1; // 17 Software reset for core0 debug only.
+ UINT32 core1_dbg_rst : 1; // 18 Software reset for core1 debug only.
+ UINT32 core2_dbg_rst : 1; // 19 Software reset for core2 debug only.
+ UINT32 core3_dbg_rst : 1; // 20 Software reset for core3 debug only.
+ UINT32 cores_dbg_rst : 1; // 21 Software reset for debug of arm platform only.
+ UINT32 core1_enable : 1; // 22 core1 enable
+ UINT32 core2_enable : 1; // 23 core2 enable
+ UINT32 core3_enable : 1; // 24 core3 enable
+ UINT32 dbg_rst_msk_pg : 1; // 25 Do not assert debug resets after power gating event of core
+ UINT32 reserved : 6; // 26-31 reserved
+ // MSB
+ };
+} IMX_SRC_SCR_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 BOOT_CFG1 : 8; // 0-7
+ UINT32 BOOT_CFG2 : 8; // 8-15
+ UINT32 BOOT_CFG3 : 8; // 16-23
+ UINT32 BOOT_CFG4 : 8; // 24-31
+ // MSB
+ };
+} IMX_SRC_SBMR1_REG;
+
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 SEC_COFNIG : 2; // 0-1
+ UINT32 reserved1 : 1; // 2
+ UINT32 DIR_BT_DIS : 1; // 3
+ UINT32 BT_FUSE_SEL : 1; // 4
+ UINT32 reserved2 : 19; // 5-23
+ UINT32 BMOD : 2; // 24-25
+ UINT32 reserved3 : 6; // 26-31
+ // MSB
+ };
+} IMX_SRC_SBMR2_REG;
+
+typedef struct {
+ UINT32 SCR; // 0x00 SRC Control Register (SRC_SCR)
+ UINT32 SBMR1; // 0x04 SRC Boot Mode Register 1 (SRC_SBMR1)
+ UINT32 SRSR; // 0x08 SRC Reset Status Register (SRC_SRSR)
+ UINT32 reserved1[2];
+ UINT32 SISR; // 0x14 SRC Interrupt Status Register (SRC_SISR)
+ UINT32 SIMR; // 0x18 SRC Interrupt Mask Register (SRC_SIMR)
+ UINT32 SBMR2; // 0x1C SRC Boot Mode Register 2 (SRC_SBMR2)
+ UINT32 GPR1; // 0x20 SRC General Purpose Register 1 (SRC_GPR1)
+ UINT32 GPR2; // 0x24 SRC General Purpose Register 2 (SRC_GPR2)
+ UINT32 GPR3; // 0x28 SRC General Purpose Register 3 (SRC_GPR3)
+ UINT32 GPR4; // 0x2C SRC General Purpose Register 4 (SRC_GPR4)
+ UINT32 GPR5; // 0x30 SRC General Purpose Register 4 (SRC_GPR5)
+ UINT32 GPR6; // 0x34 SRC General Purpose Register 4 (SRC_GPR6)
+ UINT32 GPR7; // 0x38 SRC General Purpose Register 4 (SRC_GPR7)
+ UINT32 GPR8; // 0x3C SRC General Purpose Register 4 (SRC_GPR8)
+ UINT32 GPR9; // 0x40 SRC General Purpose Register 4 (SRC_GPR9)
+ UINT32 GPR10; // 0x44 SRC General Purpose Register 4 (SRC_GPR10)
+} IMX_SRC_REGISTERS;
+
+
+//
+// Watchdog (WDOG)
+//
+
+#define IMX_WDOG1_BASE 0x020BC000
+#define IMX_WDOG2_BASE 0x020C0000
+#define IMX_WDOG_LENGTH 0x4000
+
+#define IMX_WDOG_WSR_FEED1 0x5555
+#define IMX_WDOG_WSR_FEED2 0xAAAA
+
+typedef union {
+ UINT16 AsUint16;
+ struct {
+ // LSB
+ UINT16 WDZST : 1; // 0 Watchdog Low Power
+ UINT16 WDBG : 1; // 1 Watchdog DEBUG Enable
+ UINT16 WDE : 1; // 2 Watchdog Enable
+ UINT16 WDT : 1; // 3 WDOG_B Time-out assertion.
+ UINT16 SRS : 1; // 4 Software Reset Signal
+ UINT16 WDA : 1; // 5 WDOG_B assertion
+ UINT16 reserved1 : 1; // 6
+ UINT16 WDW : 1; // 7 Watchdog Disable for Wait
+ UINT16 WT : 8; // 8-15 Watchdog Time-out Field
+ // MSB
+ };
+} IMX_WDOG_WCR_REG;
+
+typedef struct {
+ UINT16 WCR; // 0x0 Watchdog Control Register (WDOG1_WCR)
+ UINT16 WSR; // 0x2 Watchdog Service Register (WDOG1_WSR)
+ UINT16 WRSR; // 0x4 Watchdog Reset Status Register (WDOG1_WRSR)
+ UINT16 WICR; // 0x6 Watchdog Interrupt Control Register (WDOG1_WICR)
+ UINT16 WMCR; // 0x8 Watchdog Miscellaneous Control Register (WDOG1_WMCR)
+} IMX_WDOG_REGISTERS;
+
+//
+// Clock Control Module (CCM)
+//
+
+#define IMX_CCM_BASE 0x020C4000
+#define IMX_CCM_LENGTH 0x4000
+#define IMX_CCM_ANALOG_BASE 0x020C8000
+#define IMX_CCM_ANALOG_LENGTH 0x1000
+
+#define IMX_GPU2D_CORE_CLK_MAX 532000000 // 532Mhz
+#define IMX_GPU3D_CORE_CLK_MAX 540000000 // 540Mhz
+
+#define IMX_REF_CLK_24M_FREQ 24000000
+
+typedef enum {
+ IMX_CCM_PLL3_SW_CLK_SEL_PLL3_MAIN_CLK,
+ IMX_CCM_PLL3_SW_CLK_SEL_PLL3_BYPASS_CLK,
+} IMX_CCM_PLL3_SW_CLK_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 pll3_sw_clk_sel : 1; // 0 Selects source to generate pll3_sw_clk
+ UINT32 reserved1 : 1; // 1 reserved
+ UINT32 pll1_sw_clk_sel : 1; // 2 Selects source to generate pll1_sw_clk.
+ UINT32 reserved2 : 5; // 3-7
+ UINT32 step_sel : 1; // 8 Selects the option to be chosen for the step frequency
+ UINT32 pfd_396m_dis_mask : 1; // 9 Mask of 396M PFD auto-disable
+ UINT32 pfd_352m_dis_mask : 1; // 10 Mask of 352M PFD auto-disable.
+ UINT32 pfd_594_dis_mask : 1; // 11 Mask of 594M PFD auto-disable.
+ UINT32 pfd_508m_dis_mask : 1; // 12 Mask of 508M PFD auto-disable
+ UINT32 pfd_454m_dis_mask : 1; // 13 Mask of 454M PFD auto-disable.
+ UINT32 pfd_720m_dis_mask : 1; // 14 Mask of 720M PFD auto-disable.
+ UINT32 pfd_540m_dis_mask : 1; // 15 Mask of 540M PFD auto-disable.
+ UINT32 reserved3 : 16; // 16-31
+ // MSB
+ };
+} IMX_CCM_CCSR_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 arm_podf : 3; // 0-3 Divider for ARM clock root
+ UINT32 reserved : 29; // 3-31
+ // MSB
+ };
+} IMX_CCM_CACRR_REG;
+
+// CBCMR.gpu2d_axi_clk_sel
+typedef enum {
+ IMX_CCM_GPU2D_AXI_CLK_SEL_AXI,
+ IMX_CCM_GPU2D_AXI_CLK_SEL_AHB,
+} IMX_CCM_GPU2D_AXI_CLK_SEL;
+
+// CBCMR.gpu3d_axi_clk_sel
+typedef enum {
+ IMX_CCM_GPU3D_AXI_CLK_SEL_AXI,
+ IMX_CCM_GPU3D_AXI_CLK_SEL_AHB,
+} IMX_CCM_GPU3D_AXI_CLK_SEL;
+
+// CBCMR.gpu2d_core_clk_sel
+typedef enum {
+ IMX_CCM_GPU2D_CORE_CLK_SEL_AXI,
+ IMX_CCM_GPU2D_CORE_CLK_SEL_PLL3_SW,
+ IMX_CCM_GPU2D_CORE_CLK_SEL_PLL2_PFD0,
+ IMX_CCM_GPU2D_CORE_CLK_SEL_PLL2_PFD2,
+} IMX_CCM_GPU2D_CORE_CLK_SEL;
+
+// CBCMR.pre_periph_clk_sel
+typedef enum {
+ IMX_CCM_PRE_PERIPH_CLK_SEL_PLL2,
+ IMX_CCM_PRE_PERIPH_CLK_SEL_PLL2_PFD2,
+ IMX_CCM_PRE_PERIPH_CLK_SEL_PLL2_PFD0,
+ IMX_CCM_PRE_PERIPH_CLK_SEL_PLL2_PFD2_DIV2,
+} IMX_CCM_PRE_PERIPH_CLK_SEL;
+
+// CBCMR.gpu3d_core_clk_sel
+typedef enum {
+ IMX_CCM_GPU3D_CORE_CLK_SEL_MMDC_CH0_AXI,
+ IMX_CCM_GPU3D_CORE_CLK_SEL_PLL3_SW,
+ IMX_CCM_GPU3D_CORE_CLK_SEL_PLL2_PFD1,
+ IMX_CCM_GPU3D_CORE_CLK_SEL_PLL2_PFD2,
+} IMX_CCM_GPU3D_CORE_CLK_SEL;
+
+// CBCMR.gpu3d_shader_clk_sel
+typedef enum {
+ IMX_CCM_GPU3D_SHADER_CLK_SEL_MMDC_CH0_AXI,
+ IMX_CCM_GPU3D_SHADER_CLK_SEL_PLL3_SW,
+ IMX_CCM_GPU3D_SHADER_CLK_SEL_PLL2_PFD1,
+ IMX_CCM_GPU3D_SHADER_CLK_SEL_PLL3_PFD0,
+} IMX_CCM_GPU3D_SHADER_CLK_SEL;
+
+// CBCMR.periph_clk2_sel
+typedef enum {
+ IMX_CCM_PERIPH_CLK2_SEL_PLL3_SW_CLK,
+ IMX_CCM_PERIPH_CLK2_SEL_OSC_CLK,
+ IMX_CCM_PERIPH_CLK2_SEL_PLL2,
+} IMX_CCM_PERIPH_CLK2_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 gpu2d_axi_clk_sel : 1; // 0 Selector for gpu2d_axi clock multiplexer (IMX_CCM_GPU2D_AXI_CLK_SEL)
+ UINT32 gpu3d_axi_clk_sel : 1; // 1 Selector for gpu3d_axi clock multiplexer (IMX_CCM_GPU3D_AXI_CLK_SEL)
+ UINT32 reserved1 : 2; // 2-3
+ UINT32 gpu3d_core_clk_sel : 2; // 4-5 Selector for gpu3d_core clock multiplexer (IMX_CCM_GPU3D_CORE_CLK_SEL)
+ UINT32 reserved2 : 2; // 6-7
+ UINT32 gpu3d_shader_clk_sel : 2; // 8-9 Selector for gpu3d_shader clock multiplexer (IMX_CCM_GPU3D_SHADER_CLK_SEL)
+ UINT32 pcie_axi_clk_sel : 1; // 10 Selector for pcie_axi clock multiplexer
+ UINT32 vdoaxi_clk_sel : 1; // 11 Selector for vdoaxi clock multiplexer
+ UINT32 periph_clk2_sel : 2; // 12-13 Selector for peripheral clk2 clock multiplexer
+ UINT32 vpu_axi_clk_sel : 2; // 14-15 Selector for VPU axi clock multiplexer
+ UINT32 gpu2d_core_clk_sel : 2; // 16-17 Selector for open vg (GPU2D Core) clock multiplexer (IMX_CCM_GPU2D_CORE_CLK_SEL)
+ UINT32 pre_periph_clk_sel : 2; // 18-19 Selector for pre_periph clock multiplexer
+ UINT32 periph2_clk2_sel : 1; // 20 Selector for periph2_clk2 clock multiplexer
+ UINT32 pre_periph2_clk_sel : 2; // 21-22 Selector for pre_periph2 clock multiplexer
+ UINT32 gpu2d_core_clk_podf : 3; // 23-25 Divider for gpu2d_core clock.
+ UINT32 gpu3d_core_podf : 3; // 26-28 Divider for gpu3d_core clock
+ UINT32 gpu3d_shader_podf : 3; // 29-31 Divider for gpu3d_shader clock.
+ // MSB
+ };
+} IMX_CCM_CBCMR_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ssi1_clk_podf : 6; // 0-5 Divider for ssi1 clock podf
+ UINT32 ssi1_clk_pred : 3; // 6-8 Divider for ssi1 clock pred
+ UINT32 esai_clk_pred : 3; // 9-11 Divider for esai clock pred
+ UINT32 reserved1 : 4; // 12-15 Reserved
+ UINT32 ssi3_clk_podf : 6; // 16-21 Divider for ssi3 clock podf
+ UINT32 ssi3_clk_pred : 3; // 22-24 Divider for ssi3 clock pred
+ UINT32 esai_clk_podf : 3; // 25-27 Divider for esai clock podf
+ UINT32 reserved2 : 4; // 28-31 Reserved
+ // MSB
+ };
+} IMX_CCM_CS1CDR_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ssi2_clk_podf : 6; // 0-5 Divider for ssi2 clock podf
+ UINT32 ssi2_clk_pred : 3; // 6-8 Divider for ssi2 clock pred
+ UINT32 ldb_di0_clk_sel : 3; // 9-11 Selector for ldb_di0 clock multiplexer
+ UINT32 ldb_di1_clk_sel : 3; // 12-14 Selector for ldb_di1 clock multiplexer
+ UINT32 reserved1 : 1; // 15 Reserved
+ UINT32 enfc_clk_sel : 2; // 16-17 Selector for enfc clock multiplexer
+ UINT32 enfc_clk_pred : 3; // 18-20 Divider for enfc clock pred divider
+ UINT32 esai_clk_podf : 6; // 21-26 Divider for enfc clock divider
+ UINT32 reserved2 : 5; // 27-31 Reserved
+ // MSB
+ };
+} IMX_CCM_CS2CDR_REG;
+
+typedef enum {
+ IMX_CCM_CCGR_OFF = 0x0, // Clock is off during all modes. Stop enter hardware handshake is disabled.
+ IMX_CCM_CCGR_ON_RUN = 0x1, // Clock is on in run mode, but off in WAIT and STOP modes
+ IMX_CCM_CCGR_ON = 0x3, // Clock is on during all modes, except STOP mode.
+} IMX_CCM_CCGR;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 aips_tz1_clk_enable : 2; // 0-1 aips_tz1 clocks (aips_tz1_clk_enable)
+ UINT32 aips_tz2_clk_enable : 2; // 2-3 aips_tz2 clocks (aips_tz2_clk_enable)
+ UINT32 apbhdma_hclk_enable : 2; // 4-5 apbhdma hclk clock (apbhdma_hclk_enable)
+ UINT32 asrc_clk_enable : 2; // 6-7 asrc clock (asrc_clk_enable)
+ UINT32 caam_secure_mem_clk_enable : 2; // 8-9 caam_secure_mem clock (caam_secure_mem_clk_enable)
+ UINT32 caam_wrapper_aclk_enable : 2; // 10-11 caam_wrapper_aclk clock (caam_wrapper_aclk_enable)
+ UINT32 caam_wrapper_ipg_enable : 2; // 12-13 caam_wrapper_ipg clock (caam_wrapper_ipg_enable)
+ UINT32 can1_clk_enable : 2; // 14-15 can1 clock (can1_clk_enable)
+ UINT32 can1_serial_clk_enable : 2; // 16-17 can1_serial clock (can1_serial_clk_enable)
+ UINT32 can2_clk_enable : 2; // 18-19 can2 clock (can2_clk_enable)
+ UINT32 can2_serial_clk_enable : 2; // 20-21 can2_serial clock (can2_serial_clk_enable)
+ UINT32 arm_dbg_clk_enable : 2; // 22-23 CPU debug clocks (arm_dbg_clk_enable)
+ UINT32 dcic1_clk_enable : 2; // 24-25 dcic 1 clocks (dcic1_clk_enable)
+ UINT32 dcic2_clk_enable : 2; // 26-27 dcic2 clocks (dcic2_clk_enable)
+ UINT32 dtcp_clk_enable : 2; // 28-29 dtcp clocks (dtcp_clk_enable)
+ UINT32 reserved : 2; // 30-31
+ // MSB
+ };
+} IMX_CCM_CCGR0_REG;
+
+// CHSCCDR.ipu1_di0_clk_sel
+typedef enum {
+ IMX_CHSCCDR_IPU1_DI0_CLK_SEL_PREMUX, // 0
+ IMX_CHSCCDR_IPU1_DI0_CLK_SEL_IPP_DI0_CLK, // 1
+ IMX_CHSCCDR_IPU1_DI0_CLK_SEL_IPP_DI1_CLK, // 2
+ IMX_CHSCCDR_IPU1_DI0_CLK_SEL_LDB_DI0_CLK, // 3
+ IMX_CHSCCDR_IPU1_DI0_CLK_SEL_LDB_DI1_CLK, // 4
+} IMX_CHSCCDR_IPU1_DI0_CLK_SEL;
+
+// CHSCCDR.ipu1_di0_podf
+typedef enum {
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_1, // 0
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_2, // 1
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_3,
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_4,
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_5,
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_6,
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_7,
+ IMX_CHSCCDR_IPU1_DI0_PODF_DIV_8,
+} IMX_CHSCCDR_IPU1_DI0_PODF;
+
+// CHSCCDR.ipu1_di0_pre_clk_sel
+typedef enum {
+ IMX_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MMDC_CH0, // 0
+ IMX_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL3_SW_CLK, // 1
+ IMX_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL5, // 2
+ IMX_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL2_PFD0,
+ IMX_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL2_PFD2,
+ IMX_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_PLL3_PFD1,
+} IMX_CHSCCDR_IPU1_DI0_PRE_CLK_SEL;
+
+// CHSCCDR.ipu1_di1_clk_sel
+typedef enum {
+ IMX_CHSCCDR_IPU1_DI1_CLK_SEL_PREMUX, // 0
+ IMX_CHSCCDR_IPU1_DI1_CLK_SEL_IPP_DI0_CLK, // 1
+ IMX_CHSCCDR_IPU1_DI1_CLK_SEL_IPP_DI1_CLK, // 2
+ IMX_CHSCCDR_IPU1_DI1_CLK_SEL_LDB_DI0_CLK, // 3
+ IMX_CHSCCDR_IPU1_DI1_CLK_SEL_LDB_DI1_CLK, // 4
+} IMX_CHSCCDR_IPU1_DI1_CLK_SEL;
+
+// CHSCCDR.ipu1_di1_podf
+typedef enum {
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_1, // 0
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_2,
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_3,
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_4,
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_5,
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_6,
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_7,
+ IMX_CHSCCDR_IPU1_DI1_PODF_DIV_8,
+} IMX_CHSCCDR_IPU1_DI1_PODF;
+
+// CHSCCDR.ipu1_di1_pre_clk_sel
+typedef enum {
+ IMX_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MMDC_CH0, // 0
+ IMX_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_PLL3_SW_CLK, // 1
+ IMX_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_PLL5, // 2
+ IMX_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_PLL2_PFD0,
+ IMX_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_PLL2_PFD2,
+ IMX_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_PLL3_PFD1,
+} IMX_CHSCCDR_IPU1_DI1_PRE_CLK_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ipu1_di0_clk_sel : 3; // 0-2 Selector for ipu1 di0 root clock multiplexer
+ UINT32 ipu1_di0_podf : 3; // 3-5 Divider for ipu1_di0 clock divider
+ UINT32 ipu1_di0_pre_clk_sel : 3; // 6-8 Selector for ipu1 di0 root clock pre-multiplexer
+ UINT32 ipu1_di1_clk_sel : 3; // 9-11 Selector for ipu1 di1 root clock multiplexer
+ UINT32 ipu1_di1_podf : 3; // 12-14 Divider for ipu1_di clock divider
+ UINT32 ipu1_di1_pre_clk_sel : 3; // 15-17 Selector for ipu1 di1 root clock pre-multiplexer
+ UINT32 reserved : 14; // 18-31
+ // MSB
+ };
+} IMX_CCM_CHSCCDR_REG;
+
+//
+// NOTE: OPENVG clock cannot be gated without gating GPU2D clock as well.
+// Configure both CG bits (CCM_ANALOG_CCGR1[CG12] and
+// CCM_ANALOG_CCGR3[CG15]) to gate OPENVG.
+//
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ecspi1_clk_enable : 2; // 0-1 ecspi1 clocks (ecspi1_clk_enable)
+ UINT32 ecspi2_clk_enable : 2; // 2-3 ecspi2 clocks (ecspi2_clk_enable)
+ UINT32 ecspi3_clk_enable : 2; // 4-5 ecspi3 clocks (ecspi3_clk_enable)
+ UINT32 ecspi4_clk_enable : 2; // 6-7 ecspi4 clocks (ecspi4_clk_enable)
+ UINT32 ecspi5_clk_enable : 2; // 8-9 ecspi5 clocks (ecspi5_clk_enable)
+ UINT32 enet_clk_enable : 2; // 10-11 enet clock (enet_clk_enable)
+ UINT32 epit1_clk_enable : 2; // 12-13 epit1 clocks (epit1_clk_enable)
+ UINT32 epit2_clk_enable : 2; // 14-15 epit2 clocks (epit2_clk_enable)
+ UINT32 esai_clk_enable : 2; // 16-17 esai clocks (esai_clk_enable)
+ UINT32 reserved1 : 2; // 18-19
+ UINT32 gpt_clk_enable : 2; // 20-21 gpt bus clock (gpt_clk_enable)
+ UINT32 gpt_serial_clk_enable : 2; // 22-23 gpt serial clock (gpt_serial_clk_enable)
+ UINT32 gpu2d_clk_enable : 2; // 24-25 gpu2d clock (gpu2d_clk_enable)
+ UINT32 gpu3d_clk_enable : 2; // 26-27 gpu3d clock (gpu3d_clk_enable)
+ UINT32 reserved2 : 4; // 28-31
+ // MSB
+ };
+} IMX_CCM_CCGR1_REG;
+
+// CBCDR.axi_sel
+typedef enum {
+ IMX_CCM_AXI_SEL_PERIPH_CLK,
+ IMX_CCM_AXI_SEL_AXI_ALT,
+} IMX_CCM_AXI_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 periph2_clk2_podf : 3; // 0-2 Divider for periph2_clk2 podf
+ UINT32 mmdc_ch1_axi_podf : 3; // 3-5 Divider for mmdc_ch1_axi podf
+ UINT32 axi_sel : 1; // 6 AXI clock source select (IMX_CCM_AXI_SEL)
+ UINT32 axi_alt_sel : 1; // 7 AXI alternative clock select
+ UINT32 ipg_podf : 2; // 8-9 Divider for ipg podf.
+ UINT32 ahb_podf : 3; // 10-12 Divider for AHB PODF.
+ UINT32 reserved1 : 3; // 13-15
+ UINT32 axi_podf : 3; // 16-18 Divider for axi podf
+ UINT32 mmdc_ch0_axi_podf : 3; // 19-21 Divider for mmdc_ch0_axi podf.
+ UINT32 reserved2 : 3; // 22-24
+ UINT32 periph_clk_sel : 1; // 25 Selector for peripheral main clock (source of MMDC_CH0_CLK_ROOT).
+ UINT32 periph2_clk_sel : 1; // 16 Selector for peripheral2 main clock (source of mmdc_ch1_clk_root
+ UINT32 periph_clk2_podf : 3; // 27-29 Divider for periph2 clock podf.
+ UINT32 reserved3 : 2; // 30-31
+ // MSB
+ };
+} IMX_CCM_CBCDR_REG;
+
+// CCOSR.CLKO1_SEL
+typedef enum {
+ IMX_CCM_CLKO1_SEL_PLL3_SW_CLK_2,
+ IMX_CCM_CLKO1_SEL_PLL2_MAIN_CLK_2,
+ IMX_CCM_CLKO1_SEL_PLL1_MAIN_CLK_2,
+ IMX_CCM_CLKO1_SEL_PLL5_MAIN_CLK_2,
+ IMX_CCM_CLKO1_SEL_VIDEO_27M_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_AXI_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_ENFC_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_IPU1_DI0_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_IPU1_DI1_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_IPU2_DI0_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_IPU2_DI1_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_AHB_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_IPG_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_PERCLK_ROOT,
+ IMX_CCM_CLKO1_SEL_CKIL_SYNC_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_PLL4_MAIN_CLK,
+} IMX_CCM_CLKO1_SEL;
+
+// CCOSR.CLK_OUT_SEL
+typedef enum {
+ IMX_CCM_CLK_OUT_SEL_CCM_CLKO1,
+ IMX_CCM_CLK_OUT_SEL_CCM_CLKO2,
+} IMX_CCM_CLK_OUT_SEL;
+
+// CCOSR.CLKO2_SEL
+typedef enum {
+ IMX_CCM_CLKO2_SEL_MMDC_CH0_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_MMDC_CH1_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_USDHC4_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_USDHC1_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_GPU2D_AXI_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_WRCK_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_ECSPI_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_GPU3D_AXI_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_USDHC3_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_125M_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_ARM_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_IPU1_HSP_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_IPU2_HSP_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_VDO_AXI_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_OSC_CLK,
+ IMX_CCM_CLKO2_SEL_GPU2D_CORE_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_GPU3D_CORE_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_USDHC2_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_SSI1_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_SSI2_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_SSI3_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_GPU3D_SHADER_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_VPU_AXI_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_CAN_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_LDB_DI0_SERIAL_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_LDB_DI1_SERIAL_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_ESAI_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_ACLK_EIM_SLOW_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_UART_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_SPDIF0_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_SPDIF1_CLK_ROOT,
+ IMX_CCM_CLKO2_SEL_HSI_TX_CLK_ROOT,
+} IMX_CCM_CLKO2_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 CLKO1_SEL : 4; // 0-3 Selection of the clock to be generated on CCM_CLKO1 (IMX_CCM_CLKO1_SEL)
+ UINT32 CLKO1_DIV : 3; // 4-6 Setting the divider of CCM_CLKO1
+ UINT32 CLKO1_EN : 1; // 7 Enable of CCM_CLKO1 clock
+ UINT32 CLK_OUT_SEL : 1; // 8 CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks
+ UINT32 reserved1 : 7; // 9-15
+ UINT32 CLKO2_SEL : 5; // 16-20 Selection of the clock to be generated on CCM_CLKO2 (IMX_CCM_CLKO2_SEL)
+ UINT32 CLKO2_DIV : 3; // 21-23 Setting the divider of CCM_CLKO2
+ UINT32 CLKO2_EN : 1; // 24 Enable of CCM_CLKO2 clock
+ UINT32 reserved2 : 7; // 25-31
+ // MSB
+ };
+} IMX_CCM_CCOSR_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ipu1_ipu_clk_enable : 2; // 0-1 ipu1_ipu clock (ipu1_ipu_clk_enable)
+ UINT32 ipu1_ipu_di0_clk_enable : 2; // 2-3 ipu1_di0 clock and pre-clock (ipu1_ipu_di0_clk_enable)
+ UINT32 ipu1_ipu_di1_clk_enable : 2; // 4-5 ipu1_di1 clock and pre-clock (ipu1_ipu_di1_clk_enable)
+ UINT32 ipu2_ipu_clk_enable : 2; // 6-7 ipu2_ipu clock (ipu2_ipu_clk_enable)
+ UINT32 ipu2_ipu_di0_clk_enable : 2; // 8-9 ipu2_di0 clock and pre-clock (ipu2_ipu_di0_clk_enable)
+ UINT32 ipu2_ipu_di1_clk_enable : 2; // 10-11 ipu2_di1 clock and pre-clock (ipu2_ipu_di1_clk_enable)
+ UINT32 ldb_di0_clk_enable : 2; // 12-13 ldb_di0 clock (ldb_di0_clk_enable)
+ UINT32 ldb_di1_clk_enable : 2; // 14-15 ldb_di1 clock (ldb_di1_clk_enable)
+ UINT32 mipi_core_cfg_clk_enable : 2; // 16-17 mipi_core_cfg clock (mipi_core_cfg_clk_enable)
+ UINT32 mlb_clk_enable : 2; // 18-19 mlb clock (mlb_clk_enable)
+ UINT32 mmdc_core_aclk_fast_core_p0_enable : 2; // 20-21 mmdc_core_aclk_fast_core_p0 clock (mmdc_core_aclk_fast_core_p0_enable)
+ UINT32 reserved1 : 2; // 22-23
+ UINT32 mmdc_core_ipg_clk_p0_enable : 2; // 24-25 mmdc_core_ipg_clk_p0 clock (mmdc_core_ipg_clk_p0_enable)
+ UINT32 reserved2 : 2; // 26-27
+ UINT32 ocram_clk_enable : 2; // 28-29 ocram clock (ocram_clk_enable)
+ UINT32 openvgaxiclk_clk_root_enable : 2; // 30-31 openvgaxiclk clock (openvgaxiclk_clk_root_enable)
+ // MSB
+ };
+} IMX_CCM_CCGR3_REG;
+
+typedef struct {
+ UINT32 CCR; // 0x00 CCM Control Register (CCM_CCR)
+ UINT32 CCDR; // 0x04 CCM Control Divider Register (CCM_CCDR)
+ UINT32 CSR; // 0x08 CCM Status Register (CCM_CSR)
+ UINT32 CCSR; // 0x0C CCM Clock Switcher Register (CCM_CCSR)
+ UINT32 CACRR; // 0x10 CCM Arm Clock Root Register (CCM_CACRR)
+ UINT32 CBCDR; // 0x14 CCM Bus Clock Divider Register (CCM_CBCDR)
+ UINT32 CBCMR; // 0x18 CCM Bus Clock Multiplexer Register (CCM_CBCMR)
+ UINT32 CSCMR1; // 0x1C CCM Serial Clock Multiplexer Register 1 (CCM_CSCMR1)
+ UINT32 CSCMR2; // 0x20 CCM Serial Clock Multiplexer Register 2 (CCM_CSCMR2)
+ UINT32 CSCDR1; // 0x24 CCM Serial Clock Divider Register 1 (CCM_CSCDR1)
+ UINT32 CS1CDR; // 0x28 CCM SSI1 Clock Divider Register (CCM_CS1CDR)
+ UINT32 CS2CDR; // 0x2C CCM SSI2 Clock Divider Register (CCM_CS2CDR)
+ UINT32 CDCDR; // 0x30 CCM D1 Clock Divider Register (CCM_CDCDR)
+ UINT32 CHSCCDR; // 0x34 CCM HSC Clock Divider Register (CCM_CHSCCDR)
+ UINT32 CSCDR2; // 0x38 CCM Serial Clock Divider Register 2 (CCM_CSCDR2)
+ UINT32 CSCDR3; // 0x3C CCM Serial Clock Divider Register 3 (CCM_CSCDR3)
+ UINT32 reserved1[2];
+ UINT32 CDHIPR; // 0x48 CCM Divider Handshake In-Process Register (CCM_CDHIPR)
+ UINT32 reserved2[2];
+ UINT32 CLPCR; // 0x54 CCM Low Power Control Register (CCM_CLPCR)
+ UINT32 CISR; // 0x58 CCM Interrupt Status Register (CCM_CISR)
+ UINT32 CIMR; // 0x5C CCM Interrupt Mask Register (CCM_CIMR)
+ UINT32 CCOSR; // 0x60 CCM Clock Output Source Register (CCM_CCOSR)
+ UINT32 CGPR; // 0x64 CCM General Purpose Register (CCM_CGPR)
+ UINT32 CCGR[7]; // 0x68-7C CCM Clock Gating Register 0-6 (CCM_CCGR0-CCM_CCGR6)
+ UINT32 reserved3[1];
+ UINT32 CMEOR; // 0x88 CCM Module Enable Override Register (CCM_CMEOR)
+} IMX_CCM_REGISTERS;
+
+//
+// CCM Analog
+//
+
+typedef enum {
+ IMX_PLL_BYPASS_CLK_SRC_REF_CLK_24M,
+ IMX_PLL_BYPASS_CLK_SRC_CLK1,
+ IMX_PLL_BYPASS_CLK_SRC_CLK2,
+ IMX_PLL_BYPASS_CLK_SRC_XOR,
+} IMX_PLL_BYPASS_CLK_SRC;
+
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 DIV_SELECT : 7; // 0-6 Valid range for divider value: 54-108. Fout = Fin * div_select/2.0
+ UINT32 reserved1 : 5; // 7-11
+ UINT32 POWERDOWN : 1; // 12 Powers down the PLL.
+ UINT32 ENABLE: 1; // 13 Enable the clock output.
+ UINT32 BYPASS_CLK_SRC : 2; // 14-15 Determines the bypass and PLL reference clock source.
+ UINT32 BYPASS : 1; // 16 Bypass the PLL.
+ UINT32 LVDS_SEL : 1; // 17 Analog Debug Bit
+ UINT32 LVDS_24MHZ_SEL : 1; // 18 Analog Debug Bit
+ UINT32 reserved2 : 1; // 19 PLL_SEL (Reserved)
+ UINT32 reserved3 : 11; // 20-30
+ UINT32 LOCK : 1; // 31 1 - PLL is currently locked. 0 - PLL is not currently locked.
+ // MSB
+ };
+} IMX_CCM_ANALOG_PLL_ARM_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 DIV_SELECT : 1; // 0 0 - Fout=Fref*20; 1 - Fout=Fref*22.
+ UINT32 reserved1 : 11; // 1-11
+ UINT32 POWERDOWN : 1; // 12 Powers down the PLL.
+ UINT32 ENABLE : 1; // 13 Enable PLL output
+ UINT32 BYPASS_CLK_SRC : 2; // 14-15 Determines the bypass source.
+ UINT32 BYPASS : 1; // 16 Bypass the PLL.
+ UINT32 reserved2 : 1; // 17
+ UINT32 PFD_OFFSET_EN : 1; // 18 Enables an offset in the phase frequency detector
+ UINT32 reserved3 : 12; // 19-30
+ UINT32 LOCK : 1; // 31 1 - PLL is currently locked; 0 - PLL is not currently locked.
+ // MSB
+ };
+} IMX_CCM_ANALOG_PLL_SYS_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 DIV_SELECT : 2; // 0-1 - Fout=Fref*20; 1 - Fout=Fref*22.
+ UINT32 reserved1 : 4; // 2-5
+ UINT32 EN_USB_CLKS : 1; // 6 Powers the 9-phase PLL outputs for USBPHYn
+ UINT32 reserved2 : 5; // 7-11
+ UINT32 POWER : 1; // 12 Powers up the PLL.
+ UINT32 ENABLE : 1; // 13 Enable the PLL clock output
+ UINT32 BYPASS_CLK_SRC : 2; // 14-15 Determines the bypass source
+ UINT32 BYPASS : 1; // 16 Bypass the PLL.
+ UINT32 reserved3 : 14; // 17-30
+ UINT32 LOCK : 1; // 31 1 - PLL is currently locked
+ // MSB
+ };
+} IMX_CCM_ANALOG_PLL_USB1_REG;
+
+typedef enum {
+ IMX_POST_DIV_SELECT_DIVIDE_4,
+ IMX_POST_DIV_SELECT_DIVIDE_2,
+ IMX_POST_DIV_SELECT_DIVIDE_1,
+} IMX_CCM_PLL_VIDEO_CTRL_POST_DIV_SELECT;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 DIV_SELECT : 7; // 0-6 This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54
+ UINT32 Reserved1 : 5; // 7-11
+ UINT32 POWERDOWN : 1; // 12 Powers down the PLL
+ UINT32 ENABLE : 1; // 13 Enalbe PLL output
+ UINT32 BYPASS_CLK_SRC : 2; // 14-15 Determines the bypass source
+ UINT32 BYPASS : 1; // 16 Bypass the PLL
+ UINT32 Reserved2 : 1; // 17
+ UINT32 PFD_OFFSET_EN : 1; // 18 Enables an offset in the phase frequency detector
+ UINT32 POST_DIV_SELECT : 2; // 19-20 These bits implement a divider after the PLL, but before the enable and bypass mux.
+ UINT32 Reserved3 : 1; // 21
+ UINT32 Reserved4 : 9; // 22-30 Always set to zero
+ UINT32 LOCK : 1; // 31 PLL is/not currently locked
+ // MSB
+ };
+} IMX_CCM_PLL_VIDEO_CTRL_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 PFD0_FRAC : 6; // 0-5 fractional divide value. The resulting frequency shall be 528*18/PFD0_FRAC where PFD0_FRAC is in the range 12-35.
+ UINT32 PFD0_STABLE : 1; // 6
+ UINT32 PFD0_CLKGATE : 1; // 7 Set to 1 to gate ref_pfd0
+ UINT32 PFD1_FRAC : 6; // 8-13 fractional divide value
+ UINT32 PFD1_STABLE : 1; // 14
+ UINT32 PFD1_CLKGATE : 1; // 15 Set to 1 to gate ref_pfd1
+ UINT32 PFD2_FRAC : 6; // 16-21 fractional divide value
+ UINT32 PFD2_STABLE : 1; // 22
+ UINT32 PFD2_CLKGATE : 1; // 23 Set to 1 to gate ref_pfd2
+ UINT32 PFD3_FRAC : 6; // 24-29 fractional divide value
+ UINT32 PFD3_STABLE : 1; // 30
+ UINT32 PFD3_CLKGATE : 1; // 31 Set to 1 to gate ref_pfd3
+ // MSB
+ };
+} IMX_CCM_PFD_480_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 PFD0_FRAC : 6; // 0-5 fractional divide value. The resulting frequency shall be 528*18/PFD0_FRAC where PFD0_FRAC is in the range 12-35.
+ UINT32 PFD0_STABLE : 1; // 6
+ UINT32 PFD0_CLKGATE : 1; // 7 Set to 1 to gate ref_pfd0
+ UINT32 PFD1_FRAC : 6; // 8-13 fractional divide value
+ UINT32 PFD1_STABLE : 1; // 14
+ UINT32 PFD1_CLKGATE : 1; // 15 Set to 1 to gate ref_pfd1
+ UINT32 PFD2_FRAC : 6; // 16-21 fractional divide value
+ UINT32 PFD2_STABLE : 1; // 22
+ UINT32 PFD2_CLKGATE : 1; // 23 Set to 1 to gate ref_pfd2
+ UINT32 reserved : 8; // 24-31
+ // MSB
+ };
+} IMX_CCM_PFD_528_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 REG0_TARG : 5; // 0-4 target voltage for the ARM core power domain
+ UINT32 reserved1 : 4; // 5-8
+ UINT32 REG1_TARG : 5; // 9-13 target voltage for the VPU/GPU power domain
+ UINT32 reserved2 : 4; // 14-17
+ UINT32 REG2_TARG : 5; // 18-22 target voltage for the SOC power domain
+ UINT32 reserved3 : 6; // 23-28
+ UINT32 FET_ODRIVE : 1; // 29 increases the gate drive on power gating FET
+ UINT32 reserved4 : 2; // 30-31
+ // MSB
+ };
+} IMX_PMU_REG_CORE_REG;
+
+typedef enum {
+ PLL_ENET_DIV_SELECT_25MHZ = 0,
+ PLL_ENET_DIV_SELECT_50MHZ = 1,
+ PLL_ENET_DIV_SELECT_100MHZ = 2,
+ PLL_ENET_DIV_SELECT_125MHZ = 3,
+} CCM_ANALOG_PLL_ENET_DIV_SELECT;
+
+//
+// CCM ANALOG PLL Ethernet(n) register
+//
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ unsigned DIV_SELECT : 2; // 0-1
+ unsigned Zero1 : 5; // 2-6
+ unsigned Reserved1 : 5; // 7-11
+ unsigned POWERDOWN : 1; // 12
+ unsigned ENABLE : 1; // 13
+ unsigned BYPASS_CLK_SRC : 2; // 14-15
+ unsigned BYPASS : 1; // 16
+ unsigned Reserved2 : 1; // 17
+ unsigned PFD_OFFSET_EN : 1; // 18
+ unsigned ENABLE_125M : 1; // 19
+ unsigned ENABLE_100M : 1; // 20
+ unsigned Zero2 : 10; // 21-30
+ unsigned LOCK : 1; // 31
+ // MSB
+ };
+} IMX_CCM_ANALOG_PLL_ENET_REG;
+
+//
+// CCM ANALOG PLL Ethernet(n) register
+//
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ unsigned LVDS1_CLK_SEL : 5; // 0-4
+ unsigned LVDS2_CLK_SEL : 5; // 5-9
+ unsigned LVDSCLK1_OBEN : 1; // 10
+ unsigned LVDSCLK2_OBEN : 1; // 11
+ unsigned LVDSCLK1_IBEN : 1; // 12
+ unsigned LVDSCLK2_IBEN : 1; // 13
+ unsigned Reserved0 : 15; // 14-28
+ unsigned IRQ_TEMPSENSE : 1; // 29
+ unsigned IRQ_ANA_BO : 1; // 30
+ unsigned IRQ_DIG_BO : 1; // 31
+ // MSB
+ };
+} IMX_CCM_ANALOG_MISC1_REG;
+
+typedef struct {
+ UINT32 PLL_ARM; // 0x000 Analog ARM PLL control Register (CCM_ANALOG_PLL_ARM)
+ UINT32 PLL_ARM_SET; // 0x004 Analog ARM PLL control Register (CCM_ANALOG_PLL_ARM_SET)
+ UINT32 PLL_ARM_CLR; // 0x008 Analog ARM PLL control Register (CCM_ANALOG_PLL_ARM_CLR)
+ UINT32 PLL_ARM_TOG; // 0x00C Analog ARM PLL control Register (CCM_ANALOG_PLL_ARM_TOG)
+ UINT32 PLL_USB1; // 0x010 Analog USB1 480MHz PLL Control Register (CCM_ANALOG_PLL_USB1)
+ UINT32 PLL_USB1_SET; // 0x014 Analog USB1 480MHz PLL Control Register (CCM_ANALOG_PLL_USB1_SET)
+ UINT32 PLL_USB1_CLR; // 0x018 Analog USB1 480MHz PLL Control Register (CCM_ANALOG_PLL_USB1_CLR)
+ UINT32 PLL_USB1_TOG; // 0x01C Analog USB1 480MHz PLL Control Register (CCM_ANALOG_PLL_USB1_TOG)
+ UINT32 PLL_USB2; // 0x020 Analog USB2 480MHz PLL Control Register (CCM_ANALOG_PLL_USB2)
+ UINT32 PLL_USB2_SET; // 0x024 Analog USB2 480MHz PLL Control Register (CCM_ANALOG_PLL_USB2_SET)
+ UINT32 PLL_USB2_CLR; // 0x028 Analog USB2 480MHz PLL Control Register (CCM_ANALOG_PLL_USB2_CLR)
+ UINT32 PLL_USB2_TOG; // 0x02C Analog USB2 480MHz PLL Control Register (CCM_ANALOG_PLL_USB2_TOG)
+ UINT32 PLL_SYS; // 0x030 Analog System PLL Control Register (CCM_ANALOG_PLL_SYS)
+ UINT32 PLL_SYS_SET; // 0x034 Analog System PLL Control Register (CCM_ANALOG_PLL_SYS_SET)
+ UINT32 PLL_SYS_CLR; // 0x038 Analog System PLL Control Register (CCM_ANALOG_PLL_SYS_CLR)
+ UINT32 PLL_SYS_TOG; // 0x03C Analog System PLL Control Register (CCM_ANALOG_PLL_SYS_CLR)
+ UINT32 PLL_SYS_SS; // 0x040 528MHz System PLL Spread Spectrum Register (CCM_ANALOG_PLL_SYS_SS)
+ UINT32 reserved1[3];
+ UINT32 PLL_SYS_NUM; // 0x050 Numerator of 528MHz System PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_SYS_NUM)
+ UINT32 reserved2[3];
+ UINT32 PLL_SYS_DENOM; // 0x060 Denominator of 528MHz System PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_SYS_DENOM)
+ UINT32 reserved3[3];
+ UINT32 PLL_AUDIO; // 0x070 Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIO)
+ UINT32 PLL_AUDIO_SET; // 0x074 Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIO_SET)
+ UINT32 PLL_AUDIO_CLR; // 0x078 Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIO_CLR)
+ UINT32 PLL_AUDIO_TOG; // 0x07C Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIO_TOG)
+ UINT32 PLL_AUDIO_NUM; // 0x080 Numerator of Audio PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_AUDIO_NUM)
+ UINT32 reserved4[3];
+ UINT32 PLL_AUDIO_DENOM; // 0x090 Denominator of Audio PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_AUDIO_DENOM)
+ UINT32 reserved5[3];
+ UINT32 PLL_VIDEO; // 0x0A0 Analog Video PLL control Register (CCM_ANALOG_PLL_VIDEO)
+ UINT32 PLL_VIDEO_SET; // 0x0A4 Analog Video PLL control Register (CCM_ANALOG_PLL_VIDEO_SET)
+ UINT32 PLL_VIDEO_CLR; // 0x0A8 Analog Video PLL control Register (CCM_ANALOG_PLL_VIDEO_CLR)
+ UINT32 PLL_VIDEO_TOG; // 0x0AC Analog Video PLL control Register (CCM_ANALOG_PLL_VIDEO_TOG)
+ UINT32 PLL_VIDEO_NUM; // 0x0B0 Numerator of Video PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_VIDEO_NUM)
+ UINT32 reserved6[3];
+ UINT32 PLL_VIDEO_DENOM; // 0x0C0 Denominator of Video PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_VIDEO_DENOM)
+ UINT32 reserved7[3];
+ UINT32 PLL_MLB; // 0x0D0 MLB PLL Control Register (CCM_ANALOG_PLL_MLB)
+ UINT32 PLL_MLB_SET; // 0x0D4 MLB PLL Control Register (CCM_ANALOG_PLL_MLB_SET)
+ UINT32 PLL_MLB_CLR; // 0x0D8 MLB PLL Control Register (CCM_ANALOG_PLL_MLB_CLR)
+ UINT32 PLL_MLB_TOG; // 0x0DC MLB PLL Control Register (CCM_ANALOG_PLL_MLB_TOG)
+ UINT32 PLL_ENET; // 0x0E0 Analog ENET PLL Control Register (CCM_ANALOG_PLL_ENET)
+ UINT32 PLL_ENET_SET; // 0x0E4 Analog ENET PLL Control Register (CCM_ANALOG_PLL_ENET_SET)
+ UINT32 PLL_ENET_CLR; // 0x0E8 Analog ENET PLL Control Register (CCM_ANALOG_PLL_ENET_CLR)
+ UINT32 PLL_ENET_TOG; // 0x0EC Analog ENET PLL Control Register (CCM_ANALOG_PLL_ENET_TOG)
+ UINT32 PFD_480; // 0x0F0 480MHz Clock (PLL3) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_480)
+ UINT32 PFD_480_SET; // 0x0F4 480MHz Clock (PLL3) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_480_SET)
+ UINT32 PFD_480_CLR; // 0x0F8 480MHz Clock (PLL3) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_480_CLR)
+ UINT32 PFD_480_TOG; // 0x0FC 480MHz Clock (PLL3) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_480_TOG)
+ UINT32 PFD_528; // 0x100 528MHz Clock (PLL2) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_528)
+ UINT32 PFD_528_SET; // 0x104 528MHz Clock (PLL2) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_528_SET)
+ UINT32 PFD_528_CLR; // 0x108 528MHz Clock (PLL2) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_528_CLR)
+ UINT32 PFD_528_TOG; // 0x10C 528MHz Clock (PLL2) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_528_TOG)
+ UINT32 PMU_REG_1P1; // 0x110 Regulator 1P1 Register (PMU_REG_1P1)
+ UINT32 PMU_REG_1P1_SET; // 0x114
+ UINT32 PMU_REG_1P1_CLR; // 0x118
+ UINT32 PMU_REG_1P1_TOG; // 0x11C
+ UINT32 PMU_REG_3P0; // 0X120 Regulator 3P0 Register (PMU_REG_3P0)
+ UINT32 PMU_REG_3P0_SET; // 0x124
+ UINT32 PMU_REG_3P0_CLR; // 0x128
+ UINT32 PMU_REG_3P0_TOG; // 0x12C
+ UINT32 PMU_REG_2P5; // 0x130 Regulator 2P5 Register (PMU_REG_2P5)
+ UINT32 PMU_REG_2P5_SET; // 0x134
+ UINT32 PMU_REG_2P5_CLR; // 0x138
+ UINT32 PMU_REG_2P5_TOG; // 0x13C
+ UINT32 PMU_REG_CORE; // 0x140 Digital Regulator Core Register (PMU_REG_CORE)
+ UINT32 PMU_REG_CORE_SET; // 0x144
+ UINT32 PMU_REG_CORE_CLR; // 0x148
+ UINT32 PMU_REG_CORE_TOG; // 0x14C
+ UINT32 MISC0; // 0x150 Miscellaneous Register 0 (CCM_ANALOG_MISC0)
+ UINT32 MISC0_SET; // 0x154 Miscellaneous Register 0 (CCM_ANALOG_MISC0_SET)
+ UINT32 MISC0_CLR; // 0x158 Miscellaneous Register 0 (CCM_ANALOG_MISC0_CLR)
+ UINT32 MISC0_TOG; // 0x15C Miscellaneous Register 0 (CCM_ANALOG_MISC0_TOG)
+ UINT32 MISC1; // 0x160 Miscellaneous Register 1 (CCM_ANALOG_MISC1)
+ UINT32 MISC1_SET; // 0x164 Miscellaneous Register 1 (CCM_ANALOG_MISC1_SET)
+ UINT32 MISC1_CLR; // 0x168 Miscellaneous Register 1 (CCM_ANALOG_MISC1_CLR)
+ UINT32 MISC1_TOG; // 0x16C Miscellaneous Register 1 (CCM_ANALOG_MISC1_TOG)
+ UINT32 MISC2; // 0x170 Miscellaneous Register 2 (CCM_ANALOG_MISC2)
+ UINT32 MISC2_SET; // 0x174 Miscellaneous Register 2 (CCM_ANALOG_MISC2_SET)
+ UINT32 MISC2_CLR; // 0x178 Miscellaneous Register 2 (CCM_ANALOG_MISC2_CLR)
+ UINT32 MISC2_TOG; // 0x17C Miscellaneous Register 2 (CCM_ANALOG_MISC2_TOG)
+} IMX_CCM_ANALOG_REGISTERS;
+
+//
+// General Power Controller (GPC)
+//
+
+#define IMX_GPC_BASE 0x020DC000
+#define IMX_GPC_LENGTH 0x1000
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 PCR : 1; // 0 Power Control
+ UINT32 reserved : 31; // 1-31
+ // MSB
+ };
+} IMX_GPC_PGC_PGCR_REG;
+
+#define IMX_GPC_PGC_PUPSCR_SW_DEFAULT 1
+#define IMX_GPC_PGC_PUPSCR_SW2ISO_DEFAULT 0xf
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 SW : 6; // 0-5 number of IPG clock cycles before asserting power toggle on/off signal (switch_b)
+ UINT32 reserved1 : 2; // 6-7
+ UINT32 SW2ISO : 6; // 8-13 IPG clock cycles before negating isolation
+ UINT32 reserved2 : 18; // 14-31
+ // MSB
+ };
+} IMX_GPC_PGC_PUPSCR_REG;
+
+#define IMX_GPC_PGC_PDNSCR_ISO_DEFAULT 1
+#define IMX_GPC_PGC_PDNSCR_ISO2SW_DEFAULT 1
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ISO : 6; // 0-5 number of IPG clocks before isolation
+ UINT32 reserved1 : 2; // 6-7
+ UINT32 ISO2SW : 6; // 8-13 number of IPG clocks before negating power toggle on/off signal (switch_b)
+ UINT32 reserved2 : 18; // 14-31
+ // MSB
+ };
+} IMX_GPC_PGC_PDNSCR_REG;
+
+typedef struct {
+ UINT32 CTRL; // 0x0 PGC Control Register (PGC_GPU/CPU_CTRL)
+ UINT32 PUPSCR; // 0x4 Power Up Sequence Control Register (PGC_GPU/CPU_PUPSCR)
+ UINT32 PDNSCR; // 0x8 Pull Down Sequence Control Register (PGC_GPU/CPU_PDNSCR)
+ UINT32 SR; // 0xC Power Gating Controller Status Register (PGC_GPU/CPU_SR)
+} IMX_GPC_PGC_REGISTERS;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 gpu_vpu_pdn_req : 1; // 0 GPU/VPU Power Down request. Self-cleared bit.
+ UINT32 gpu_vpu_pup_req : 1; // 1 GPU/VPU Power Up request. Self-cleared bit.
+ UINT32 reserved1 : 14; // 2-15
+ UINT32 DVFS0CR : 1; // 16 DVFS0 (ARM) Change request (bit is read-only)
+ UINT32 reserved2 : 4; // 17-20
+ UINT32 GPCIRQM : 1; // 21 GPC interrupt/event masking
+ UINT32 reserved3 : 10; // 22-31
+ // MSB
+ };
+} IMX_GPC_CNTR_REG;
+
+typedef struct {
+ UINT32 CNTR; // 0x000 GPC Interface control register (GPC_CNTR)
+ UINT32 PGR; // 0x004 GPC Power Gating Register (GPC_PGR)
+ UINT32 IMR1; // 0x008 IRQ masking register 1 (GPC_IMR1)
+ UINT32 IMR2; // 0x00C IRQ masking register 2 (GPC_IMR2)
+ UINT32 IMR3; // 0x010 IRQ masking register 3 (GPC_IMR3)
+ UINT32 IMR4; // 0x014 IRQ masking register 4 (GPC_IMR4)
+ UINT32 ISR1; // 0x018 IRQ status resister 1 (GPC_ISR1)
+ UINT32 ISR2; // 0x01C IRQ status resister 2 (GPC_ISR2)
+ UINT32 ISR3; // 0x020 IRQ status resister 3 (GPC_ISR3)
+ UINT32 ISR4; // 0x024 IRQ status resister 4 (GPC_ISR4)
+ UINT32 reserved1[142];
+ IMX_GPC_PGC_REGISTERS PGC_GPU; // 0x260-0x26C GPU PGC Control
+ UINT32 reserved2[12];
+ IMX_GPC_PGC_REGISTERS PGC_CPU; // 0x2A0-0x2AC CPU PGC Control
+} IMX_GPC_REGISTERS;
+
+//
+// Ethernet controller (ENET)
+//
+
+#define IMX_ENET_BASE 0x02188000
+#define IMX_ENET_LENGTH 0x4000
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 RESET : 1; // 0 Ethernet MAC Reset
+ UINT32 ETHEREN : 1; // 1 Ethernet Enable
+ UINT32 MAGICEN : 1; // 2 Magic Packet Detection Enable
+ UINT32 SLEEP : 1; // 3 Sleep Mode Enable
+ UINT32 EN1588 : 1; // 4 EN1588 Enable
+ UINT32 SPEED : 1; // 5 Selects between 10/100 and 1000 Mbps modes of operation
+ UINT32 DBGEN : 1; // 6 Debug Enable
+ UINT32 STOPEN : 1; // 7 STOPEN Signal Control
+ UINT32 DBSWP : 1; // 8 Descriptor Byte Swapping Enable
+ UINT32 reserved1 : 3; // 9-11
+ UINT32 reserved2 : 20; // 12-31 This field must be set to F_0000h
+ // MSB
+ };
+} IMX_ENET_ECR_REG;
+
+typedef struct {
+ UINT32 reserved0; // 0
+ UINT32 EIR; // 4
+ UINT32 EIMR; // 8
+ UINT32 reserved1; // Ch
+ UINT32 RDAR; // 10h
+ UINT32 TDAR; // 14h
+ UINT32 reserved2[3]; // 18h - 20h
+ UINT32 ECR; // 24h Ethernet Control Register (ENET_ECR)
+ UINT32 reserved3[6]; // 28h - 3Ch
+ UINT32 MMFR; // 40h
+ UINT32 MSCR; // 44h
+ UINT32 reserved4[7]; // 48h - 60h
+ UINT32 MIBC; // 64h
+ UINT32 reserved5[7]; //
+ UINT32 RCR; // 84h
+ UINT32 reserved6[15]; //
+ UINT32 TCR; // C4h
+ UINT32 reserved7[7];
+ UINT32 PALR; // E4h
+ UINT32 PAUR; // E8h
+ UINT32 OPD; // ECh
+ UINT32 reserved8[322];
+} IMX_ENET_REGISTERS;
+
+//
+// GPIO Controller (GPIO)
+//
+
+#define IMX_GPIO_BASE 0x0209C000
+#define IMX_GPIO_LENGTH (7 * 0x4000)
+
+//
+// USB CORE (EHCI)
+//
+
+#define IMX_USBCORE_BASE 0x02184000
+#define IMX_USBCORE_LENGTH 0x200
+#define IMX_USBCMD_OFFSET 0x140
+#define IMX_USBMODE_OFFSET 0x1A8
+
+//
+// To do:
+// - Add the USB Core register file
+//
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 RS : 1; // 0 Run/Stop (RS) . Read/Write. Default 0b. 1=Run. 0=Stop.
+ UINT32 RST : 1; // 1 Controller Reset (RESET) - Read/Write.
+ UINT32 FS_1 : 2; // 2-3 Frame List Size (Read/Write or Read Only). Default 000b.
+ UINT32 PSE : 1; // 4 Periodic Schedule Enable- Read/Write. Default 0b.
+ UINT32 ASE : 1; // 5 Asynchronous Schedule Enable Read/Write. Default 0b.
+ UINT32 IAA : 1; // 6 Interrupt on Async Advance Doorbell Read/Write.
+ UINT32 reserved1 : 1; // 7
+ UINT32 ASP : 2; // 8-9 Asynchronous Schedule Park Mode Count (OPTIONAL) . Read/Write.
+ UINT32 reserved2 : 1; // 10 Reserved. These bits are reserved and should be set to zero.
+ UINT32 ASPE : 1; // 11 Asynchronous Schedule Park Mode Enable (OPTIONAL) . Read/Write.
+ UINT32 ATDTW : 1; // 12 Add dTD TripWire C Read/Write. [device mode only]
+ UINT32 SUTW : 1; // 13 Setup TripWire C Read/Write. [device mode only]
+ UINT32 reserved3 : 1; // 14
+ UINT32 FS2 : 1; // 15 Frame List Size - (Read/Write or Read Only). [host mode only]
+ UINT32 ITC : 8; // 16-23 Interrupt Threshold Control Read/Write. Default 08h.
+ UINT32 reserved : 8; // 24-31 Reserved. These bits are reserved and should be set to zero.
+ // LSB
+ };
+} USB_USBCMD_REG;
+
+typedef enum {
+ IMX_USBMODE_IDLE = 0,
+ IMX_USBMODE_DEVICE = 2,
+ IMX_USBMODE_HOST = 3,
+} IMX_USBMODE_CM;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 CM : 2; // 0-1 Controller Mode.
+ UINT32 ES : 1; // 1 Endian Select (0- Little, 1-Big)
+ UINT32 SLOM : 1; // 3 Setup Lockout Mode
+ UINT32 SDIS : 1; // 4 Stream Disable Mode
+ UINT32 reserved : 26; // 5-31
+ // LSB
+ };
+} USB_USBMODE_REG;
+
+//
+// USB Non-CORE
+//
+
+#define IMX_USBNONCORE_BASE 0x02184800
+#define IMX_USBNONCORE_LENGTH 0x20
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 reserved1 : 7; // 0-6
+ UINT32 OVER_CUR_DIS : 1; // 7 Disable Overcurrent Detection
+ UINT32 OVER_CUR_POL : 1; // 8 Polarity of Overcurrent (1-active low, 0-active high)
+ UINT32 PWR_POL : 1; // 9 Power Polarity (1-active high, 0-active low)
+ UINT32 WIE : 1; // 10 Wake-up Interrupt Enable
+ UINT32 RESET : 1; // 11 Force Host 1 UTMI PHY Reset.
+ UINT32 SUSPENDM : 1; // 12 Force Host 1 UTMI PHY Suspend.
+ UINT32 UTMI_ON_CLOCK : 1; // 13 Force UTMI PHY clock output on even if in low-power suspend mode.
+ UINT32 WKUP_SW_EN : 1; // 14 Software Wake-up Enable
+ UINT32 WKUP_SW : 1; // 15 Software Wake-up
+ UINT32 WKUP_ID_EN : 1; // 16 Wake-up on ID change enable
+ UINT32 WKUP_VBUS_EN : 1; // 17 wake-up on VBUS change enable
+ UINT32 reserved2 : 13; // 18-30
+ UINT32 WIR : 1; // 31 Wake-up Interrupt Request
+ // LSB
+ };
+} USBNC_USB_UH_CTRL_REG;
+
+typedef struct {
+ UINT32 USBNC_USB_OTG_CTRL; // 0x00 USB OTG Control Register (USBNC_USB_OTG_CTRL)
+ UINT32 USBNC_USB_UH1_CTRL; // 0x04 USB Host1 Control Register (USBNC_USB_UH1_CTRL)
+ UINT32 USBNC_USB_UH2_CTRL; // 0x08 USB Host2 Control Register (USBNC_USB_UH2_CTRL)
+ UINT32 USBNC_USB_UH3_CTRL; // 0x0C USB Host3 Control Register (USBNC_USB_UH3_CTRL)
+ UINT32 USBNC_USB_UH2_HSIC_CTRL; // 0x10 USB Host2 HSIC Control Register (USBNC_USB_UH2_HSIC_CTRL)
+ UINT32 USBNC_USB_UH3_HSIC_CTRL; // 0x14 USB Host3 HSIC Control Register (USBNC_USB_UH3_HSIC_CTRL)
+ UINT32 USBNC_USB_OTG_PHY_CTRL_0; // 0x18 OTG UTMI PHY Control 0 Register (USBNC_USB_OTG_PHY_CTRL_0)
+ UINT32 USBNC_USB_UH1_PHY_CTRL_0; // 0x1C Host1 UTMI PHY Control 0 Register (USBNC_USB_UH1_PHY_CTRL_0)
+} IMX_USBNONCORE_REGISTERS;
+
+
+//
+// USB PHY
+//
+
+#define IMX_USBPHY1_BASE 0x020C9000
+#define IMX_USBPHY2_BASE 0x020CA000
+#define IMX_USBPHY_LENGTH 0x1000
+
+typedef enum {
+ IMX_USBPHY0, // OTG
+ IMX_USBPHY1,
+
+ IMX_USBPHY_COUNT
+} IMX_USBPHY_ID;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ENOTG_ID_CHG_IRQ : 1; // 0 Enable OTG_ID_CHG_IRQ.
+ UINT32 ENHOSTDISCONDETECT : 1; // 1 For host mode, enables high-speed disconnect detector.
+ UINT32 ENIRQHOSTDISCON : 1; // 2 Enables interrupt for detection of disconnection to Device when in high-speed host mode.
+ UINT32 HOSTDISCONDETECT_IRQ : 1; // 3 Indicates that the device has disconnected in high-speed mode.
+ UINT32 ENDEVPLUGINDETECT : 1; // 4 For device mode, enables 200-KOhm pullups for detecting connectivity to the host.
+ UINT32 DEVPLUGIN_POLARITY : 1; // 5 For device mode interrupt generation polarity
+ UINT32 OTG_ID_CHG_IRQ : 1; // 6 OTG ID change interrupt. Indicates the value of ID pin changed.
+ UINT32 ENOTGIDDETECT : 1; // 7 Enables circuit to detect resistance of MiniAB ID pin.
+ UINT32 RESUMEIRQSTICKY : 1; // 8 1 makes RESUME_IRQ bit a sticky bit.
+ UINT32 ENIRQRESUMEDETECT : 1; // 9 Enables interrupt for detection of a non-J state on the USB line.
+ UINT32 RESUME_IRQ : 1; // 10 Indicates that the host is sending a wake-up after suspend
+ UINT32 ENIRQDEVPLUGIN : 1; // 11 Enables interrupt for the detection of connectivity to the USB line.
+ UINT32 DEVPLUGIN_IRQ : 1; // 12 Indicates that the device is connected
+ UINT32 DATA_ON_LRADC : 1; // 13 Enables the LRADC to monitor USB_DP and USB_DM.
+ UINT32 ENUTMILEVEL2 : 1; // 14 Enables UTMI+ Level2.
+ UINT32 ENUTMILEVEL3 : 1; // 15 Enables UTMI+ Level3.
+ UINT32 ENIRQWAKEUP : 1; // 16 Enables interrupt for the wakeup events
+ UINT32 WAKEUP_IRQ : 1; // 17 Indicates that there is a wakeup event.
+ UINT32 reserved1 : 1; // 18 reserved
+ UINT32 ENAUTOCLR_CLKGATE : 1; // 19 Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended.
+ UINT32 ENAUTOCLR_PHY_PWD : 1; // 20 Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended
+ UINT32 ENDPDMCHG_WKUP : 1; // 21 Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended
+ UINT32 ENIDCHG_WKUP : 1; // 22 Enables the feature to wakeup USB if ID is toggled when USB is suspended
+ UINT32 ENVBUSCHG_WKUP : 1; // 23 Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.
+ UINT32 FSDLL_RST_EN : 1; // 24 Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.
+ UINT32 reserved2 : 2; // 25-26
+ UINT32 OTG_ID_VALUE : 1; // 27
+ UINT32 HOST_FORCE_LS_SE0 : 1; // 28 Forces the next FS packet that is transmitted to have a EOP with LS timing.
+ UINT32 UTMI_SUSPENDM : 1; // 29 Used by the PHY to indicate a powered-down state.
+ UINT32 CLKGATE : 1; // 30 Gate UTMI Clocks. Clear to 0 to run clocks.
+ UINT32 SFTRST : 1; // 31 Soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, Set to 0 to release the PHY from reset.
+ // MSB
+ };
+} USBPHYx_CTRL_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 STEP : 16; // 0-15 Fixed read-only value reflecting the stepping of the RTL version.
+ UINT32 MINOR : 8; // 16-23 Fixed read-only value reflecting the MINOR field of the RTL version.
+ UINT32 MAJOR : 8; // 24-31 Fixed read-only value reflecting the MAJOR field of the RTL version
+ // MSB
+ };
+} USBPHYx_VERSION_REG;
+
+typedef struct {
+ UINT32 USBPHY_PWD; // 0x00 USB PHY Power-Down Register (USBPHY_PWD)
+ UINT32 USBPHY_PWD_SET; // 0x04 USB PHY Power-Down Register (USBPHY_PWD_SET)
+ UINT32 USBPHY_PWD_CLR; // 0x08 USB PHY Power-Down Register (USBPHY_PWD_CLR)
+ UINT32 USBPHY_PWD_TOG; // 0x0C USB PHY Power-Down Register (USBPHY_PWD_TOG)
+ UINT32 USBPHY_TX; // 0x10 USB PHY Transmitter Control Register (USBPHY_TX)
+ UINT32 USBPHY_TX_SET; // 0x14 USB PHY Transmitter Control Register (USBPHY_TX_SET)
+ UINT32 USBPHY_TX_CLR; // 0x18 USB PHY Transmitter Control Register (USBPHY_TX_CLR)
+ UINT32 USBPHY_TX_TOG; // 0x1C USB PHY Transmitter Control Register (USBPHY_TX_TOG)
+ UINT32 USBPHY_RX; // 0x20 USB PHY Receiver Control Register (USBPHY_RX)
+ UINT32 USBPHY_RX_SET; // 0x24 USB PHY Receiver Control Register(USBPHY_RX_SET)
+ UINT32 USBPHY_RX_CLR; // 0x28 USB PHY Receiver Control Register (USBPHY_RX_CLR)
+ UINT32 USBPHY_RX_TOG; // 0x2C USB PHY Receiver Control Register (USBPHY_RX_TOG)
+ UINT32 USBPHY_CTRL; // 0x30 USB PHY General Control Register (USBPHY_CTRL)
+ UINT32 USBPHY_CTRL_SET; // 0x34 USB PHY General Control Register (USBPHY_CTRL_SET)
+ UINT32 USBPHY_CTRL_CLR; // 0x38 USB PHY General Control Register (USBPHY_CTRL_CLR)
+ UINT32 USBPHY_CTRL_TOG; // 0x3C USB PHY General Control Register (USBPHY_CTRL_TOG)
+ UINT32 USBPHY_STATUS; // 0x40 USB PHY Status Register (USBPHY_STATUS)
+ UINT32 reserved1[3];
+ UINT32 USBPHY_DEBUG; // 0x50 USB PHY Debug Register (USBPHY_DEBUG)
+ UINT32 USBPHY_DEBUG_SET; // 0x54 USB PHY Debug Register(USBPHY_DEBUG_SET)
+ UINT32 USBPHY_DEBUG_CLR; // 0x58 USB PHY Debug Register (USBPHY_DEBUG_CLR)
+ UINT32 USBPHY_DEBUG_TOG; // 0x5C USB PHY Debug Register(USBPHY_DEBUG_TOG)
+ UINT32 USBPHY_DEBUG0_STATUS; // 0x60 UTMI Debug Status Register 0 (USBPHY_DEBUG0_STATUS)
+ UINT32 reserved2[3];
+ UINT32 USBPHY_DEBUG1; // 0x70 UTMI Debug Status Register 1 (USBPHY_DEBUG1)
+ UINT32 USBPHY_DEBUG1_SET; // 0x74 UTMI Debug Status Register 1 (USBPHY_DEBUG1_SET)
+ UINT32 USBPHY_DEBUG1_CLR; // 0x78 UTMI Debug Status Register 1 (USBPHY_DEBUG1_CLR)
+ UINT32 USBPHY_DEBUG1_TOG; // 0x7C UTMI Debug Status Register 1 (USBPHY_DEBUG1_TOG)
+ UINT32 USBPHY_VERSION; // 0x80 UTMI RTL Version (USBPHYx_VERSION)
+} IMX_USBPHY_REGISTERS;
+
+//
+// USB Analog
+//
+
+#define IMX_USBANA_BASE 0x020C81A0
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 reserved1 : 18; // 0-17
+ UINT32 CHK_CONTACT : 1; // 18
+ UINT32 CHK_CHRG_B : 1; // 19
+ UINT32 EN_B : 1; // 20
+ UINT32 reserved2 : 11; // 21-31
+ // MSB
+ };
+} USB_ANALOG_USB_CHRG_DETECT_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 HS_USE_EXTERNAL_R : 1; // 0 Use external resistor to generate the current bias for the high speed transmitter.
+ UINT32 EN_DEGLITCH : 1; // 1 Enable the deglitching circuit of the USB PLL output.
+ UINT32 reserved1 : 28; // 2-29
+ UINT32 EN_CLK_UTMI : 1; // Enables the clk to the UTMI block.
+ UINT32 reserved2 : 1; // 31
+ // MSB
+ };
+} USB_ANALOG_USB_MISC_REG;
+
+typedef struct {
+ UINT32 USB_ANALOG_USB_VBUS_DETECT; // 0x00 USB VBUS Detect Register (USB_ANALOG_USB_VBUS_DETECT)
+ UINT32 USB_ANALOG_USB_VBUS_DETECT_SET; // 0x04 USB VBUS Detect Register (USB_ANALOG_USB_VBUS_DETECT_SET)
+ UINT32 USB_ANALOG_USB_VBUS_DETECT_CLR; // 0x08 USB VBUS Detect Register (USB_ANALOG_USB_VBUS_DETECT_CLR)
+ UINT32 USB_ANALOG_USB_VBUS_DETECT_TOG; // 0x0C USB VBUS Detect Register (USB_ANALOG_USB_VBUS_DETECT_TOG)
+ UINT32 USB_ANALOG_USB_CHRG_DETECT; // 0x10 USB Charger Detect Register (USB_ANALOG_USB_CHRG_DETECT)
+ UINT32 USB_ANALOG_USB_CHRG_DETECT_SET; // 0x14 USB Charger Detect Register (USB_ANALOG_USB_CHRG_DETECT_SET)
+ UINT32 USB_ANALOG_USB_CHRG_DETECT_CLR; // 0x18 USB Charger Detect Register (USB_ANALOG_USB_CHRG_DETECT_CLR)
+ UINT32 USB_ANALOG_USB_CHRG_DETECT_TOG; // 0x1C USB Charger Detect Register (USB_ANALOG_USB_CHRG_DETECT_TOG)
+ UINT32 USB_ANALOG_USB_VBUS_DETECT_STAT; // 0x20 USB VBUS Detect Status Register (USB_ANALOG_USB_VBUS_DETECT_STAT)
+ UINT32 reserved1[3];
+ UINT32 USB_ANALOG_USB_CHRG_DETECT_STAT; // 0x30 USB Charger Detect Status Register (USB_ANALOG_USB_CHRG_DETECT_STAT)
+ UINT32 reserved2[7];
+ UINT32 USB_ANALOG_USB_MISC; // 0x50 USB Misc Register (USB_ANALOG_USB_MISC)
+ UINT32 USB_ANALOG_USB_MISC_SET; // 0x54 USB Misc Register (USB_ANALOG_USB_MISC_SET)
+ UINT32 USB_ANALOG_USB_MISC_CLR; // 0x58 USB Misc Register (USB_ANALOG_USB_MISC_CLR)
+ UINT32 USB_ANALOG_USB_MISC_TOG; // 0x5C USB Misc Register (USB_ANALOG_USB_MISC_TOG)
+} IMX_USBANA_USB_REGISTERS;
+
+typedef struct {
+ IMX_USBANA_USB_REGISTERS USBANA[IMX_USBPHY_COUNT];
+ UINT32 USB_ANALOG_DIGPROG; // 0xC0 Chip Silicon Version (USB_ANALOG_DIGPROG)
+} IMX_USBANA_REGISTERS;
+
+#pragma pack(pop)
+
+#endif // __IMX6_SDL_H__
diff --git a/Silicon/NXP/iMX6Pkg/Include/iMX6_SX.h b/Silicon/NXP/iMX6Pkg/Include/iMX6_SX.h
new file mode 100644
index 000000000000..5438e9915344
--- /dev/null
+++ b/Silicon/NXP/iMX6Pkg/Include/iMX6_SX.h
@@ -0,0 +1,1762 @@
+/** @file
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#ifndef __IMX6_SX_H__
+#define __IMX6_SX_H__
+
+#pragma pack(push, 1)
+
+// DDR attributes
+#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
+#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
+
+// Boot DRAM region (kernel.img & boot working DRAM)
+#define FRAME_BUFFER_BASE 0x821D4000
+#define FRAME_BUFFER_SIZE 0x00800000 // 8MB
+
+#define BOOT_IMAGE_PHYSICAL_BASE 0x82004000
+#define BOOT_IMAGE_PHYSICAL_LENGTH 0x001D0000 // 1MB
+#define BOOT_IMAGE_ATTRIBUTES CacheAttributes
+
+// The region of registers from 0x00100000 to 0x02300000
+#define SOC_REGISTERS_PHYSICAL_BASE1 0x00100000
+#define SOC_REGISTERS_PHYSICAL_LENGTH1 0x02200000
+#define SOC_REGISTERS_ATTRIBUTES ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
+
+// PCIE registers and configuration space (0x08000000 - 0x09000000)
+#define PCIE_REGISTERS_PHYSICAL_BASE 0x08000000
+#define PCIE_REGISTERS_PHYSICAL_LENGTH 0x01000000
+
+// The region of registers from 0x0C000000 to 0x80000000
+#define SOC_REGISTERS_PHYSICAL_BASE2 0x0C000000
+#define SOC_REGISTERS_PHYSICAL_LENGTH2 0x74000000
+
+// Main system DRAM as defined by the PCD definitions of system memory.
+
+// MPPP definitions
+#define CPU0_MPPP_PHYSICAL_BASE 0x8080F000
+
+// Interrupt controller
+#define CSP_BASE_REG_PA_IC_IFC 0x00A00100
+#define CSP_BASE_REG_PA_IC_DIST 0x00A01000
+
+// L2 cache controller
+#define CSP_BASE_REG_PA_PL310 0x00A02000
+
+// Timers
+#define CSP_BASE_REG_PA_GPT 0x02098000
+#define CSP_BASE_REG_PA_EPIT1 0x020D0000
+#define CSP_BASE_REG_PA_EPIT2 0x020D4000
+
+// Timers IRQs
+#define IC_DIST_VECTOR_BASE 0
+#define IRQ_EPIT1 88
+#define IRQ_EPIT2 89
+
+// SDMA (Smart DMA) controller
+#define CSP_BASE_REG_PA_SDMA 0x020EC000
+#define IRQ_SDMA 34
+
+// SOC peripherals
+#define CSP_BASE_REG_PA_UART1 0x02020000
+#define CSP_BASE_REG_PA_UART2 0x021e8000
+#define CSP_BASE_REG_PA_UART3 0x021EC000
+#define CSP_BASE_REG_PA_UART4 0x021F0000
+#define CSP_BASE_REG_PA_UART5 0x021F4000
+#define CSP_BASE_REG_PA_ESDHC2 0x02194000
+#define CSP_BASE_REG_PA_ESDHC3 0x02198000
+
+#define DBG_PORT_SUBTYPE_IMX6 0x000C
+
+// Timers clock sources
+#define SOC_OSC_FREQUENCY_REF_HZ 24000000 // Oscillator frequency 24Mhz
+#define SOC_HIGH_FREQUENCY_REF_HZ 66000000 // High Frequency reference clock 66Mhz
+#define SOC_LOW_FREQ_REF_HZ 32768 // SNVS RTC frequency 32kHz
+
+// GPU Definitions
+#define IMX_GPU_CORE_CLK_MAX 540000000 // 540 Mhz NEW UNUSED SX RM.p790, Mirroring GPU Constants for DQ
+
+//
+// IOMUX Controller (IOMUXC)
+//
+
+#define IMX_IOMUXC_BASE 0x020E0000
+#define IMX_IOMUXC_LENGTH 0x4000
+
+//
+// Secure Nonvolatile Storage (SNVS)
+//
+
+#define IMX_SNVS_BASE 0x020CC000
+#define IMX_SNVS_LENGTH 0x4000
+#define IMX_SNVS_IP_ID 0x3E
+#define IMX_SNVS_IRQ 51 // SNVS consolidated interrupt
+
+//
+// IOMUXC Registers
+//
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0 0x020E00A4
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1 0x020E00A8
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2 0x020E00AC
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3 0x020E00B0
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4 0x020E00B4
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0 0x020E00B8
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1 0x020E00BC
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2 0x020E00C0
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3 0x020E00C4
+#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4 0x020E00C8
+
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0 0x020E03EC
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1 0x020E03F0
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2 0x020E03F4
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3 0x020E03F8
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4 0x020E03FC
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0 0x020E0400
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1 0x020E0404
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2 0x020E0408
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3 0x020E040C
+#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4 0x020E0410
+
+// define base address of Select Input registers to be one word
+// less than the minimum value so that a valid Select Input value
+// is non-zero. (IOMUXC_SW_PAD_CTL_GRP_B3DS)
+#define IOMUXC_SELECT_INPUT_BASE_ADDRESS 0x20E0620
+
+typedef enum {
+ IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT = 0x20E0624,
+ IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT = 0x20E0628,
+ IOMUXC_AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT = 0x20E062C,
+ IOMUXC_AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT = 0x20E0630,
+ IOMUXC_AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT = 0x20E0634,
+ IOMUXC_AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT = 0x20E0638,
+ IOMUXC_AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT = 0x20E063C,
+ IOMUXC_AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT = 0x20E0640,
+ IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT = 0x20E0644,
+ IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT = 0x20E0648,
+ IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT = 0x20E064C,
+ IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT = 0x20E0650,
+ IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT = 0x20E0654,
+ IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT = 0x20E0658,
+ IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT = 0x20E065C,
+ IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT = 0x20E0660,
+ IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT = 0x20E0664,
+ IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT = 0x20E0668,
+ IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT = 0x20E066C,
+ IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT = 0x20E0670,
+ IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT = 0x20E0674,
+ IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT = 0x20E0678,
+ IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT = 0x20E067C,
+ IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT = 0x20E0680,
+ IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT = 0x20E0684,
+ IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT = 0x20E0688,
+ IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT = 0x20E068C,
+ IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT = 0x20E0690,
+ IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT = 0x20E069C,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0 = 0x20E06A0,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1 = 0x20E06A4,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2 = 0x20E06A8,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3 = 0x20E06AC,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4 = 0x20E06B0,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5 = 0x20E06B4,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6 = 0x20E06B8,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7 = 0x20E06BC,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8 = 0x20E06C0,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9 = 0x20E06C4,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11 = 0x20E06C8,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12 = 0x20E06CC,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13 = 0x20E06D0,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14 = 0x20E06D4,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15 = 0x20E06D8,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16 = 0x20E06DC,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17 = 0x20E06E0,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18 = 0x20E06E4,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19 = 0x20E06E8,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20 = 0x20E06EC,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21 = 0x20E06F0,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22 = 0x20E06F4,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23 = 0x20E06F8,
+ IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10 = 0x20E06FC,
+ IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT = 0x20E0700,
+ IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT = 0x20E0704,
+ IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT = 0x20E0708,
+ IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT = 0x20E070C,
+ IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT = 0x20E0710,
+ IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT = 0x20E0714,
+ IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT = 0x20E0718,
+ IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0 = 0x20E071C,
+ IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT = 0x20E0720,
+ IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT = 0x20E0724,
+ IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT = 0x20E0728,
+ IOMUXC_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0 = 0x20E072C,
+ IOMUXC_ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT = 0x20E0730,
+ IOMUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT = 0x20E0734,
+ IOMUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT = 0x20E0738,
+ IOMUXC_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0 = 0x20E073C,
+ IOMUXC_ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT = 0x20E0740,
+ IOMUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT = 0x20E0744,
+ IOMUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT = 0x20E0748,
+ IOMUXC_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0 = 0x20E074C,
+ IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT = 0x20E0750,
+ IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT = 0x20E0754,
+ IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT = 0x20E0758,
+ IOMUXC_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0 = 0x20E075C,
+ IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT = 0x20E0760,
+ IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT = 0x20E0764,
+ IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT = 0x20E0768,
+ IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT = 0x20E076C,
+ IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT = 0x20E0770,
+ IOMUXC_ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT = 0x20E0774,
+ IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT = 0x20E0778,
+ IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT = 0x20E077C,
+ IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT = 0x20E0780,
+ IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT = 0x20E0784,
+ IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT = 0x20E0788,
+ IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT = 0x20E078C,
+ IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT = 0x20E0790,
+ IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT = 0x20E0794,
+ IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT = 0x20E0798,
+ IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT = 0x20E079C,
+ IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT = 0x20E07A0,
+ IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT = 0x20E07A4,
+ IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT = 0x20E07A8,
+ IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT = 0x20E07AC,
+ IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT = 0x20E07B0,
+ IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT = 0x20E07B4,
+ IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT = 0x20E07B8,
+ IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT = 0x20E07BC,
+ IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT = 0x20E07C0,
+ IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT = 0x20E07C4,
+ IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5 = 0x20E07C8,
+ IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6 = 0x20E07CC,
+ IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7 = 0x20E07D0,
+ IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5 = 0x20E07D4,
+ IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6 = 0x20E07D8,
+ IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7 = 0x20E07DC,
+ IOMUXC_LCD1_BUSY_SELECT_INPUT = 0x20E07E0,
+ IOMUXC_LCD2_BUSY_SELECT_INPUT = 0x20E07E4,
+ IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT = 0x20E07E8,
+ IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT = 0x20E07EC,
+ IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT = 0x20E07F0,
+ IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 0x20E07F4,
+ IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 0x20E07F8,
+ IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 0x20E07FC,
+ IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 0x20E0800,
+ IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 0x20E0804,
+ IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 0x20E0808,
+ IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 0x20E080C,
+ IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 0x20E0810,
+ IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 0x20E0814,
+ IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 0x20E0818,
+ IOMUXC_SDMA_EVENTS_SELECT_INPUT_14 = 0x20E081C,
+ IOMUXC_SDMA_EVENTS_SELECT_INPUT_15 = 0x20E0820,
+ IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 0x20E0824,
+ IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT = 0x20E0828,
+ IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT = 0x20E082C,
+ IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT = 0x20E0830,
+ IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT = 0x20E0834,
+ IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT = 0x20E0838,
+ IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT = 0x20E083C,
+ IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT = 0x20E0840,
+ IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT = 0x20E0844,
+ IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT = 0x20E0848,
+ IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT = 0x20E084C,
+ IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT = 0x20E0850,
+ IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT = 0x20E0854,
+ IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT = 0x20E0858,
+ IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT = 0x20E085C,
+ IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT = 0x20E0860,
+ IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT = 0x20E0864,
+ IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT = 0x20E0868,
+ IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT = 0x20E086C,
+ IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT = 0x20E0870,
+ IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT = 0x20E0874,
+ IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT = 0x20E0878,
+ IOMUXC_SELECT_INPUT_UPPER_BOUND = IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT,
+} IMX_INPUT_SELECT;
+
+#define IOMUXC_GPR_BASE_ADDRESS 0x020E4000
+
+typedef struct{
+ UINT32 GPR0; // 0x00 IOMUXC_GPR0
+ UINT32 GPR1; // 0x04 IOMUXC_GPR1
+ UINT32 GPR2; // 0x08 IOMUXC_GPR2
+ UINT32 GPR3; // 0x0C IOMUXC_GPR3
+ UINT32 GPR4; // 0x10 IOMUXC_GPR4
+ UINT32 GPR5; // 0x14 IOMUXC_GPR5
+ UINT32 GPR6; // 0x18 IOMUXC_GPR6
+ UINT32 GPR7; // 0x1C IOMUXC_GPR7
+ UINT32 GPR8; // 0x20 IOMUXC_GPR8
+ UINT32 GPR9; // 0x24 IOMUXC_GPR9
+ UINT32 GPR10; // 0x28 IOMUXC_GPR10
+ UINT32 GPR11; // 0x2c IOMUXC_GPR11
+ UINT32 GPR12; // 0x30 IOMUXC_GPR12
+ UINT32 GPR13; // 0x34 IOMUXC_GPR13
+} IMX_IOMUXC_GPR_REGISTERS;
+
+typedef enum {
+ IMX_IOMUXC_GPR1_USB_OTG_ID_SEL_ENET_RX_ER,
+ IMX_IOMUXC_GPR1_USB_OTG_ID_SEL_GPIO_1,
+} IMX_IOMUXC_GPR1_USB_OTG_ID_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ACT_CS0 : 1; // 0
+ UINT32 ADDRS0_10 : 2; // 1-2
+ UINT32 ACT_CS1 : 1; // 3
+ UINT32 ADDRS1_10 : 2; // 4-5
+ UINT32 ACT_CS2 : 1; // 6
+ UINT32 ADDRS2_10 : 2; // 7-8
+ UINT32 ACT_CS3 : 1; // 9
+ UINT32 ADDRS3_10 : 2; // 10-11 Active Chip Select and Address Space
+ UINT32 GINT : 1; // 12 Global interrupt "0" bit (connected to ARM IRQ#0 and GPC)
+ UINT32 USB_OTG_ID_SEL : 1; // 13 ''usb_otg_id' pin iomux select control.
+ UINT32 SYS_INT : 1; // 14 PCIe_CTL
+ UINT32 USB_EXP_MODE : 1; // 15 USB Exposure mode
+ UINT32 REF_SSP_EN : 1; // 16 PCIe_PHY - Reference Clock Enable for SS function.
+ UINT32 PU_VPU_MUX : 1; // 17 IPU-1/IPU-2 to VPU signals control.
+ UINT32 TEST_POWERDOWN : 1; // 18 PCIe_PHY - All Circuits Power-Down Control Function.
+ UINT32 MIPI_IPU1_MUX : 1; // 19 MIPI sensor to IPU-1 mux control.
+ UINT32 MIPI_IPU2_MUX : 1; // 20 MIPI sensor to IPU-2 mux control
+ UINT32 ENET_CLK_SEL : 1; // 21 ENET TX reference clock
+ UINT32 EXC_MON : 1; // 22 Exclusive monitor response select of illegal command
+ UINT32 reserved1 : 1; // 23
+ UINT32 MIPI_DPI_OFF : 1; // 24 MIPI DPI shutdown request
+ UINT32 MIPI_COLOR_SW : 1; // 25 MIPI color switch control
+ UINT32 APP_REQ_ENTR_L1 : 1; // 26 PCIe_CTL - Application Request to Enter L1
+ UINT32 APP_READY_ENTR_L23 : 1; // 27 PCIe_CTL - Application Ready to Enter L23
+ UINT32 APP_REQ_EXIT_L1 : 1; // 28 PCIe_CTL - Application Request to Exit L1
+ UINT32 reserved2 : 1; // 29
+ UINT32 APP_CLK_REQ_N : 1; // 30 PCIe_CTL (CLK LOGIC CONTROLLER GLUE) - Indicates that application logic is ready to have reference clock removed.
+ UINT32 CFG_L1_CLK_REMOVAL_EN : 1; // 31 PCIe_CTL (CLK LOGIC CONTROLLER GLUE) - Enable the reference clock removal in L1 state.
+ // MSB
+ };
+} IMX_IOMUXC_GPR1_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 PCS_TX_DEEMPH_GEN1 : 6; // 0-5 PCIe_PHY - This static value sets the launch amplitude of the transmitter when pipe0_tx_swing is set to 1'b0 (default state).
+ UINT32 PCS_TX_DEEMPH_GEN2_3P5DB : 6;// 6-11 PCIe_PHY - This static value sets the Tx driver SWING_FULL value.
+ UINT32 PCS_TX_DEEMPH_GEN2_6DB : 6; // 12-17 PCIe_PHY - This static value sets the Tx driver de-emphasis value in the case where pipe0_tx_deemph is set to 1'b0 and the PHY is running at the Gen2 (6db) rate.
+ UINT32 PCS_TX_SWING_FULL : 7; // 18-24 PCIe_PHY - This static value sets the Tx driver de-emphasis value in the case where pipe0_tx_deemph is set to 1'b1 (the default setting) and the PHY is running at the Gen2 (3p5db) rate.
+ UINT32 PCS_TX_SWING_LOW : 7; // 25-31 PCIe_PHY - This static value sets the Tx driver de-emphasis value in the case where pipe0_tx_deemph is set to 1'b1 (the default setting) and the PHY is running at the Gen1 rate.
+ // MSB
+ };
+} IMX_IOMUXC_GPR8_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 reserved0 : 2; // 0-1
+ UINT32 uSDHC_DBG_MUX : 2; // 2-3 uSDHC debug bus IO mux control
+ UINT32 LOS_LEVEL : 5; // 4-8 PCIe_PHY - Loss-of-Signal Detector Sensitivity Level Control Function: Sets the sensitivity level for the Loss - of - Signal detector.This signal must be set to 0x9
+ UINT32 APPS_PM_XMT_PME : 1; // 9 PCIe_CTL - Wake Up. Used by application logic to wake up the PMC state machine from a D1, D2 or D3 power state.Upon wake - up, the core sends a PM_PME Message
+ UINT32 APP_LTSSM_ENABLE : 1; // 10 PCIe_CTL Driven low by the application after reset to hold the LTSSM in the Detect state until the application is ready.When the application has finished initializing the core configuration registers, it asserts app_ltssm_enable to allow the LTSSM to continue Link establishment.
+ UINT32 APP_INIT_RST : 1; // 11 PCIe_PHY - PCIe_CTL - Request from the application to send a Hot Reset to the downstream device.
+ UINT32 DEVICE_TYPE : 4; // 12-15 PCIe_CTL - Device/Port Type. 0000 PCIE_EP - EP Mode 0010 PCIE_RC - RC Mode
+ UINT32 APPS_PM_XMT_TURNOFF : 1; // 16 PCIe_CTL - Request from the application to generate a PM_Turn_Off Message.
+ UINT32 DIA_STATUS_BUS_SELECT : 4; // 17-20 PCIe_CTL - used for debug to select what part of diag_status_bus will be reflected on the 32 bits of the iomux
+ UINT32 PCIe_CTL_7 : 3; // 21-23 PCIe control of diagnostic bus select
+ UINT32 ARMP_APB_CLK_EN : 1; // 24 ARM platform APB clock enable
+ UINT32 ARMP_ATB_CLK_EN : 1; // 25 ARM platform ATB clock enable
+ UINT32 ARMP_AHB_CLK_EN : 1; // 26 ARM platform AHB clock enable
+ UINT32 ARMP_IPG_CLK_EN : 1; // 27 ARM platform IPG clock enable
+ UINT32 reserved1 : 4; // 28-31
+ // MSB
+ };
+} IMX_IOMUXC_GPR12_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 reserved1 : 1; // 0
+ UINT32 reserved2 : 1; // 1
+ UINT32 MC_ENV : 1; // 2 Monotonic Counter Enable and Valid
+ UINT32 reserved3 : 1; // 3
+ UINT32 reserved4 : 1; // 4
+ UINT32 DP_EN : 1; // 5 Dumb PMIC Enabled
+ UINT32 TOP : 1; // 6 Turn off System Power
+ UINT32 PWR_GLITCH_EN : 1; // 7 Power Glitch Detection Enable
+ UINT32 reserved5 : 1; // 8
+ UINT32 reserved6 : 1; // 9
+ UINT32 reserved7 : 5; // 10-14
+ UINT32 reserved8 : 1; // 15
+ UINT32 BTN_PRESS_TIME : 2; // 16-17 Button press time out values for PMIC Logic.
+ UINT32 DEBOUNCE : 2; // 18-19 debounce time for the BTN input signal
+ UINT32 ON_TIME : 2; // 20-21 Time after BTN is asserted before pmic_en_b is asserted
+ UINT32 PK_EN : 1; // 22 PMIC On Request Enable
+ UINT32 PK_OVERRIDE : 1; // 23 PMIC On Request Override
+ UINT32 reserved9 : 8; // 24-31
+ // MSB
+ };
+} IMX_SNVS_LPCR_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 MINOR_REV : 8; // 0-7 SNVS block minor version number
+ UINT32 MAJOR_REV : 8; // 8-15 SNVS block major version number
+ UINT32 IP_ID : 16; // 16-31 SNVS block ID (IMX_SNVS_IP_ID)
+ // MSB
+ };
+} IMX_SNVS_HPVIDR1_REG;
+
+typedef struct {
+ UINT32 HPLR; // 0x000 SNVS_HP Lock Register (SNVS_HPLR)
+ UINT32 HPCOMR; // 0x004 SNVS_HP Command Register (SNVS_HPCOMR)
+ UINT32 HPCR; // 0x008 SNVS_HP Control Register (SNVS_HPCR)
+ UINT32 reserved1[2];
+ UINT32 HPSR; // 0x014 SNVS_HP Status Register (SNVS_HPSR)
+ UINT32 reserved2[3];
+ UINT32 HPRTCMR; // 0x024 SNVS_HP Real Time Counter MSB Register (SNVS_HPRTCMR
+ UINT32 HPRTCLR; // 0x028 SNVS_HP Real Time Counter LSB Register (SNVS_HPRTCLR)
+ UINT32 HPTAMR; // 0x02C SNVS_HP Time Alarm MSB Register (SNVS_HPTAMR)
+ UINT32 HPTALR; // 0x030 SNVS_HP Time Alarm LSB Register (SNVS_HPTALR)
+ UINT32 LPLR; // 0x034 SNVS_LP Lock Register (SNVS_LPLR)
+ UINT32 LPCR; // 0x038 SNVS_LP Control Register (SNVS_LPCR)
+ UINT32 reserved3[4];
+ UINT32 LPSR; // 0x04C SNVS_LP Status Register (SNVS_LPSR)
+ UINT32 reserved4[3];
+ UINT32 LPSMCMR; // 0x05C SNVS_LP Secure Monotonic Counter MSB Register (SNVS_LPSMCMR)
+ UINT32 LPSMCLR; // 0x060 SNVS_LP Secure Monotonic Counter LSB Register (SNVS_LPSMCLR)
+ UINT32 reserved5[1];
+ UINT32 LPGPR; // 0x068 SNVS_LP General Purpose Register (SNVS_LPGPR)
+ UINT32 reserved6[739];
+ UINT32 HPVIDR1; // 0xBF8 SNVS_HP Version ID Register 1 (SNVS_HPVIDR1)
+ UINT32 HPVIDR2; // 0xBFC SNVS_HP Version ID Register 2 (SNVS_HPVIDR2)
+} IMX_SNVS_REGISTERS;
+
+//
+// System Reset Controller (SRC)
+//
+
+#define IMX_SRC_BASE 0x020D8000
+#define IMX_SRC_LENGTH 0x4000
+
+//
+// SCR Register Definition
+//
+
+// SRC_SCR_REG.warm_rst_bypass_count
+typedef enum {
+ IMX_SCR_WARM_RST_BYPASS_COUNT_DISABLED,
+ IMX_SCR_WARM_RST_BYPASS_COUNT_16,
+ IMX_SCR_WARM_RST_BYPASS_COUNT_32,
+ IMX_SCR_WARM_RST_BYPASS_COUNT_64,
+} IMX_SCR_WARM_RST_BYPASS_COUNT;
+
+// SRC_SCR_REG.mask_wdog_rst
+typedef enum {
+ IMX_SRC_MASK_WDOG_RST_B_MASKED = 0x5,
+ IMX_SRC_MASK_WDOG_RST_B_NOT_MASKED = 0xA,
+} IMX_SRC_MASK_WDOG_RST;
+
+// SRC_SCR_REG.mask_tempsense_reset
+typedef enum {
+ IMX_SRC_MASK_TEMPSENSE_RESET_NOT_MASKED = 0x2,
+ IMX_SRC_MASK_TEMPSENSE_RESET_MASKED = 0x5,
+} IMX_SRC_MASK_TEMPSENSE_RESET;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 warm_reset_enable : 1; // 0 WARM reset enable bit
+ UINT32 sw_gpu_rst : 1; // 1 Software reset for GPU
+ UINT32 reserved1 : 1; // 2
+ UINT32 m4c_rst : 1; // 3 Self-clearing SW reset for M4 core
+ UINT32 m4c_non_sclr_rst : 1; // 4 Non-self-clearing SW reset for M4 core
+ UINT32 warm_rst_bypass_count : 2; // 5-6 Defines the XTALI cycles to count before bypassing the MMDC acknowledge for WARM reset. (IMX_SCR_WARM_RST_BYPASS_COUNT)
+ UINT32 mask_wdog_rst : 4; // 7-10 Mask wdog_rst_b source (IMX_SRC_MASK_WDOG_RST)
+ UINT32 eim_rst : 1; // 11 EIM reset is needed in order to reconfigure the eim chip select.
+ UINT32 m4p_rst : 1; // 12 Self-clearing SW reset for M4 platform
+ UINT32 core0_rst : 1; // 13 Software reset for core0 only
+ UINT32 reserved2 : 3; // 14-16
+ UINT32 core0_dbg_rst : 1; // 17 Software reset for core0 debug only.
+ UINT32 mask_tempsense_reset : 3; // 18-20 Mask tempsense_reset source (IMX_SRC_MASK_TEMPSENSE_RESET)
+ UINT32 cores_dbg_rst : 1; // 21 Software reset for debug of arm platform only
+ UINT32 m4_enable : 1; // 22 Enable M4 core
+ UINT32 wdog3_rst_optn_m4 : 1; // 23 wdog3_rst_b option for M4. This bit is only effective when wdog3_rst_option is set to 1.
+ UINT32 wdog3_rst_optn : 1; // 24 Wdog3_rst_b option
+ UINT32 dbg_rst_msk_pg : 1; // 25 Do not assert debug resets after power gating event of core
+ UINT32 mix_rst_strch : 2; // 26-27 SoC mix (Audio, ENET, uSDHC, EIM, QSPI, OCRAM, MMDC, etc) power up reset stretch mix reset width = (mix_rst_strtch +1)* 88 ipg_clk cycles
+ UINT32 mask_wdog3_rst : 4; // 28-31 Mask wdog3_rst_b source (IMX_SRC_MASK_WDOG_RST)
+ // MSB
+ };
+} IMX_SRC_SCR_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 BOOT_CFG1 : 8; // 0-7
+ UINT32 BOOT_CFG2 : 8; // 8-15
+ UINT32 BOOT_CFG3 : 8; // 16-23
+ UINT32 BOOT_CFG4 : 8; // 24-31
+ // MSB
+ };
+} IMX_SRC_SBMR1_REG;
+
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 SEC_COFNIG : 2; // 0-1
+ UINT32 reserved1 : 1; // 2
+ UINT32 DIR_BT_DIS : 1; // 3
+ UINT32 BT_FUSE_SEL : 1; // 4
+ UINT32 reserved2 : 19; // 5-23
+ UINT32 BMOD : 2; // 24-25
+ UINT32 reserved3 : 6; // 26-31
+ // MSB
+ };
+} IMX_SRC_SBMR2_REG;
+
+typedef struct {
+ UINT32 SCR; // 0x00 SRC Control Register (SRC_SCR)
+ UINT32 SBMR1; // 0x04 SRC Boot Mode Register 1 (SRC_SBMR1)
+ UINT32 SRSR; // 0x08 SRC Reset Status Register (SRC_SRSR)
+ UINT32 reserved1[2];
+ UINT32 SISR; // 0x14 SRC Interrupt Status Register (SRC_SISR)
+ UINT32 SIMR; // 0x18 SRC Interrupt Mask Register (SRC_SIMR)
+ UINT32 SBMR2; // 0x1C SRC Boot Mode Register 2 (SRC_SBMR2)
+ UINT32 GPR1; // 0x20 SRC General Purpose Register 1 (SRC_GPR1)
+ UINT32 GPR2; // 0x24 SRC General Purpose Register 2 (SRC_GPR2)
+ UINT32 GPR3; // 0x28 SRC General Purpose Register 3 (SRC_GPR3)
+ UINT32 GPR4; // 0x2C SRC General Purpose Register 4 (SRC_GPR4)
+ UINT32 GPR5; // 0x30 SRC General Purpose Register 4 (SRC_GPR5)
+ UINT32 GPR6; // 0x34 SRC General Purpose Register 4 (SRC_GPR6)
+ UINT32 GPR7; // 0x38 SRC General Purpose Register 4 (SRC_GPR7)
+ UINT32 GPR8; // 0x3C SRC General Purpose Register 4 (SRC_GPR8)
+ UINT32 GPR9; // 0x40 SRC General Purpose Register 4 (SRC_GPR9)
+ UINT32 GPR10; // 0x44 SRC General Purpose Register 4 (SRC_GPR10)
+} IMX_SRC_REGISTERS;
+
+
+//
+// Watchdog (WDOG)
+//
+
+#define IMX_WDOG1_BASE 0x020BC000
+#define IMX_WDOG2_BASE 0x020C0000
+#define IMX_WDOG3_BASE 0x02288000 // SX RM.p4734
+
+#define IMX_WDOG_LENGTH 0x4000
+
+#define IMX_WDOG_WSR_FEED1 0x5555
+#define IMX_WDOG_WSR_FEED2 0xAAAA
+
+typedef union {
+ UINT16 AsUint16;
+ struct {
+ // LSB
+ UINT16 WDZST : 1; // 0 Watchdog Low Power
+ UINT16 WDBG : 1; // 1 Watchdog DEBUG Enable
+ UINT16 WDE : 1; // 2 Watchdog Enable
+ UINT16 WDT : 1; // 3 WDOG_B Time-out assertion.
+ UINT16 SRS : 1; // 4 Software Reset Signal
+ UINT16 WDA : 1; // 5 WDOG_B assertion
+ UINT16 reserved1 : 1; // 6
+ UINT16 WDW : 1; // 7 Watchdog Disable for Wait
+ UINT16 WT : 8; // 8-15 Watchdog Time-out Field
+ // MSB
+ };
+} IMX_WDOG_WCR_REG;
+
+typedef struct {
+ UINT16 WCR; // 0x0 Watchdog Control Register (WDOG1_WCR)
+ UINT16 WSR; // 0x2 Watchdog Service Register (WDOG1_WSR)
+ UINT16 WRSR; // 0x4 Watchdog Reset Status Register (WDOG1_WRSR)
+ UINT16 WICR; // 0x6 Watchdog Interrupt Control Register (WDOG1_WICR)
+ UINT16 WMCR; // 0x8 Watchdog Miscellaneous Control Register (WDOG1_WMCR)
+} IMX_WDOG_REGISTERS;
+
+//
+// Clock Control Module (CCM)
+//
+
+#define IMX6SX_CCM_CLOCK_OFF 0
+#define IMX6SX_RUN_ONLY 1
+#define IMX6SX_RUN_AND_WAIT 3
+
+#define IMX_CCM_BASE 0x020C4000
+#define IMX_CCM_LENGTH 0x4000
+#define IMX_CCM_ANALOG_BASE 0x020C8000
+#define IMX_CCM_ANALOG_LENGTH 0x1000
+
+#define IMX_REF_CLK_24M_FREQ 24000000
+
+typedef enum {
+ IMX_CCM_PLL3_SW_CLK_SEL_PLL3_MAIN_CLK,
+ IMX_CCM_PLL3_SW_CLK_SEL_PLL3_BYPASS_CLK,
+} IMX_CCM_PLL3_SW_CLK_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 pll3_sw_clk_sel : 1; // 0 Selects source to generate pll3_sw_clk (IMX_CCM_PLL3_SW_CLK_SEL)
+ UINT32 reserved1 : 1; // 1
+ UINT32 pll1_sw_clk_sel : 1; // 2 Selects source to generate pll1_sw_clk.
+ UINT32 reserved2 : 5; // 3-7
+ UINT32 step_sel : 1; // 8 Selects the option to be chosen for the step frequency
+ UINT32 reserved3 : 23; // 9-31
+ // MSB
+ };
+} IMX_CCM_CCSR_REG; // SX RM.p812
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 arm_podf : 3; // 0-3 Divider for ARM clock root
+ UINT32 reserved : 29; // 3-31
+ // MSB
+ };
+} IMX_CCM_CACRR_REG;
+
+// CBCMR.gpu_core_sel
+typedef enum {
+ IMX_CCM_GPU_CLK_SEL_PLL3_PFD1,
+ IMX_CCM_GPU_CLK_SEL_PLL3_PFD0,
+ IMX_CCM_GPU_CLK_SEL_PLL2,
+ IMX_CCM_GPU_CLK_SEL_PLL2_PFD2
+} IMX_CCM_GPU_CLK_SEL;
+
+// CBCMR.gpu_axi_sel
+typedef enum {
+ IMX_CCM_GPU_AXI_SEL_PLL2_PFD2,
+ IMX_CCM_GPU_AXI_SEL_PLL3_PFD0,
+ IMX_CCM_GPU_AXI_SEL_PLL3_PFD1,
+ IMX_CCM_GPU_AXI_SEL_PLL2
+} IMX_CCM_GPU_AXI_SEL;
+
+// CBCMR.pcie_axi_clock_sel
+typedef enum {
+ IMX_CCM_PCIE_AXI_CLOCK_SEL_AXI,
+ IMX_CCM_PCIE_AXI_CLOCK_SEL_AHB,
+} IMX_CCM_PCIE_AXI_CLOCK_SEL;
+
+// CBCMR.periph_clk2_sel
+typedef enum {
+ IMX_CCM_PERIPH_CLK2_SEL_PLL3_SW_CLK,
+ IMX_CCM_PERIPH_CLK2_SEL_OSC_CLK,
+ IMX_CCM_PERIPH_CLK2_SEL_PLL2_BYPASS_CLK
+} IMX_CCM_PERIPH_CLK2_SEL;
+
+// CBCMR.pre_periph_clk_sel
+typedef enum {
+ IMX_CCM_PRE_PERIPH_CLK_SEL_PLL2,
+ IMX_CCM_PRE_PERIPH_CLK_SEL_PLL2_PFD2,
+ IMX_CCM_PRE_PERIPH_CLK_SEL_PLL2_PFD0,
+ IMX_CCM_PRE_PERIPH_CLK_SEL_PLL2_PFD2_DIV2,
+} IMX_CCM_PRE_PERIPH_CLK_SEL;
+
+// CBCMR.periph2_clk2_sel
+typedef enum {
+ IMX_CCM_PERIPH2_CLK2_SEL_PLL3_SW_CLK,
+ IMX_CCM_PERIPH2_CLK2_SEL_OSC
+} IMX_CCM_PERIPH2_CLK2_SEL;
+
+// CBCMR.pre_periph2_clk_sel
+typedef enum {
+ IMX_CCM_PRE_PERIPH2_CLK_SEL_PLL2,
+ IMX_CCM_PRE_PERIPH2_CLK_SEL_PLL2_PFD2,
+ IMX_CCM_PRE_PERIPH2_CLK_SEL_PLL2_PFD0,
+ IMX_CCM_PRE_PERIPH2_CLK_SEL_PLL4
+} IMX_CCM_PRE_PERIPH2_CLK_SEL;
+
+// CBCMR.podf (divider for lcdif1_podf, gpu_axi_podf, gpu_core_podf)
+typedef enum {
+ IMX_CCM_PODF_DIV1,
+ IMX_CCM_PODF_DIV2,
+ IMX_CCM_PODF_DIV3,
+ IMX_CCM_PODF_DIV4,
+ IMX_CCM_PODF_DIV5,
+ IMX_CCM_PODF_DIV6,
+ IMX_CCM_PODF_DIV7,
+ IMX_CCM_PODF_DIV8
+} IMX_CCM_PODF;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 reserved1 : 4; // 0-3
+ UINT32 gpu_core_sel : 2; // 4-5 Selector for gpu_core clock multiplexer (IMX_CCM_GPU_CLK_SEL)
+ UINT32 reserved2 : 2; // 6-7
+ UINT32 gpu_axi_sel : 2; // 8-9 Selector for gpu_axi clock multiplexer (IMX_CCM_GPU_AXI_SEL)
+ UINT32 pcie_axi_clock_sel : 1; // 10 Selector for pcie_axi_clock multiplexier (IMX_CCM_PCIE_AXI_CLOCK_SEL)
+ UINT32 reserved3 : 1; // 11
+ UINT32 periph_clk2_sel : 2; // 12-13 Selector for peripheral clk2 clock multiplexer (IMX_CCM_PERIPH_CLK2_SEL)
+ UINT32 reserved4 : 4; // 14-17
+ UINT32 pre_periph_clk_sel : 2; // 18-19 Selector for pre_periph clock multiplexer (IMX_CCM_PRE_PERIPH_CLK_SEL)
+ UINT32 periph2_clk2_sel : 1; // 20 Selector for periph2_clk2 clock multiplexer (IMX_CCM_PERIPH2_CLK2_SEL)
+ UINT32 pre_periph2_clk_sel : 2; // 21-22 Selector for pre_periph2 clock multiplexer (IMX_CCM_PRE_PERIPH2_CLK_SEL)
+ UINT32 lcdif1_podf : 3; // 23-25 Post-divider for lcdif1 clock (IMX_CCM_PODF)
+ UINT32 gpu_axi_podf : 3; // 26-28 Divider for gpu_axi_podf (IMX_CCM_PODF)
+ UINT32 gpu_core_podf : 3; // 29-31 Post divider for gpu_core clock (IMX_CCM_PODF)
+ // MSB
+ };
+} IMX_CCM_CBCMR_REG; // SX RM.p816
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ssi1_clk_podf : 6; // 0-5 Divider for ssi1 clock podf
+ UINT32 ssi1_clk_pred : 3; // 6-8 Divider for ssi1 clock pred
+ UINT32 esai_clk_pred : 3; // 9-11 Divider for esai clock pred
+ UINT32 reserved1 : 4; // 12-15 Reserved
+ UINT32 ssi3_clk_podf : 6; // 16-21 Divider for ssi3 clock podf
+ UINT32 ssi3_clk_pred : 3; // 22-24 Divider for ssi3 clock pred
+ UINT32 esai_clk_podf : 3; // 25-27 Divider for esai clock podf
+ UINT32 reserved2 : 4; // 28-31 Reserved
+ // MSB
+ };
+} IMX_CCM_CS1CDR_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ssi2_clk_podf : 6; // 0-5 Divider for ssi2 clock podf
+ UINT32 ssi2_clk_pred : 3; // 6-8 Divider for ssi2 clock pred
+ UINT32 ldb_di0_clk_sel : 3; // 9-11 Selector for ldb_di0 clock multiplexer
+ UINT32 ldb_di1_clk_sel : 3; // 12-14 Selector for ldb_di1 clock multiplexer
+ UINT32 qspi2_clk_sel : 3; // 15-17 Selector for QSPI2 clock multiplexer
+ UINT32 qspi2_clk_pred : 3; // 18-20 Divider for QSPI1 clock pred divider
+ UINT32 qspi2_clk_podf : 6; // 21-26 Divider for QSPI2 clock divider
+ UINT32 reserved : 5; // 27-31
+ // MSB
+ };
+} IMX_CCM_CS2CDR_REG; // SX RM.p827
+
+typedef enum {
+ IMX_CCM_CCGR_OFF = 0x0, // Clock is off during all modes. Stop enter hardware handshake is disabled.
+ IMX_CCM_CCGR_ON_RUN = 0x1, // Clock is on in run mode, but off in WAIT and STOP modes
+ IMX_CCM_CCGR_ON = 0x3, // Clock is on during all modes, except STOP mode.
+} IMX_CCM_CCGR;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 aips_tz1_clk_enable : 2; // 0-1 aips_tz1 clocks (aips_tz1_clk_enable)
+ UINT32 aips_tz2_clk_enable : 2; // 2-3 aips_tz2 clocks (aips_tz2_clk_enable)
+ UINT32 apbhdma_hclk_enable : 2; // 4-5 apbhdma hclk clock (apbhdma_hclk_enable)
+ UINT32 asrc_clk_enable : 2; // 6-7 asrc clock (asrc_clk_enable)
+ UINT32 caam_secure_mem_clk_enable : 2; // 8-9 caam_secure_mem clock (caam_secure_mem_clk_enable)
+ UINT32 caam_wrapper_aclk_enable : 2; // 10-11 caam_wrapper_aclk clock (caam_wrapper_aclk_enable)
+ UINT32 caam_wrapper_ipg_enable : 2; // 12-13 caam_wrapper_ipg clock (caam_wrapper_ipg_enable)
+ UINT32 can1_clk_enable : 2; // 14-15 can1 clock (can1_clk_enable)
+ UINT32 can1_serial_clk_enable : 2; // 16-17 can1_serial clock (can1_serial_clk_enable)
+ UINT32 can2_clk_enable : 2; // 18-19 can2 clock (can2_clk_enable)
+ UINT32 can2_serial_clk_enable : 2; // 20-21 can2_serial clock (can2_serial_clk_enable)
+ UINT32 arm_dbg_clk_enable : 2; // 22-23 CPU debug clocks (arm_dbg_clk_enable)
+ UINT32 dcic1_clk_enable : 2; // 24-25 dcic 1 clocks (dcic1_clk_enable)
+ UINT32 dcic2_clk_enable : 2; // 26-27 dcic2 clocks (dcic2_clk_enable)
+ UINT32 reserved : 2; // 28-29
+ UINT32 aips_tz3_clk_enable : 2; // 30-31 aips_tz3 clocks (aips_tz3_clk_enable)
+ // MSB
+ };
+} IMX_CCM_CCGR0_REG; // SX RM.p851
+
+// CHSCCDR.m4_clk_sel
+typedef enum {
+ IMX_CHSCCDR_M4_CLK_SEL_DIVIDED_PRE_MUXED_M4_CLOCK,
+ IMX_CHSCCDR_M4_CLK_SEL_IPP_DI0_CLK,
+ IMX_CHSCCDR_M4_CLK_SEL_IPP_DI1_CLK,
+ IMX_CHSCCDR_M4_CLK_SEL_LDB_DI0_CLK,
+ IMX_CHSCCDR_M4_CLK_SEL_LDB_DI1_CLK
+} IMX_CHSCCDR_M4_CLK_SEL;
+
+// CHSCCDR.m4_pre_clk_sel
+typedef enum {
+ IMX_M4_PRE_CLK_SEL_PLL2,
+ IMX_M4_PRE_CLK_SEL_PLL3_SW_CLK,
+ IMX_M4_PRE_CLK_SEL_OSC_CLK_24M,
+ IMX_M4_PRE_CLK_SEL_PLL2_PFD0,
+ IMX_M4_PRE_CLK_SEL_PLL2_PFD2,
+ IMX_M4_PRE_CLK_SEL_PLL3_PFD3
+} IMX_M4_PRE_CLK_SEL;
+
+// CHSCCDR.enet_clk_sel
+typedef enum {
+ IMX_ENET_CLK_SEL_DIVIDED_PREMUXED_ENET_CLK,
+ IMX_ENET_CLK_SEL_IPP_DI0_CLK,
+ IMX_ENET_CLK_SEL_IPP_DI1_CLK,
+ IMX_ENET_CLK_SEL_LDB_DI0_CLK,
+ IMX_ENET_CLK_SEL_LDB_DI1_CLK
+} IMX_ENET_CLK_SEL;
+
+// CHSCCDR.enet_pre_clk_sel
+typedef enum {
+ IMX_ENET_PRE_CLK_SEL_PLL2,
+ IMX_ENET_PRE_CLK_SEL_PLL3_SW_CLK,
+ IMX_ENET_PRE_CLK_SEL_PLL5,
+ IMX_ENET_PRE_CLK_SEL_PLL2_PFD0,
+ IMX_ENET_PRE_CLK_SEL_PLL2_PFD2,
+ IMX_ENET_PRE_CLK_SEL_PLL3_PFD2
+} IMX_ENET_PRE_CLK_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 m4_clk_sel : 3; // 0-2 Selector for M4 root clock multiplexer (IMX_CHSCCDR_M4_CLK_SEL)
+ UINT32 m4_podf : 3; // 3-5 Divider for M4 clock divider
+ UINT32 m4_pre_clk_sel : 3; // 6-8 Selector for M4 root clock pre-multiplexer (IMX_M4_PRE_CLK_SEL)
+ UINT32 enet_clk_sel : 3; // 9-11 Selector for ENET root clock multiplexer (IMX_ENET_CLK_SEL)
+ UINT32 enet_podf : 3; // 12-14 Divider for ENET clock divider
+ UINT32 enet_pre_clk_sel : 3; // 15-17 Selector for ENET root clock pre-multiplexer (IMX_ENET_PRE_CLK_SEL)
+ UINT32 reserved : 14; // 18-31
+ // MSB
+ };
+} IMX_CCM_CHSCCDR_REG; // SX RM.p830
+
+//
+// NOTE: OPENVG clock cannot be gated without gating GPU2D clock as well.
+// Configure both CG bits (CCM_ANALOG_CCGR1[CG12] and
+// CCM_ANALOG_CCGR3[CG15]) to gate OPENVG.
+//
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ecspi1_clk_enable : 2; // 0-1 ecspi1 clocks (ecspi1_clk_enable)
+ UINT32 ecspi2_clk_enable : 2; // 2-3 ecspi2 clocks (ecspi2_clk_enable)
+ UINT32 ecspi3_clk_enable : 2; // 4-5 ecspi3 clocks (ecspi3_clk_enable)
+ UINT32 ecspi4_clk_enable : 2; // 6-7 ecspi4 clocks (ecspi4_clk_enable)
+ UINT32 ecspi5_clk_enable : 2; // 8-9 ecspi5 clocks (ecspi5_clk_enable)
+ UINT32 reserved1 : 2; // 10-11
+ UINT32 epit1_clk_enable : 2; // 12-13 epit1 clocks (epit1_clk_enable)
+ UINT32 epit2_clk_enable : 2; // 14-15 epit2 clocks (epit2_clk_enable)
+ UINT32 esai_clk_enable : 2; // 16-17 esai clocks (esai_clk_enable)
+ UINT32 wakeup_clk_enable : 2; // 18-19 wakeup clock (wakeup_clk_enable)
+ UINT32 gpt_clk_enable : 2; // 20-21 gpt bus clock (gpt_clk_enable)
+ UINT32 gpt_serial_clk_enable : 2; // 22-23 gpt serial clock (gpt_serial_clk_enable)
+ UINT32 reserved2 : 2; // 24-25
+ UINT32 gpu_clk_enable : 2; // 26-27 gpu clock (gpu_clk_enable)
+ UINT32 ocram_s_clk_enable : 2; // 28-29 ocram_s clock (ocram_s_clk_enable)
+ UINT32 canfd_clk_enable : 2; // 30-31 canfd clock (canfd_clk_enable)
+ // MSB
+ };
+} IMX_CCM_CCGR1_REG;
+
+// CBCDR.ocram_clk_sel
+typedef enum {
+ IMX_CCM_OCRAM_CLK_SEL_PERIPH_CLK,
+ IMX_CCM_OCRAM_CLK_SEL_AXI_ALT_CLK
+} IMX_CCM_OCRAM_CLK_SEL;
+
+// CBCDR.ocram_alt_clk_sel
+typedef enum {
+ IMX_CCM_OCRAM_ALT_CLK_SEL_PLL2_PFD2,
+ IMX_CCM_OCRAM_ALT_CLK_SEL_PLL3_PFD1
+} IMX_CCM_OCRAM_ALT_CLK_SEL;
+
+// CBCDR.periph_clk_sel
+typedef enum {
+ IMX_CCM_PERIPH_CLK_SEL_PRE_PERIPH_CLK_SEL,
+ IMX_CCM_PERIPH_CLK_SEL_PERIPH_CLK2_CLK_DIVIDED
+} IMX_CCM_PERIPH_CLK_SEL;
+
+// CBCDR.periph2_clk_sel
+typedef enum {
+ IMX_CCM_PERIPH2_CLK_SEL_PRE_PERIPH2_CLK,
+ IMX_CCM_PERIPH2_CLK_SEL_PERIPH2_CLK2_CLK_DIVIDED
+} IMX_CCM_PERIPH2_CLK_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 periph2_clk2_podf : 3; // 0-2 Divider for periph2_clk2 podf
+ UINT32 fabric_mmdc_podf : 3; // 3-5 Post divider for fabric / mmdc clock
+ UINT32 ocram_clk_sel : 1; // 6 OCRAM clock source select (IMX_CCM_OCRAM_CLK_SEL)
+ UINT32 ocram_alt_clk_sel : 1; // 7 OCRAM alternative clock select (IMX_CCM_OCRAM_ALT_CLK_SEL)
+ UINT32 ipg_podf : 2; // 8-9 Divider for ipg podf
+ UINT32 ahb_podf : 3; // 10-12 Divider for AHB PODF
+ UINT32 reserved1 : 3; // 13-15
+ UINT32 ocram_podf : 3; // 16-18 Post divider for ocram clock
+ UINT32 reserved2 : 6; // 19-24
+ UINT32 periph_clk_sel : 1; // 25 Selector for peripheral main clock (IMX_CCM_PERIPH_CLK_SEL)
+ UINT32 periph2_clk_sel : 1; // 26 Selector for peripheral2 main clock (source of mmdc_clk_root ) (IMX_CCM_PERIPH2_CLK_SEL)
+ UINT32 periph_clk2_podf : 3; // 27-29 Divider for periph_clk2_podf
+ UINT32 reserved3 : 2; // 30-31
+ // MSB
+ };
+} IMX_CCM_CBCDR_REG; // SX RM.p813
+
+// CCOSR.CLKO1_SEL
+typedef enum {
+ IMX_CCM_CLKO1_SEL_VID_CLK_ROOT = 4,
+ IMX_CCM_CLKO1_SEL_OCRAM_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_QSPI2_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_M4_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_ENET_AXI_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_LCDIF2_PIX_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_LCDIF1_PIX_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_AHB_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_IPG_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_PERCLK_ROOT,
+ IMX_CCM_CLKO1_SEL_CKIL_SYNC_CLK_ROOT,
+ IMX_CCM_CLKO1_SEL_PLL4_MAIN_CLK
+} IMX_CCM_CLKO1_SEL;
+
+// CCOSR.CLKO2_SEL
+typedef enum {
+ IMX_CCM_CLKO2_SEL_MMDC_CLK_ROOT = 1,
+ IMX_CCM_CLKO2_SEL_USDHC4_CLK_ROOT = 2,
+ IMX_CCM_CLKO2_SEL_USDHC1_CLK_ROOT = 3,
+ IMX_CCM_CLKO2_SEL_WRCK_CLK_ROOT = 5,
+ IMX_CCM_CLKO2_SEL_ECSPI_CLK_ROOT = 6,
+ IMX_CCM_CLKO2_SEL_USDHC3_CLK_ROOT = 8,
+ IMX_CCM_CLKO2_SEL_PCIE_CLK_ROOT = 9,
+ IMX_CCM_CLKO2_SEL_ARM_CLK_ROOT = 10,
+ IMX_CCM_CLKO2_SEL_CSI_CORE = 11,
+ IMX_CCM_CLKO2_SEL_DISPLAY_AXI_CLK_ROOT = 12,
+ IMX_CCM_CLKO2_SEL_OSC_CLK = 14,
+ IMX_CCM_CLKO2_SEL_USDHC2_CLK_ROOT = 17,
+ IMX_CCM_CLKO2_SEL_SSI1_CLK_ROOT = 18,
+ IMX_CCM_CLKO2_SEL_SSI2_CLK_ROOT = 19,
+ IMX_CCM_CLKO2_SEL_SSI3_CLK_ROOT = 20,
+ IMX_CCM_CLKO2_SEL_GPU_AXI_CLK_ROOT = 21,
+ IMX_CCM_CLKO2_SEL_CAN_CLK_ROOT = 23,
+ IMX_CCM_CLKO2_SEL_LVDS_CLK_ROOT = 24,
+ IMX_CCM_CLKO2_SEL_QSPI1_CLK_ROOT = 25,
+ IMX_CCM_CLKO2_SEL_ESAI_CLK_ROOT = 26,
+ IMX_CCM_CLKO2_SEL_ACLK_EIM_SLOW_CLK_ROOT = 27,
+ IMX_CCM_CLKO2_SEL_UART_CLK_ROOT = 28,
+ IMX_CCM_CLKO2_SEL_SPDIF0_CLK_ROOT = 29,
+ IMX_CCM_CLKO2_SEL_AUDIO_CLK_ROOT = 36
+} IMX_CCM_CLKO2_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 CLKO1_SEL : 4; // 0-3 Selection of the clock to be generated on CCM_CLKO1 (IMX_CCM_CLKO1_SEL)
+ UINT32 CLKO1_DIV : 3; // 4-6 Setting the divider of CCM_CLKO1
+ UINT32 CLKO1_EN : 1; // 7 Enable of CCM_CLKO1 clock
+ UINT32 CLK_OUT_SEL : 1; // 8 CCM_CLKO1 output to reflect CCM_CLKO1 or CCM_CLKO2 clocks
+ UINT32 reserved1 : 7; // 9-15
+ UINT32 CLKO2_SEL : 5; // 16-20 Selection of the clock to be generated on CCM_CLKO2 (IMX_CCM_CLKO2_SEL)
+ UINT32 CLKO2_DIV : 3; // 21-23 Setting the divider of CCM_CLKO2
+ UINT32 CLKO2_EN : 1; // 24 Enable of CCM_CLKO2 clock
+ UINT32 reserved2 : 7; // 25-31
+ // MSB
+ };
+} IMX_CCM_CCOSR_REG; // SX RM.p847
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 reserved1 : 2; // 0-1
+ UINT32 csi_clk_enable : 2; // 2-3 csi clock (csi_clk_enable)
+ UINT32 reserved2 : 2; // 4-5
+ UINT32 i2c1_serial_clk_enable : 2; // 6-7 i2c1_serial clock (i2c1_serial_clk_enable)
+ UINT32 i2c2_serial_clk_enable : 2; // 8-9 i2c2_serial clock (i2c2_serial_clk_enable)
+ UINT32 i2c3_serial_clk_enable : 2; // 10-11 i2c3_serial clock (i2c3_serial_clk_enable)
+ UINT32 iim_clk_enable : 2; // 12-13 OCOTP_CTRL clock (iim_clk_enable)
+ UINT32 iomux_ipt_clk_io_enable : 2; // 14-15 iomux_ipt_clk_io clock (iomux_ipt_clk_io_enable)
+ UINT32 ipmux1_clk_enable : 2; // 16-17 ipmux1 clock (ipmux1_clk_enable)
+ UINT32 ipmux2_clk_enable : 2; // 18-19 ipmux2 clock (ipmux2_clk_enable)
+ UINT32 ipmux3_clk_enable : 2; // 20-21 ipmux3 clock (ipmux3_clk_enable)
+ UINT32 ipsync_ip2apb_tzasc1_ipg_master_clk_enable : 2; // 22-23 ipsync_ip2apb_tzasc1_ipg clocks (ipsync_ip2apb_tzasc1_ipg_master_clk_enable)
+ UINT32 reserved3 : 2; // 24-25
+ UINT32 reserved4 : 2; // 26-27
+ UINT32 lcd_clk_enable : 2; // 28-29 lcd clocks (lcd_clk_enable)
+ UINT32 pxp_clk_enable : 2; // 30-31 pxp clocks (pxp_clk_enable)
+ // MSB
+ };
+} IMX_CCM_CCGR2_REG; // SX RM.p853
+// Check(IMX_CCM_CCGR2_REG, sizeof(UINT32));
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 reserved1 : 2; // 0-1
+ UINT32 m4_clk_enable : 2; // 2-3 m4 clock (m4_clk_enable)
+ UINT32 enet_clk_enable : 2; // 4-5 enet clock (enet_clk_enable)
+ UINT32 disp_axi_clk_enable : 2; // 6-7 display axi clock (disp_axi_clk_enable)
+ UINT32 lcdif2_pix_clk_enable : 2; // 8-9 lcdif2 pix clock (lcdif2_pix_clk_enable)
+ UINT32 lcdif1_pix_clk_enable : 2; // 10-11 lcdif1 pix clock (lcdif1_pix_clk_enable)
+ UINT32 ldb_di0_clk_enable : 2; // 12-13 ldb_di0 clock (ldb_di0_clk_enable)
+ UINT32 qspi1_clk_enable : 2; // 14-15 qspi1 clock (qspi1_clk_enable)
+ UINT32 reserved2 : 2; // 16-17
+ UINT32 mlb_clk_enable : 2; // 18-19 mlb clock (mlb_clk_enable)
+ UINT32 mmdc_core_aclk_fast_core_p0_enable : 2; // 20-21 mmdc_core_aclk_fast_core_p0 clock (mmdc_core_aclk_fast_core_p0_enable)
+ UINT32 reserved3 : 2; // 22-23
+ UINT32 mmdc_core_ipg_clk_p0_enable : 2; // 24-25 mmdc_core_ipg_clk_p0 clock (mmdc_core_ipg_clk_p0_enable)
+ UINT32 mmdc_core_ipg_clk_p1_enable : 2; // 26-27 mmdc_core_ipg_clk_p1 clock (mmdc_core_ipg_clk_p1_enable)
+ UINT32 ocram_clk_enable : 2; // 28-29 ocram clock (ocram_clk_enable)
+ UINT32 reserved4 : 2; // 30-31
+ // MSB
+ };
+} IMX_CCM_CCGR3_REG;
+
+typedef enum {
+ IMX_CCM_PERCLK_CLK_SEL_IPG_CLK_ROOT = 0,
+ IMX_CCM_PERCLK_CLK_SEL_OSC_CLK = 1
+} IMX_CCM_PERCLK_CLK_SEL;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ UINT32 perclk_podf : 6; // 0-5 Divider for perclk podf.
+ UINT32 perclk_clk_sel : 1; // 6 Selector for the perclk clock multiplexor (IMX_CCM_PERCLK_CLK_SEL);
+ UINT32 qspi1_sel : 3; // 7-9 QSPI1 clock select
+ UINT32 ssi1_clk_sel : 2; // 10-11 Selector for ssi1 clock multiplexer
+ UINT32 ssi2_clk_sel : 2; // 12-13 Selector for ssi2 clock multiplexer
+ UINT32 ssi3_clk_sel : 2; // 14-15 Selector for ssi3 clock multiplexer
+ UINT32 usdhc1_clk_sel : 1; // 16 Selector for usdhc1 clock multiplexer
+ UINT32 usdhc2_clk_sel : 1; // 17 Selector for usdhc2 clock multiplexer
+ UINT32 usdhc3_clk_sel : 1; // 18 Selector for usdhc3 clock multiplexe
+ UINT32 usdhc4_clk_sel : 1; // 19 Selector for usdhc4 clock multiplexer
+ UINT32 lcdif2_podf : 3; // 20-22 Post-divider for lcdif2 clock.
+ UINT32 aclk_eim_slow_podf : 3; // 23-25 Divider for aclk_eim_slow clock root.
+ UINT32 qspi1_podf : 3; // 26-28 Divider for QSPI1 clock root
+ UINT32 aclk_eim_slow_sel : 2; // 29-30 Selector for aclk_eim_slow root clock multiplexer
+ UINT32 reserved1 : 1; // 31
+ };
+} IMX_CCM_CSCMR1_REG; // SX RM.p818
+
+typedef struct {
+ UINT32 CCR; // 0x00 CCM Control Register (CCM_CCR)
+ UINT32 CCDR; // 0x04 CCM Control Divider Register (CCM_CCDR)
+ UINT32 CSR; // 0x08 CCM Status Register (CCM_CSR)
+ UINT32 CCSR; // 0x0C CCM Clock Switcher Register (CCM_CCSR)
+ UINT32 CACRR; // 0x10 CCM Arm Clock Root Register (CCM_CACRR)
+ UINT32 CBCDR; // 0x14 CCM Bus Clock Divider Register (CCM_CBCDR)
+ UINT32 CBCMR; // 0x18 CCM Bus Clock Multiplexer Register (CCM_CBCMR)
+ UINT32 CSCMR1; // 0x1C CCM Serial Clock Multiplexer Register 1 (CCM_CSCMR1)
+ UINT32 CSCMR2; // 0x20 CCM Serial Clock Multiplexer Register 2 (CCM_CSCMR2)
+ UINT32 CSCDR1; // 0x24 CCM Serial Clock Divider Register 1 (CCM_CSCDR1)
+ UINT32 CS1CDR; // 0x28 CCM SSI1 Clock Divider Register (CCM_CS1CDR)
+ UINT32 CS2CDR; // 0x2C CCM SSI2 Clock Divider Register (CCM_CS2CDR)
+ UINT32 CDCDR; // 0x30 CCM D1 Clock Divider Register (CCM_CDCDR)
+ UINT32 CHSCCDR; // 0x34 CCM HSC Clock Divider Register (CCM_CHSCCDR)
+ UINT32 CSCDR2; // 0x38 CCM Serial Clock Divider Register 2 (CCM_CSCDR2)
+ UINT32 CSCDR3; // 0x3C CCM Serial Clock Divider Register 3 (CCM_CSCDR3)
+ UINT32 reserved1;
+ UINT32 CWDR; // 0x44 CCM Wakeup Detector Register (CCM_CWDR)
+ UINT32 CDHIPR; // 0x48 CCM Divider Handshake In-Process Register (CCM_CDHIPR)
+ UINT32 reserved2[2];
+ UINT32 CLPCR; // 0x54 CCM Low Power Control Register (CCM_CLPCR)
+ UINT32 CISR; // 0x58 CCM Interrupt Status Register (CCM_CISR)
+ UINT32 CIMR; // 0x5C CCM Interrupt Mask Register (CCM_CIMR)
+ UINT32 CCOSR; // 0x60 CCM Clock Output Source Register (CCM_CCOSR)
+ UINT32 CGPR; // 0x64 CCM General Purpose Register (CCM_CGPR)
+ UINT32 CCGR[7]; // 0x68-80 CCM Clock Gating Register 0-6 (CCM_CCGR0-CCM_CCGR6)
+ UINT32 reserved3;
+ UINT32 CMEOR; // 0x88 CCM Module Enable Override Register (CCM_CMEOR)
+} IMX_CCM_REGISTERS;
+
+//
+// CCM Analog
+//
+
+typedef enum {
+ IMX_PLL_BYPASS_CLK_SRC_REF_CLK_24M,
+ IMX_PLL_BYPASS_CLK_SRC_CLK1,
+ IMX_PLL_BYPASS_CLK_SRC_GPANAIO, // Only for CCM_ANALOG_PLL_SYS and CCM_ANALOG_PLL_USB1n (SX RM.p868)
+ IMX_PLL_BYPASS_CLK_SRC_CHRG_DET_B // Only for CCM_ANALOG_PLL_SYS and CCM_ANALOG_PLL_USB1n (SX RM.p868)
+} IMX_PLL_BYPASS_CLK_SRC; // SX RM.p866
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 PFD0_FRAC : 6; // 0-5 fractional divide value. The resulting frequency shall be 528*18/PFD0_FRAC where PFD0_FRAC is in the range 12-35.
+ UINT32 PFD0_STABLE : 1; // 6
+ UINT32 PFD0_CLKGATE : 1; // 7 Set to 1 to gate ref_pfd0
+ UINT32 PFD1_FRAC : 6; // 8-13 fractional divide value
+ UINT32 PFD1_STABLE : 1; // 14
+ UINT32 PFD1_CLKGATE : 1; // 15 Set to 1 to gate ref_pfd1
+ UINT32 PFD2_FRAC : 6; // 16-21 fractional divide value
+ UINT32 PFD2_STABLE : 1; // 22
+ UINT32 PFD2_CLKGATE : 1; // 23 Set to 1 to gate ref_pfd2
+ UINT32 PFD3_FRAC : 6; // 24-29 fractional divide value
+ UINT32 PFD3_STABLE : 1; // 30
+ UINT32 PFD3_CLKGATE : 1; // 31 Set to 1 to gate ref_pfd3
+ // MSB
+ };
+} IMX_CCM_PFD_480_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 PFD0_FRAC : 6; // 0-5 fractional divide value. The resulting frequency shall be 528*18/PFD0_FRAC where PFD0_FRAC is in the range 12-35.
+ UINT32 PFD0_STABLE : 1; // 6
+ UINT32 PFD0_CLKGATE : 1; // 7 Set to 1 to gate ref_pfd0
+ UINT32 PFD1_FRAC : 6; // 8-13 fractional divide value
+ UINT32 PFD1_STABLE : 1; // 14
+ UINT32 PFD1_CLKGATE : 1; // 15 Set to 1 to gate ref_pfd1
+ UINT32 PFD2_FRAC : 6; // 16-21 fractional divide value
+ UINT32 PFD2_STABLE : 1; // 22
+ UINT32 PFD2_CLKGATE : 1; // 23 Set to 1 to gate ref_pfd2
+ UINT32 PFD3_FRAC : 6; // 24-29 fractional divide value. The resulting frequency shall be 528*18/PFD3_FRAC where PFD3_FRAC is in the range 12-35
+ UINT32 PFD3_STABLE : 1; // 30
+ UINT32 PFD3_CLKGATE : 1; // 31 Set to 1 to gate ref_pfd3
+ // MSB
+ };
+} IMX_CCM_PFD_528_REG; // SX RM.p888
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 DIV_SELECT : 7; // 0-6 Valid range for divider value: 54-108. Fout = Fin * div_select/2.0
+ UINT32 reserved1 : 5; // 7-11
+ UINT32 POWERDOWN : 1; // 12 Powers down the PLL.
+ UINT32 ENABLE: 1; // 13 Enable the clock output.
+ UINT32 BYPASS_CLK_SRC : 2; // 14-15 Determines the bypass and PLL reference clock source.
+ UINT32 BYPASS : 1; // 16 Bypass the PLL.
+ UINT32 LVDS_SEL : 1; // 17 Analog Debug Bit
+ UINT32 LVDS_24MHZ_SEL : 1; // 18 Analog Debug Bit
+ UINT32 reserved2 : 1; // 19 PLL_SEL (Reserved)
+ UINT32 reserved3 : 11; // 20-30
+ UINT32 LOCK : 1; // 31 1 - PLL is currently locked. 0 - PLL is not currently locked.
+ // MSB
+ };
+} IMX_CCM_ANALOG_PLL_ARM_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 DIV_SELECT : 1; // 0 0 - Fout=Fref*20; 1 - Fout=Fref*22.
+ UINT32 reserved1 : 11; // 1-11
+ UINT32 POWERDOWN : 1; // 12 Powers down the PLL.
+ UINT32 ENABLE : 1; // 13 Enable PLL output
+ UINT32 BYPASS_CLK_SRC : 2; // 14-15 Determines the bypass source.
+ UINT32 BYPASS : 1; // 16 Bypass the PLL.
+ UINT32 reserved2 : 1; // 17
+ UINT32 PFD_OFFSET_EN : 1; // 18 Enables an offset in the phase frequency detector
+ UINT32 reserved3 : 12; // 19-30
+ UINT32 LOCK : 1; // 31 1 - PLL is currently locked; 0 - PLL is not currently locked.
+ // MSB
+ };
+} IMX_CCM_ANALOG_PLL_SYS_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 DIV_SELECT : 2; // 0-1 - Fout=Fref*20; 1 - Fout=Fref*22.
+ UINT32 reserved1 : 4; // 2-5
+ UINT32 EN_USB_CLKS : 1; // 6 Powers the 9-phase PLL outputs for USBPHYn
+ UINT32 reserved2 : 5; // 7-11
+ UINT32 POWER : 1; // 12 Powers up the PLL.
+ UINT32 ENABLE : 1; // 13 Enable the PLL clock output
+ UINT32 BYPASS_CLK_SRC : 2; // 14-15 Determines the bypass source
+ UINT32 BYPASS : 1; // 16 Bypass the PLL.
+ UINT32 reserved3 : 14; // 17-30
+ UINT32 LOCK : 1; // 31 1 - PLL is currently locked
+ // MSB
+ };
+} IMX_CCM_ANALOG_PLL_USB1_REG;
+
+typedef enum {
+ IMX_POST_DIV_SELECT_DIVIDE_4,
+ IMX_POST_DIV_SELECT_DIVIDE_2,
+ IMX_POST_DIV_SELECT_DIVIDE_1,
+} IMX_CCM_PLL_VIDEO_CTRL_POST_DIV_SELECT;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 DIV_SELECT : 7; // 0-6 This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54
+ UINT32 Reserved1 : 5; // 7-11
+ UINT32 POWERDOWN : 1; // 12 Powers down the PLL
+ UINT32 ENABLE : 1; // 13 Enalbe PLL output
+ UINT32 BYPASS_CLK_SRC : 2; // 14-15 Determines the bypass source
+ UINT32 BYPASS : 1; // 16 Bypass the PLL
+ UINT32 Reserved2 : 1; // 17
+ UINT32 PFD_OFFSET_EN : 1; // 18 Enables an offset in the phase frequency detector
+ UINT32 POST_DIV_SELECT : 2; // 19-20 These bits implement a divider after the PLL, but before the enable and bypass mux.
+ UINT32 Reserved3 : 1; // 21
+ UINT32 Reserved4 : 9; // 22-30 Always set to zero
+ UINT32 LOCK : 1; // 31 PLL is/not currently locked
+ // MSB
+ };
+} IMX_CCM_PLL_VIDEO_CTRL_REG;
+
+//
+// Power Management Unit
+//
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 REG0_TARG : 5; // 0-4 target voltage for the ARM core power domain
+ UINT32 reserved1 : 4; // 5-8
+ UINT32 REG1_TARG : 5; // 9-13 target voltage for the VPU/GPU power domain
+ UINT32 reserved2 : 4; // 14-17
+ UINT32 REG2_TARG : 5; // 18-22 target voltage for the SOC power domain
+ UINT32 reserved3 : 4; // 23-26
+ UINT32 RAMP_RATE : 2; // 27-28 Regulator voltage ramp rate
+ UINT32 FET_ODRIVE : 1; // 29 increases the gate drive on power gating FET
+ UINT32 reserved4 : 2; // 30-31
+ // MSB
+ };
+} IMX_PMU_REG_CORE_REG;
+
+typedef enum {
+ PLL_ENET_DIV_SELECT_25MHZ = 0,
+ PLL_ENET_DIV_SELECT_50MHZ = 1,
+ PLL_ENET_DIV_SELECT_100MHZ = 2,
+ PLL_ENET_DIV_SELECT_125MHZ = 3,
+} CCM_ANALOG_PLL_ENET_DIV_SELECT;
+
+//
+// CCM ANALOG PLL Ethernet(n) register
+//
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ unsigned DIV_SELECT : 2; // 0-1
+ unsigned Zero1 : 5; // 2-6
+ unsigned Reserved1 : 5; // 7-11
+ unsigned POWERDOWN : 1; // 12
+ unsigned ENABLE : 1; // 13
+ unsigned BYPASS_CLK_SRC : 2; // 14-15
+ unsigned BYPASS : 1; // 16
+ unsigned Reserved2 : 1; // 17
+ unsigned PFD_OFFSET_EN : 1; // 18
+ unsigned ENABLE_125M : 1; // 19
+ unsigned ENABLE_100M : 1; // 20
+ unsigned Zero2 : 10; // 21-30
+ unsigned LOCK : 1; // 31
+ // MSB
+ };
+} IMX_CCM_ANALOG_PLL_ENET_REG;
+
+//
+// CCM ANALOG PLL Ethernet(n) register
+//
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ unsigned LVDS1_CLK_SEL : 5; // 0-4
+ unsigned LVDS2_CLK_SEL : 5; // 5-9
+ unsigned LVDSCLK1_OBEN : 1; // 10
+ unsigned LVDSCLK2_OBEN : 1; // 11
+ unsigned LVDSCLK1_IBEN : 1; // 12
+ unsigned LVDSCLK2_IBEN : 1; // 13
+ unsigned Reserved0 : 15; // 14-28
+ unsigned IRQ_TEMPSENSE : 1; // 29
+ unsigned IRQ_ANA_BO : 1; // 30
+ unsigned IRQ_DIG_BO : 1; // 31
+ // MSB
+ };
+} IMX_CCM_ANALOG_MISC1_REG;
+
+typedef struct {
+ UINT32 PLL_ARM; // 0x000 Analog ARM PLL control Register (CCM_ANALOG_PLL_ARM)
+ UINT32 PLL_ARM_SET; // 0x004 Analog ARM PLL control Register (CCM_ANALOG_PLL_ARM_SET)
+ UINT32 PLL_ARM_CLR; // 0x008 Analog ARM PLL control Register (CCM_ANALOG_PLL_ARM_CLR)
+ UINT32 PLL_ARM_TOG; // 0x00C Analog ARM PLL control Register (CCM_ANALOG_PLL_ARM_TOG)
+ UINT32 PLL_USB1; // 0x010 Analog USB1 480MHz PLL Control Register (CCM_ANALOG_PLL_USB1)
+ UINT32 PLL_USB1_SET; // 0x014 Analog USB1 480MHz PLL Control Register (CCM_ANALOG_PLL_USB1_SET)
+ UINT32 PLL_USB1_CLR; // 0x018 Analog USB1 480MHz PLL Control Register (CCM_ANALOG_PLL_USB1_CLR)
+ UINT32 PLL_USB1_TOG; // 0x01C Analog USB1 480MHz PLL Control Register (CCM_ANALOG_PLL_USB1_TOG)
+ UINT32 PLL_USB2; // 0x020 Analog USB2 480MHz PLL Control Register (CCM_ANALOG_PLL_USB2)
+ UINT32 PLL_USB2_SET; // 0x024 Analog USB2 480MHz PLL Control Register (CCM_ANALOG_PLL_USB2_SET)
+ UINT32 PLL_USB2_CLR; // 0x028 Analog USB2 480MHz PLL Control Register (CCM_ANALOG_PLL_USB2_CLR)
+ UINT32 PLL_USB2_TOG; // 0x02C Analog USB2 480MHz PLL Control Register (CCM_ANALOG_PLL_USB2_TOG)
+ UINT32 PLL_SYS; // 0x030 Analog System PLL Control Register (CCM_ANALOG_PLL_SYS)
+ UINT32 PLL_SYS_SET; // 0x034 Analog System PLL Control Register (CCM_ANALOG_PLL_SYS_SET)
+ UINT32 PLL_SYS_CLR; // 0x038 Analog System PLL Control Register (CCM_ANALOG_PLL_SYS_CLR)
+ UINT32 PLL_SYS_TOG; // 0x03C Analog System PLL Control Register (CCM_ANALOG_PLL_SYS_CLR)
+ UINT32 PLL_SYS_SS; // 0x040 528MHz System PLL Spread Spectrum Register (CCM_ANALOG_PLL_SYS_SS)
+ UINT32 reserved1[11];
+ UINT32 PLL_AUDIO; // 0x070 Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIO)
+ UINT32 PLL_AUDIO_SET; // 0x074 Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIO_SET)
+ UINT32 PLL_AUDIO_CLR; // 0x078 Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIO_CLR)
+ UINT32 PLL_AUDIO_TOG; // 0x07C Analog Audio PLL control Register (CCM_ANALOG_PLL_AUDIO_TOG)
+ UINT32 PLL_AUDIO_NUM; // 0x080 Numerator of Audio PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_AUDIO_NUM)
+ UINT32 reserved2[3];
+ UINT32 PLL_AUDIO_DENOM; // 0x090 Denominator of Audio PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_AUDIO_DENOM)
+ UINT32 reserved3[3];
+ UINT32 PLL_VIDEO; // 0x0A0 Analog Video PLL control Register (CCM_ANALOG_PLL_VIDEO)
+ UINT32 PLL_VIDEO_SET; // 0x0A4 Analog Video PLL control Register (CCM_ANALOG_PLL_VIDEO_SET)
+ UINT32 PLL_VIDEO_CLR; // 0x0A8 Analog Video PLL control Register (CCM_ANALOG_PLL_VIDEO_CLR)
+ UINT32 PLL_VIDEO_TOG; // 0x0AC Analog Video PLL control Register (CCM_ANALOG_PLL_VIDEO_TOG)
+ UINT32 PLL_VIDEO_NUM; // 0x0B0 Numerator of Video PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_VIDEO_NUM)
+ UINT32 reserved4[3];
+ UINT32 PLL_VIDEO_DENOM; // 0x0C0 Denominator of Video PLL Fractional Loop Divider Register (CCM_ANALOG_PLL_VIDEO_DENOM)
+ UINT32 reserved5[7];
+ UINT32 PLL_ENET; // 0x0E0 Analog ENET PLL Control Register (CCM_ANALOG_PLL_ENET)
+ UINT32 PLL_ENET_SET; // 0x0E4 Analog ENET PLL Control Register (CCM_ANALOG_PLL_ENET_SET)
+ UINT32 PLL_ENET_CLR; // 0x0E8 Analog ENET PLL Control Register (CCM_ANALOG_PLL_ENET_CLR)
+ UINT32 PLL_ENET_TOG; // 0x0EC Analog ENET PLL Control Register (CCM_ANALOG_PLL_ENET_TOG)
+ UINT32 PFD_480; // 0x0F0 480MHz Clock (PLL3) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_480)
+ UINT32 PFD_480_SET; // 0x0F4 480MHz Clock (PLL3) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_480_SET)
+ UINT32 PFD_480_CLR; // 0x0F8 480MHz Clock (PLL3) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_480_CLR)
+ UINT32 PFD_480_TOG; // 0x0FC 480MHz Clock (PLL3) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_480_TOG)
+ UINT32 PFD_528; // 0x100 528MHz Clock (PLL2) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_528)
+ UINT32 PFD_528_SET; // 0x104 528MHz Clock (PLL2) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_528_SET)
+ UINT32 PFD_528_CLR; // 0x108 528MHz Clock (PLL2) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_528_CLR)
+ UINT32 PFD_528_TOG; // 0x10C 528MHz Clock (PLL2) Phase Fractional Divider Control Register (CCM_ANALOG_PFD_528_TOG)
+ UINT32 reserved6[16];
+ UINT32 MISC0; // 0x150 Miscellaneous Register 0 (CCM_ANALOG_MISC0)
+ UINT32 MISC0_SET; // 0x154 Miscellaneous Register 0 (CCM_ANALOG_MISC0_SET)
+ UINT32 MISC0_CLR; // 0x158 Miscellaneous Register 0 (CCM_ANALOG_MISC0_CLR)
+ UINT32 MISC0_TOG; // 0x15C Miscellaneous Register 0 (CCM_ANALOG_MISC0_TOG)
+ UINT32 MISC1; // 0x160 Miscellaneous Register 1 (CCM_ANALOG_MISC1)
+ UINT32 MISC1_SET; // 0x164 Miscellaneous Register 1 (CCM_ANALOG_MISC1_SET)
+ UINT32 MISC1_CLR; // 0x168 Miscellaneous Register 1 (CCM_ANALOG_MISC1_CLR)
+ UINT32 MISC1_TOG; // 0x16C Miscellaneous Register 1 (CCM_ANALOG_MISC1_TOG)
+ UINT32 MISC2; // 0x170 Miscellaneous Register 2 (CCM_ANALOG_MISC2)
+ UINT32 MISC2_SET; // 0x174 Miscellaneous Register 2 (CCM_ANALOG_MISC2_SET)
+ UINT32 MISC2_CLR; // 0x178 Miscellaneous Register 2 (CCM_ANALOG_MISC2_CLR)
+ UINT32 MISC2_TOG; // 0x17C Miscellaneous Register 2 (CCM_ANALOG_MISC2_TOG)
+} IMX_CCM_ANALOG_REGISTERS; // SX RM.p864
+
+//
+// General Power Controller (GPC)
+//
+
+#define IMX_GPC_BASE 0x020DC000
+#define IMX_GPC_LENGTH 0x1000
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 PCR : 1; // 0 Power Control
+ UINT32 reserved : 31; // 1-31
+ // MSB
+ };
+} IMX_GPC_PGC_PGCR_REG;
+
+#define IMX_GPC_PGC_PUPSCR_SW_DEFAULT 1
+#define IMX_GPC_PGC_PUPSCR_SW2ISO_DEFAULT 0xf
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 SW : 6; // 0-5 number of IPG clock cycles before asserting power toggle on/off signal (switch_b)
+ UINT32 reserved1 : 2; // 6-7
+ UINT32 SW2ISO : 6; // 8-13 IPG clock cycles before negating isolation
+ UINT32 reserved2 : 18; // 14-31
+ // MSB
+ };
+} IMX_GPC_PGC_PUPSCR_REG;
+
+#define IMX_GPC_PGC_PDNSCR_ISO_DEFAULT 1
+#define IMX_GPC_PGC_PDNSCR_ISO2SW_DEFAULT 1
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ISO : 6; // 0-5 number of IPG clocks before isolation
+ UINT32 reserved1 : 2; // 6-7
+ UINT32 ISO2SW : 6; // 8-13 number of IPG clocks before negating power toggle on/off signal (switch_b)
+ UINT32 reserved2 : 18; // 14-31
+ // MSB
+ };
+} IMX_GPC_PGC_PDNSCR_REG;
+
+typedef struct {
+ UINT32 CTRL; // 0x0 PGC Control Register (PGC_GPU/CPU_CTRL)
+ UINT32 PUPSCR; // 0x4 Power Up Sequence Control Register (PGC_GPU/CPU_PUPSCR)
+ UINT32 PDNSCR; // 0x8 Pull Down Sequence Control Register (PGC_GPU/CPU_PDNSCR)
+ UINT32 SR; // 0xC Power Gating Controller Status Register (PGC_GPU/CPU_SR)
+} IMX_GPC_PGC_REGISTERS;
+
+//
+// General Power Controller (GPC)
+//
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 gpu_vpu_pdn_req : 1; // 0 GPU/VPU Power Down request. Self-cleared bit.
+ UINT32 gpu_vpu_pup_req : 1; // 1 GPU/VPU Power Up request. Self-cleared bit.
+ UINT32 MEGA_PDN_REQ : 1; // 2 MEGA domain power down request. Self-clear bit.
+ UINT32 MEGA_PUP_REQ : 1; // 3 MEGA domain power up request. Self-clear bit.
+ UINT32 DISPLAY_PDN_REQ : 1; // 4 Display Power Down request. Self-cleared bit.
+ UINT32 DISPLAY_PUP_REQ : 1; // 5 Display Power Up request. Self-cleared bit.
+ UINT32 PCIE_PHY_PDN_REQ : 1; // 6 PCIE PHY power down request. Self-clear bit.
+ UINT32 PCIE_PHY_PUP_REQ : 1; // 7 PCIE PHY power up request. Self-clear bit.
+ UINT32 reserved1 : 8; // 8-15
+ UINT32 DVFS0CR : 1; // 16 DVFS0 (ARM) Change request (bit is read-only)
+ UINT32 VADC_ANALOG_OFF : 1; // 17 Indication to VADC whether the analog power to VADC is available or not
+ UINT32 VADC_EXT_PWD_N : 1; // 18 VADC power down bit
+ UINT32 reserved2 : 2; // 19-20
+ UINT32 GPCIRQM : 1; // 21 GPC interrupt/event masking
+ UINT32 L2_PGE : 1; // 22 L2 Cache Power Gate Enable
+ UINT32 reserved3 : 9; // 23-31
+ // MSB
+ };
+} IMX_GPC_CNTR_REG; //SX RM.p1466
+
+typedef struct {
+ UINT32 CNTR; // 0x000 GPC Interface control register (GPC_CNTR)
+ UINT32 PGR; // 0x004 GPC Power Gating Register (GPC_PGR)
+ UINT32 IMR1; // 0x008 IRQ masking register 1 (GPC_IMR1)
+ UINT32 IMR2; // 0x00C IRQ masking register 2 (GPC_IMR2)
+ UINT32 IMR3; // 0x010 IRQ masking register 3 (GPC_IMR3)
+ UINT32 IMR4; // 0x014 IRQ masking register 4 (GPC_IMR4)
+ UINT32 ISR1; // 0x018 IRQ status resister 1 (GPC_ISR1)
+ UINT32 ISR2; // 0x01C IRQ status resister 2 (GPC_ISR2)
+ UINT32 ISR3; // 0x020 IRQ status resister 3 (GPC_ISR3)
+ UINT32 ISR4; // 0x024 IRQ status resister 4 (GPC_ISR4)
+ UINT32 reserved1[142];
+ IMX_GPC_PGC_REGISTERS PGC_GPU; // 0x260-0x26C GPU PGC Control
+ UINT32 reserved2[12];
+ IMX_GPC_PGC_REGISTERS PGC_CPU; // 0x2A0-0x2AC CPU PGC Control
+} IMX_GPC_REGISTERS;
+
+//
+// Ethernet controller (ENET)
+//
+
+#define IMX_ENET_BASE 0x02188000
+#define IMX_ENET_LENGTH 0x4000
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 RESET : 1; // 0 Ethernet MAC Reset
+ UINT32 ETHEREN : 1; // 1 Ethernet Enable
+ UINT32 MAGICEN : 1; // 2 Magic Packet Detection Enable
+ UINT32 SLEEP : 1; // 3 Sleep Mode Enable
+ UINT32 EN1588 : 1; // 4 EN1588 Enable
+ UINT32 SPEED : 1; // 5 Selects between 10/100 and 1000 Mbps modes of operation
+ UINT32 DBGEN : 1; // 6 Debug Enable
+ UINT32 reserved1 : 1; // 7
+ UINT32 DBSWP : 1; // 8 Descriptor Byte Swapping Enable
+ UINT32 SVLANEN : 1; // 9 Enable additional detection of S-VLAN tag according to IEEE802.1Q
+ UINT32 VLANUSE2ND : 1; // 10 VLAN use second tag
+ UINT32 SVLANDBL : 1; // 11 S-VLAN double tag
+ UINT32 reserved2 : 4; // 12-15 This field must be set to 0
+ UINT32 TXC_DLY : 1; // 16 Transmit clock delay
+ UINT32 RXC_DLY : 1; // 17 Receive clock delay
+ UINT32 reserved3 : 14; // 18-31 This field must be set to 01110000000000b = 0x1C00
+ // MSB
+ };
+} IMX_ENET_ECR_REG;
+
+#define IMX_ENET_ECR_REG_SET_RESERVED(ecrReg) (ecrReg)->reserved3 = 0x1C00
+
+typedef struct {
+ UINT32 reserved0; // 0
+ UINT32 EIR; // 4
+ UINT32 EIMR; // 8
+ UINT32 reserved1; // Ch
+ UINT32 RDAR; // 10h
+ UINT32 TDAR; // 14h
+ UINT32 reserved2[3]; // 18h - 20h
+ UINT32 ECR; // 24h Ethernet Control Register (ENET_ECR)
+ UINT32 reserved3[6]; // 28h - 3Ch
+ UINT32 MMFR; // 40h
+ UINT32 MSCR; // 44h
+ UINT32 reserved4[7]; // 48h - 60h
+ UINT32 MIBC; // 64h
+ UINT32 reserved5[7]; //
+ UINT32 RCR; // 84h
+ UINT32 reserved6[15]; //
+ UINT32 TCR; // C4h
+ UINT32 reserved7[7];
+ UINT32 PALR; // E4h
+ UINT32 PAUR; // E8h
+ UINT32 OPD; // ECh
+ UINT32 reserved8[322];
+} IMX_ENET_REGISTERS;
+
+//
+// GPIO Controller (GPIO)
+//
+
+#define IMX_GPIO_BASE 0x0209C000
+#define IMX_GPIO_LENGTH (7 * 0x4000)
+
+//
+// USB CORE (EHCI)
+//
+
+#define IMX_USBCORE_BASE 0x02184000
+#define IMX_USBCORE_LENGTH 0x200
+ #define IMX_USBCMD_OFFSET 0x140
+ #define IMX_USBMODE_OFFSET 0x1A8
+
+//
+// To do:
+// - Add the USB Core register file
+//
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 RS : 1; // 0 Run/Stop (RS) . Read/Write. Default 0b. 1=Run. 0=Stop.
+ UINT32 RST : 1; // 1 Controller Reset (RESET) - Read/Write.
+ UINT32 FS_1 : 2; // 2-3 Frame List Size (Read/Write or Read Only). Default 000b.
+ UINT32 PSE : 1; // 4 Periodic Schedule Enable- Read/Write. Default 0b.
+ UINT32 ASE : 1; // 5 Asynchronous Schedule Enable Read/Write. Default 0b.
+ UINT32 IAA : 1; // 6 Interrupt on Async Advance Doorbell Read/Write.
+ UINT32 reserved1 : 1; // 7
+ UINT32 ASP : 2; // 8-9 Asynchronous Schedule Park Mode Count (OPTIONAL) . Read/Write.
+ UINT32 reserved2 : 1; // 10 Reserved. These bits are reserved and should be set to zero.
+ UINT32 ASPE : 1; // 11 Asynchronous Schedule Park Mode Enable (OPTIONAL) . Read/Write.
+ UINT32 ATDTW : 1; // 12 Add dTD TripWire - Read/Write. [device mode only]
+ UINT32 SUTW : 1; // 13 Setup TripWire - Read/Write. [device mode only]
+ UINT32 reserved3 : 1; // 14
+ UINT32 FS2 : 1; // 15 Frame List Size - (Read/Write or Read Only). [host mode only]
+ UINT32 ITC : 8; // 16-23 Interrupt Threshold Control Read/Write. Default 08h.
+ UINT32 reserved : 8; // 24-31 Reserved. These bits are reserved and should be set to zero.
+ // LSB
+ };
+} USB_USBCMD_REG;
+
+typedef enum {
+ IMX_USBMODE_IDLE = 0,
+ IMX_USBMODE_DEVICE = 2,
+ IMX_USBMODE_HOST = 3,
+} IMX_USBMODE_CM;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 CM : 2; // 0-1 Controller Mode.
+ UINT32 ES : 1; // 1 Endian Select (0- Little, 1-Big)
+ UINT32 SLOM : 1; // 3 Setup Lockout Mode
+ UINT32 SDIS : 1; // 4 Stream Disable Mode
+ UINT32 reserved : 26; // 5-31
+ // LSB
+ };
+} USB_USBMODE_REG;
+
+//
+// USB Non-CORE
+//
+
+#define IMX_USBNONCORE_BASE 0x02184800
+#define IMX_USBNONCORE_LENGTH 0x20
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 reserved1 : 7; // 0-6
+ UINT32 OVER_CUR_DIS : 1; // 7 Disable Overcurrent Detection
+ UINT32 OVER_CUR_POL : 1; // 8 Polarity of Overcurrent (1-active low, 0-active high)
+ UINT32 PWR_POL : 1; // 9 Power Polarity (1-active high, 0-active low)
+ UINT32 WIE : 1; // 10 Wake-up Interrupt Enable
+ UINT32 RESET : 1; // 11 Force Host 1 UTMI PHY Reset.
+ UINT32 SUSPENDM : 1; // 12 Force Host 1 UTMI PHY Suspend.
+ UINT32 UTMI_ON_CLOCK : 1; // 13 Force UTMI PHY clock output on even if in low-power suspend mode.
+ UINT32 WKUP_SW_EN : 1; // 14 Software Wake-up Enable
+ UINT32 WKUP_SW : 1; // 15 Software Wake-up
+ UINT32 WKUP_ID_EN : 1; // 16 Wake-up on ID change enable
+ UINT32 WKUP_VBUS_EN : 1; // 17 wake-up on VBUS change enable
+ UINT32 reserved2 : 13; // 18-30
+ UINT32 WIR : 1; // 31 Wake-up Interrupt Request
+ // LSB
+ };
+} USBNC_USB_UH_CTRL_REG;
+
+typedef struct {
+ UINT32 USBNC_USB_OTG_CTRL; // 0x00 USB OTG Control Register (USBNC_USB_OTG_CTRL)
+ UINT32 USBNC_USB_UH1_CTRL; // 0x04 USB Host1 Control Register (USBNC_USB_UH1_CTRL)
+ UINT32 USBNC_USB_UH2_CTRL; // 0x08 USB Host2 Control Register (USBNC_USB_UH2_CTRL)
+ UINT32 USBNC_USB_UH3_CTRL; // 0x0C USB Host3 Control Register (USBNC_USB_UH3_CTRL)
+ UINT32 USBNC_USB_UH2_HSIC_CTRL; // 0x10 USB Host2 HSIC Control Register (USBNC_USB_UH2_HSIC_CTRL)
+ UINT32 USBNC_USB_UH3_HSIC_CTRL; // 0x14 USB Host3 HSIC Control Register (USBNC_USB_UH3_HSIC_CTRL)
+ UINT32 USBNC_USB_OTG_PHY_CTRL_0; // 0x18 OTG UTMI PHY Control 0 Register (USBNC_USB_OTG_PHY_CTRL_0)
+ UINT32 USBNC_USB_UH1_PHY_CTRL_0; // 0x1C Host1 UTMI PHY Control 0 Register (USBNC_USB_UH1_PHY_CTRL_0)
+} IMX_USBNONCORE_REGISTERS;
+
+
+//
+// USB PHY
+//
+
+#define IMX_USBPHY1_BASE 0x020C9000
+#define IMX_USBPHY2_BASE 0x020CA000
+#define IMX_USBPHY_LENGTH 0x1000
+
+typedef enum {
+ IMX_USBPHY0, // OTG
+ IMX_USBPHY1,
+
+ IMX_USBPHY_COUNT
+} IMX_USBPHY_ID;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 ENOTG_ID_CHG_IRQ : 1; // 0 Enable OTG_ID_CHG_IRQ.
+ UINT32 ENHOSTDISCONDETECT : 1; // 1 For host mode, enables high-speed disconnect detector.
+ UINT32 ENIRQHOSTDISCON : 1; // 2 Enables interrupt for detection of disconnection to Device when in high-speed host mode.
+ UINT32 HOSTDISCONDETECT_IRQ : 1; // 3 Indicates that the device has disconnected in high-speed mode.
+ UINT32 ENDEVPLUGINDETECT : 1; // 4 For device mode, enables 200-KOhm pullups for detecting connectivity to the host.
+ UINT32 DEVPLUGIN_POLARITY : 1; // 5 For device mode interrupt generation polarity
+ UINT32 OTG_ID_CHG_IRQ : 1; // 6 OTG ID change interrupt. Indicates the value of ID pin changed.
+ UINT32 ENOTGIDDETECT : 1; // 7 Enables circuit to detect resistance of MiniAB ID pin.
+ UINT32 RESUMEIRQSTICKY : 1; // 8 1 makes RESUME_IRQ bit a sticky bit.
+ UINT32 ENIRQRESUMEDETECT : 1; // 9 Enables interrupt for detection of a non-J state on the USB line.
+ UINT32 RESUME_IRQ : 1; // 10 Indicates that the host is sending a wake-up after suspend
+ UINT32 ENIRQDEVPLUGIN : 1; // 11 Enables interrupt for the detection of connectivity to the USB line.
+ UINT32 DEVPLUGIN_IRQ : 1; // 12 Indicates that the device is connected
+ UINT32 DATA_ON_LRADC : 1; // 13 Enables the LRADC to monitor USB_DP and USB_DM.
+ UINT32 ENUTMILEVEL2 : 1; // 14 Enables UTMI+ Level2.
+ UINT32 ENUTMILEVEL3 : 1; // 15 Enables UTMI+ Level3.
+ UINT32 ENIRQWAKEUP : 1; // 16 Enables interrupt for the wakeup events
+ UINT32 WAKEUP_IRQ : 1; // 17 Indicates that there is a wakeup event.
+ UINT32 reserved1 : 1; // 18 reserved
+ UINT32 ENAUTOCLR_CLKGATE : 1; // 19 Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended.
+ UINT32 ENAUTOCLR_PHY_PWD : 1; // 20 Enables the feature to auto-clear the PWD register bits in USBPHYx_PWD if there is wakeup event while USB is suspended
+ UINT32 ENDPDMCHG_WKUP : 1; // 21 Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended
+ UINT32 ENIDCHG_WKUP : 1; // 22 Enables the feature to wakeup USB if ID is toggled when USB is suspended
+ UINT32 ENVBUSCHG_WKUP : 1; // 23 Enables the feature to wakeup USB if VBUS is toggled when USB is suspended.
+ UINT32 FSDLL_RST_EN : 1; // 24 Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet.
+ UINT32 reserved2 : 2; // 25-26
+ UINT32 OTG_ID_VALUE : 1; // 27
+ UINT32 HOST_FORCE_LS_SE0 : 1; // 28 Forces the next FS packet that is transmitted to have a EOP with LS timing.
+ UINT32 UTMI_SUSPENDM : 1; // 29 Used by the PHY to indicate a powered-down state.
+ UINT32 CLKGATE : 1; // 30 Gate UTMI Clocks. Clear to 0 to run clocks.
+ UINT32 SFTRST : 1; // 31 Soft-reset the USBPHYx_PWD, USBPHYx_TX, USBPHYx_RX, Set to 0 to release the PHY from reset.
+ // MSB
+ };
+} USBPHYx_CTRL_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 STEP : 16; // 0-15 Fixed read-only value reflecting the stepping of the RTL version.
+ UINT32 MINOR : 8; // 16-23 Fixed read-only value reflecting the MINOR field of the RTL version.
+ UINT32 MAJOR : 8; // 24-31 Fixed read-only value reflecting the MAJOR field of the RTL version
+ // MSB
+ };
+} USBPHYx_VERSION_REG;
+
+typedef struct {
+ UINT32 USBPHY_PWD; // 0x00 USB PHY Power-Down Register (USBPHY_PWD)
+ UINT32 USBPHY_PWD_SET; // 0x04 USB PHY Power-Down Register (USBPHY_PWD_SET)
+ UINT32 USBPHY_PWD_CLR; // 0x08 USB PHY Power-Down Register (USBPHY_PWD_CLR)
+ UINT32 USBPHY_PWD_TOG; // 0x0C USB PHY Power-Down Register (USBPHY_PWD_TOG)
+ UINT32 USBPHY_TX; // 0x10 USB PHY Transmitter Control Register (USBPHY_TX)
+ UINT32 USBPHY_TX_SET; // 0x14 USB PHY Transmitter Control Register (USBPHY_TX_SET)
+ UINT32 USBPHY_TX_CLR; // 0x18 USB PHY Transmitter Control Register (USBPHY_TX_CLR)
+ UINT32 USBPHY_TX_TOG; // 0x1C USB PHY Transmitter Control Register (USBPHY_TX_TOG)
+ UINT32 USBPHY_RX; // 0x20 USB PHY Receiver Control Register (USBPHY_RX)
+ UINT32 USBPHY_RX_SET; // 0x24 USB PHY Receiver Control Register(USBPHY_RX_SET)
+ UINT32 USBPHY_RX_CLR; // 0x28 USB PHY Receiver Control Register (USBPHY_RX_CLR)
+ UINT32 USBPHY_RX_TOG; // 0x2C USB PHY Receiver Control Register (USBPHY_RX_TOG)
+ UINT32 USBPHY_CTRL; // 0x30 USB PHY General Control Register (USBPHY_CTRL)
+ UINT32 USBPHY_CTRL_SET; // 0x34 USB PHY General Control Register (USBPHY_CTRL_SET)
+ UINT32 USBPHY_CTRL_CLR; // 0x38 USB PHY General Control Register (USBPHY_CTRL_CLR)
+ UINT32 USBPHY_CTRL_TOG; // 0x3C USB PHY General Control Register (USBPHY_CTRL_TOG)
+ UINT32 USBPHY_STATUS; // 0x40 USB PHY Status Register (USBPHY_STATUS)
+ UINT32 reserved1[3];
+ UINT32 USBPHY_DEBUG; // 0x50 USB PHY Debug Register (USBPHY_DEBUG)
+ UINT32 USBPHY_DEBUG_SET; // 0x54 USB PHY Debug Register(USBPHY_DEBUG_SET)
+ UINT32 USBPHY_DEBUG_CLR; // 0x58 USB PHY Debug Register (USBPHY_DEBUG_CLR)
+ UINT32 USBPHY_DEBUG_TOG; // 0x5C USB PHY Debug Register(USBPHY_DEBUG_TOG)
+ UINT32 USBPHY_DEBUG0_STATUS; // 0x60 UTMI Debug Status Register 0 (USBPHY_DEBUG0_STATUS)
+ UINT32 reserved2[3];
+ UINT32 USBPHY_DEBUG1; // 0x70 UTMI Debug Status Register 1 (USBPHY_DEBUG1)
+ UINT32 USBPHY_DEBUG1_SET; // 0x74 UTMI Debug Status Register 1 (USBPHY_DEBUG1_SET)
+ UINT32 USBPHY_DEBUG1_CLR; // 0x78 UTMI Debug Status Register 1 (USBPHY_DEBUG1_CLR)
+ UINT32 USBPHY_DEBUG1_TOG; // 0x7C UTMI Debug Status Register 1 (USBPHY_DEBUG1_TOG)
+ UINT32 USBPHY_VERSION; // 0x80 UTMI RTL Version (USBPHYx_VERSION)
+} IMX_USBPHY_REGISTERS;
+
+//
+// USB Analog
+//
+
+#define IMX_USBANA_BASE 0x020C81A0
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 reserved1 : 18; // 0-17
+ UINT32 CHK_CONTACT : 1; // 18
+ UINT32 CHK_CHRG_B : 1; // 19
+ UINT32 EN_B : 1; // 20
+ UINT32 reserved2 : 11; // 21-31
+ // MSB
+ };
+} USB_ANALOG_USB_CHRG_DETECT_REG;
+
+typedef union {
+ UINT32 AsUint32;
+ struct {
+ // LSB
+ UINT32 HS_USE_EXTERNAL_R : 1; // 0 Use external resistor to generate the current bias for the high speed transmitter.
+ UINT32 EN_DEGLITCH : 1; // 1 Enable the deglitching circuit of the USB PLL output.
+ UINT32 reserved1 : 28; // 2-29
+ UINT32 EN_CLK_UTMI : 1; // Enables the clk to the UTMI block.
+ UINT32 reserved2 : 1; // 31
+ // MSB
+ };
+} USB_ANALOG_USB_MISC_REG;
+
+typedef struct {
+ UINT32 USB_ANALOG_USB_VBUS_DETECT; // 0x00 USB VBUS Detect Register (USB_ANALOG_USB_VBUS_DETECT)
+ UINT32 USB_ANALOG_USB_VBUS_DETECT_SET; // 0x04 USB VBUS Detect Register (USB_ANALOG_USB_VBUS_DETECT_SET)
+ UINT32 USB_ANALOG_USB_VBUS_DETECT_CLR; // 0x08 USB VBUS Detect Register (USB_ANALOG_USB_VBUS_DETECT_CLR)
+ UINT32 USB_ANALOG_USB_VBUS_DETECT_TOG; // 0x0C USB VBUS Detect Register (USB_ANALOG_USB_VBUS_DETECT_TOG)
+ UINT32 USB_ANALOG_USB_CHRG_DETECT; // 0x10 USB Charger Detect Register (USB_ANALOG_USB_CHRG_DETECT)
+ UINT32 USB_ANALOG_USB_CHRG_DETECT_SET; // 0x14 USB Charger Detect Register (USB_ANALOG_USB_CHRG_DETECT_SET)
+ UINT32 USB_ANALOG_USB_CHRG_DETECT_CLR; // 0x18 USB Charger Detect Register (USB_ANALOG_USB_CHRG_DETECT_CLR)
+ UINT32 USB_ANALOG_USB_CHRG_DETECT_TOG; // 0x1C USB Charger Detect Register (USB_ANALOG_USB_CHRG_DETECT_TOG)
+ UINT32 USB_ANALOG_USB_VBUS_DETECT_STAT; // 0x20 USB VBUS Detect Status Register (USB_ANALOG_USB_VBUS_DETECT_STAT)
+ UINT32 reserved1[3];
+ UINT32 USB_ANALOG_USB_CHRG_DETECT_STAT; // 0x30 USB Charger Detect Status Register (USB_ANALOG_USB_CHRG_DETECT_STAT)
+ UINT32 reserved2[7];
+ UINT32 USB_ANALOG_USB_MISC; // 0x50 USB Misc Register (USB_ANALOG_USB_MISC)
+ UINT32 USB_ANALOG_USB_MISC_SET; // 0x54 USB Misc Register (USB_ANALOG_USB_MISC_SET)
+ UINT32 USB_ANALOG_USB_MISC_CLR; // 0x58 USB Misc Register (USB_ANALOG_USB_MISC_CLR)
+ UINT32 USB_ANALOG_USB_MISC_TOG; // 0x5C USB Misc Register (USB_ANALOG_USB_MISC_TOG)
+} IMX_USBANA_USB_REGISTERS;
+
+typedef struct {
+ IMX_USBANA_USB_REGISTERS USBANA[IMX_USBPHY_COUNT];
+ UINT32 USB_ANALOG_DIGPROG; // 0xC0 Chip Silicon Version (USB_ANALOG_DIGPROG)
+} IMX_USBANA_REGISTERS;
+
+#pragma pack(pop)
+
+#endif // __IMX6_SX_H__
--
2.16.2.gvfs.1.33.gf5370f1
next prev parent reply other threads:[~2018-07-20 6:33 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-20 6:33 [PATCH edk2-platforms 00/13] Silicon/NXP: Import NXP i.MX6 Package Chris Co
2018-07-20 6:33 ` Chris Co [this message]
2018-07-20 6:33 ` [PATCH edk2-platforms 02/13] Silicon/NXP: Add i.MX6 GPT and EPIT timer headers Chris Co
2018-07-20 6:33 ` [PATCH edk2-platforms 03/13] Silicon/NXP: Add iMX6Pkg dec Chris Co
2018-07-20 6:33 ` [PATCH edk2-platforms 04/13] Silicon/NXP: Add i.MX6 Timer DXE driver Chris Co
2018-07-20 6:33 ` [PATCH edk2-platforms 05/13] Silicon/NXP: Add i.MX6 GPT Timer library Chris Co
2018-07-20 6:33 ` [PATCH edk2-platforms 06/13] Silicon/NXP: Add i.MX6 USB Phy Library Chris Co
2018-07-20 6:33 ` [PATCH edk2-platforms 07/13] Silicon/NXP: Add i.MX6 I/O MUX library Chris Co
2018-07-20 6:33 ` [PATCH edk2-platforms 08/13] Silicon/NXP: Add i.MX6 Clock Library Chris Co
2018-07-20 6:33 ` [PATCH edk2-platforms 09/13] Silicon/NXP: Add i.MX6 ACPI tables Chris Co
2018-07-20 6:33 ` [PATCH edk2-platforms 10/13] Silicon/NXP: Add i.MX6 Board init library Chris Co
2018-07-20 6:34 ` [PATCH edk2-platforms 11/13] Silicon/NXP: Add i.MX6 PCIe DXE driver Chris Co
2018-07-20 6:34 ` [PATCH edk2-platforms 12/13] Silicon/NXP: Add i.MX6 GOP driver Chris Co
2018-07-20 6:34 ` [PATCH edk2-platforms 13/13] Silicon/NXP: Add i.MX6 common dsc and fdf files Chris Co
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