From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::533; helo=mail-pg1-x533.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7CE3C2098C8CB for ; Fri, 20 Jul 2018 01:03:46 -0700 (PDT) Received: by mail-pg1-x533.google.com with SMTP id r5-v6so6187956pgv.0 for ; Fri, 20 Jul 2018 01:03:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5xqx2r7poieZnu5szCIfuiS7kJL20KY1PltJswrk3N4=; b=by4KgtNCl66CBNErPnhj1tapcsEFevLZzVn3FSYAq1ofqngwyYhp9Imz8P/s70nX29 EPm4Aky6gQjkbaSgeoc/jtR1ZfbhkUfuy1cpz/l00TkVLolT/BBNEEMbflN1yrAe8kft /7U8NepNIK3k3Q9jsR8DIU/PcQci0Fpk3jjOY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5xqx2r7poieZnu5szCIfuiS7kJL20KY1PltJswrk3N4=; b=pAaa+sMX6LyDG0d2ynwrhJnzukr7BeHSgCiuYHe/tj1DqIYe0cXp1MSAlL7kiRkOd7 kqVo30f7xWkZPy7E63naKeHwHFRVwSBV9hgl2eqTJ1vuCE7Sqca8uS4jv+ISdf1DW6Ju K4cJY78Zrsqi6aQMW24td77Trx7kROECE6JEuySX+ivAZnjMBGxNHGfJAHsDITE2B9hS 7ubJuJegKzjYJGoDHqH3UjVNmQ5az2rf6Xg7SRhPmYdyh8J9pUDFuqSRTjOEc2h5Wd+e qBlYDKOMKHDK24MJurGsztrR6/wtU9UnXM0rWOts5LDY8kuIP9O/RkyuB+cRqOIGGB3E iJ3w== X-Gm-Message-State: AOUpUlHjQfbFg7ZhvrOYXYmXie5jHVdCxeT5qt+HS/SvXZlof2tMcLg1 4kCmB1zK9ewQJPXUlaYwr4iNKg== X-Google-Smtp-Source: AAOMgpehJ4YvD56h0sjFyEfgYfzucHUxHKIhgL5jO0im9dmxeaU4BBJD96sSd2Rz1ToY+F5n1vSXkQ== X-Received: by 2002:a63:1902:: with SMTP id z2-v6mr1082724pgl.86.1532073826176; Fri, 20 Jul 2018 01:03:46 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id n18-v6sm2066812pfa.50.2018.07.20.01.03.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 20 Jul 2018 01:03:45 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, Heyi Guo , Michael D Kinney Date: Fri, 20 Jul 2018 16:02:31 +0800 Message-Id: <20180720080242.3777-3-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180720080242.3777-1-ming.huang@linaro.org> References: <20180720080242.3777-1-ming.huang@linaro.org> Subject: [PATCH edk2-platforms v1 02/13] Hisilicon/D05/PlatformPciLib: fix misuse of macro X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jul 2018 08:03:46 -0000 From: Heyi Guo Each PCI root bridge has its own macro definitions for its resource aperture, so that one root bridge should not use macro definitions of other root bridges. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo Cc: Ard Biesheuvel Cc: Leif Lindholm Cc: Michael D Kinney --- Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c index ed6c4ac321..c0b756ccfb 100644 --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -159,7 +159,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB1RB0_ECAM_BASE), //MemBase (PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimit PCI_HB1RB0_IO_BASE, //IoBase - (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB0_CPUIOREGIONBASE + PCI_HB1RB0_IO_SIZE - 1), //IoLimit PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB0_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB0_PCI_BASE), //RbPciBar @@ -174,7 +174,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB1RB1_ECAM_BASE), //MemBase (PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimit PCI_HB1RB1_IO_BASE, //IoBase - (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB1_CPUIOREGIONBASE + PCI_HB1RB1_IO_SIZE - 1), //IoLimit PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB1_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB1_PCI_BASE), //RbPciBar @@ -189,7 +189,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB2_CPUMEMREGIONBASE, //MemBase PCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimit PCI_HB1RB2_IO_BASE, //IoBase - (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB2_CPUIOREGIONBASE + PCI_HB1RB2_IO_SIZE - 1), //IoLimit PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB2_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB2_PCI_BASE), //RbPciBar @@ -205,7 +205,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB1RB3_ECAM_BASE), //MemBase (PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimit PCI_HB1RB3_IO_BASE, //IoBase - (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB3_CPUIOREGIONBASE + PCI_HB1RB3_IO_SIZE - 1), //IoLimit PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB3_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB3_PCI_BASE), //RbPciBar @@ -220,7 +220,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB4_CPUMEMREGIONBASE, //MemBase PCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimit PCI_HB1RB4_IO_BASE, //IoBase - (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB4_CPUIOREGIONBASE + PCI_HB1RB4_IO_SIZE - 1), //IoLimit PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB4_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB4_PCI_BASE), //RbPciBar @@ -235,7 +235,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO PCI_HB1RB5_CPUMEMREGIONBASE, //MemBase PCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimit PCI_HB1RB5_IO_BASE, //IoBase - (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB5_CPUIOREGIONBASE + PCI_HB1RB5_IO_SIZE - 1), //IoLimit PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB5_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB5_PCI_BASE), //RbPciBar @@ -250,12 +250,12 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB1RB6_ECAM_BASE), //MemBase PCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimit PCI_HB1RB6_IO_BASE, //IoBase - (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB6_CPUIOREGIONBASE + PCI_HB1RB6_IO_SIZE - 1), //IoLimit PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB6_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB6_PCI_BASE), //RbPciBar PCI_HB1RB6_PCIREGION_BASE, //PciRegionbase - PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit + PCI_HB1RB6_PCIREGION_BASE + PCI_HB1RB6_PCIREGION_SIZE - 1 //PciRegionlimit }, /* Port 7 */ @@ -266,7 +266,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO (PCI_HB1RB7_ECAM_BASE), //MemBase PCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimit PCI_HB1RB7_IO_BASE, //IoBase - (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit + (PCI_HB1RB7_CPUIOREGIONBASE + PCI_HB1RB7_IO_SIZE - 1), //IoLimit PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase PCI_HB1RB7_CPUIOREGIONBASE, //CpuIoRegionBase (PCI_HB1RB7_PCI_BASE), //RbPciBar -- 2.17.0