From: Ming Huang <ming.huang@linaro.org>
To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org,
edk2-devel@lists.01.org, graeme.gregory@linaro.org
Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com,
wanghuiqiang@huawei.com, huangming23@huawei.com,
zhangjinsong2@huawei.com, huangdaode@hisilicon.com,
john.garry@huawei.com, Heyi Guo <heyi.guo@linaro.org>
Subject: [PATCH edk2-platforms v1 07/13] Hisilicon/PlatformPciLib: add segment for each root bridge
Date: Fri, 20 Jul 2018 16:02:36 +0800 [thread overview]
Message-ID: <20180720080242.3777-8-ming.huang@linaro.org> (raw)
In-Reply-To: <20180720080242.3777-1-ming.huang@linaro.org>
From: Heyi Guo <heyi.guo@linaro.org>
This is to prepare for switching to generic PciHostBridge driver. We
are going to create a PciHostBridgeLib instance for D0x and fetch
PCI root bridge informance from PlatformPciLib, so we add Segment to
PCI_ROOT_BRIDGE_RESOURCE_APPETURE along with other PCI resource
information. Segment numbers are kept the same as ACPI MCFG.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c | 8 ++++++++
Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 16 ++++++++++++++++
Silicon/Hisilicon/Include/Library/PlatformPciLib.h | 1 +
3 files changed, 25 insertions(+)
diff --git a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c
index c58118fe5e..3a770d17bb 100644
--- a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c
+++ b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c
@@ -28,6 +28,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
{// HostBridge 0
/* Port 0 */
{
+ 0, //Segment
PCI_HB0RB0_ECAM_BASE, //ecam
0, //BusBase
31, //BusLimit
@@ -44,6 +45,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 1 */
{
+ 1, //Segment
PCI_HB0RB1_ECAM_BASE,//ecam
224, //BusBase
254, //BusLimit
@@ -59,6 +61,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 2 */
{
+ 2, //Segment
PCI_HB0RB2_ECAM_BASE,
128, //BusBase
159, //BusLimit
@@ -75,6 +78,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
/* Port 3 */
{
+ 3, //Segment
PCI_HB0RB3_ECAM_BASE,
96, //BusBase
127, //BusLimit
@@ -92,6 +96,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
{// HostBridge 1
/* Port 0 */
{
+ 4, //Segment
PCI_HB1RB0_ECAM_BASE,
128, //BusBase
159, //BusLimit
@@ -107,6 +112,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 1 */
{
+ 5, //Segment
PCI_HB1RB1_ECAM_BASE,
160, //BusBase
191, //BusLimit
@@ -122,6 +128,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 2 */
{
+ 6, //Segment
PCI_HB1RB2_ECAM_BASE,
192, //BusBase
223, //BusLimit
@@ -138,6 +145,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
/* Port 3 */
{
+ 7, //Segment
PCI_HB1RB3_ECAM_BASE,
224, //BusBase
255, //BusLimit
diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
index c0b756ccfb..42bbdd8c98 100644
--- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
+++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
@@ -29,6 +29,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
{// HostBridge 0
/* Port 0 */
{
+ 0, //Segment
PCI_HB0RB0_ECAM_BASE, //ecam
0x80, //BusBase
0x87, //BusLimit
@@ -44,6 +45,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 1 */
{
+ 1, //Segment
PCI_HB0RB1_ECAM_BASE,//ecam
0x90, //BusBase
0x97, //BusLimit
@@ -59,6 +61,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 2 */
{
+ 2, //Segment
PCI_HB0RB2_ECAM_BASE,
0xF8, //BusBase
0xFF, //BusLimit
@@ -75,6 +78,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
/* Port 3 */
{
+ 3, //Segment
PCI_HB0RB3_ECAM_BASE,
0xb0, //BusBase
0xb7, //BusLimit
@@ -90,6 +94,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 4 */
{
+ 4, //Segment
PCI_HB0RB4_ECAM_BASE, //ecam
0x88, //BusBase
0x8f, //BusLimit
@@ -105,6 +110,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 5 */
{
+ 5, //Segment
PCI_HB0RB5_ECAM_BASE,//ecam
0x78, //BusBase
0x7F, //BusLimit
@@ -120,6 +126,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 6 */
{
+ 6, //Segment
PCI_HB0RB6_ECAM_BASE,
0xC0, //BusBase
0xC7, //BusLimit
@@ -136,6 +143,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
/* Port 7 */
{
+ 7, //Segment
PCI_HB0RB7_ECAM_BASE,
0x90, //BusBase
0x97, //BusLimit
@@ -153,6 +161,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
{// HostBridge 1
/* Port 0 */
{
+ 8, //Segment
PCI_HB1RB0_ECAM_BASE,
0x80, //BusBase
0x87, //BusLimit
@@ -168,6 +177,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 1 */
{
+ 9, //Segment
PCI_HB1RB1_ECAM_BASE,
0x90, //BusBase
0x97, //BusLimit
@@ -183,6 +193,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 2 */
{
+ 0xa, //Segment
PCI_HB1RB2_ECAM_BASE,
0x10, //BusBase
0x1f, //BusLimit
@@ -199,6 +210,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
/* Port 3 */
{
+ 0xb, //Segment
PCI_HB1RB3_ECAM_BASE,
0xb0, //BusBase
0xb7, //BusLimit
@@ -214,6 +226,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 4 */
{
+ 0xc, //Segment
PCI_HB1RB4_ECAM_BASE,
0x20, //BusBase
0x2f, //BusLimit
@@ -229,6 +242,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 5 */
{
+ 0xd, //Segment
PCI_HB1RB5_ECAM_BASE,
0x30, //BusBase
0x3f, //BusLimit
@@ -244,6 +258,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
},
/* Port 6 */
{
+ 0xe, //Segment
PCI_HB1RB6_ECAM_BASE,
0xa8, //BusBase
0xaf, //BusLimit
@@ -260,6 +275,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO
/* Port 7 */
{
+ 0xf, //Segment
PCI_HB1RB7_ECAM_BASE,
0xb8, //BusBase
0xbf, //BusLimit
diff --git a/Silicon/Hisilicon/Include/Library/PlatformPciLib.h b/Silicon/Hisilicon/Include/Library/PlatformPciLib.h
index 9d28fec375..6725a547d5 100644
--- a/Silicon/Hisilicon/Include/Library/PlatformPciLib.h
+++ b/Silicon/Hisilicon/Include/Library/PlatformPciLib.h
@@ -190,6 +190,7 @@ extern UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE];
typedef struct {
+ UINT32 Segment;
UINT64 Ecam;
UINT64 BusBase;
UINT64 BusLimit;
--
2.17.0
next prev parent reply other threads:[~2018-07-20 8:05 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-20 8:02 [PATCH edk2-platforms v1 00/13] Switching to generic PciHostBridge driver Ming Huang
2018-07-20 8:02 ` [PATCH edk2-platforms v1 01/13] Hisilicon: Enable WARN and INFO debug message Ming Huang
2018-07-20 8:02 ` [PATCH edk2-platforms v1 02/13] Hisilicon/D05/PlatformPciLib: fix misuse of macro Ming Huang
2018-07-20 8:02 ` [PATCH edk2-platforms v1 03/13] Hisilicon/Pci: Move PciPlatform to common directory Ming Huang
2018-07-20 8:02 ` [PATCH edk2-platforms v1 04/13] Hisilicon/Pci: Add two api for PciPlatform driver Ming Huang
2018-07-20 8:02 ` [PATCH edk2-platforms v1 05/13] Hisilicon/Pci: move ATU configuration to PciPlatformLib Ming Huang
2018-07-20 8:02 ` [PATCH edk2-platforms v1 06/13] Hisilicon/Pci: move EnlargeAtuConfig0() " Ming Huang
2018-07-20 8:02 ` Ming Huang [this message]
2018-07-20 8:02 ` [PATCH edk2-platforms v1 08/13] Hisilicon: add PciHostBridgeLib Ming Huang
2018-07-20 8:02 ` [PATCH edk2-platforms v1 09/13] Hisilicon: add PciCpuIo2Dxe Ming Huang
2018-07-20 10:31 ` Ard Biesheuvel
2018-07-23 1:12 ` Ming
2018-07-20 8:02 ` [PATCH edk2-platforms v1 10/13] Hisilicon: add PciSegmentLib for Hi161x Ming Huang
2018-07-20 8:02 ` [PATCH edk2-platforms v1 11/13] Hisilicon/D0x: Switch to generic PciHostBridge driver Ming Huang
2018-07-20 8:02 ` [PATCH edk2-platforms v1 12/13] Hisilicon: remove platform specific PciHostBridge Ming Huang
2018-07-20 8:02 ` [PATCH edk2-platforms v1 13/13] Hisilicon/PlatformPciLib: clear redundant felds in RESOURCE_APPETURE Ming Huang
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