From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::241; helo=mail-pl0-x241.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 857562098EAD8 for ; Fri, 20 Jul 2018 01:05:09 -0700 (PDT) Received: by mail-pl0-x241.google.com with SMTP id o7-v6so4848920plk.10 for ; Fri, 20 Jul 2018 01:05:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=mUClY3bFAbA5rWMINeAQkqU9KhlqZh2lfQKBVguGnPA=; b=J0EQHBigeP28ENLhc/rVpXNeeKGKatO2XV9uOpbnHy7q3OQ/N+tyslVQAS0UV3rI06 WmsW0S1mbMg71+rMkcfnBNEB1vj27mubbkp8oLOi27GlcxwbvxyEUv0IV8LmTqviY3Qz nPKm3RsT6XjY3g5q5CqSYUu2jQ4+inxtXW8x4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=mUClY3bFAbA5rWMINeAQkqU9KhlqZh2lfQKBVguGnPA=; b=Hl95Qq9BklOyWG95uqVTM2p2HT0Z2E51jpjLfnpfJ3ZX4+UmjG1XZ9TmU8PYCHJFWJ CqV2YW2VbYvkRaUBNszCqKPhI3T0/6i7i1uapSPazSPAO5yQcA8GX9SfkcIZRo1mJFaI Ky4dRdxy51ocFP4k9XkRi3PWWz7eV3ce0RrM0vS2+Q+FOxus7bjxgp8XBnVDryksDb4e gTLvWDxD4/T+a5ljXffJuv6Ot0NiXeyoNIlPMy7duitXqRUh3K+Uv9R37Z6pX2NTwPhk zVPZ8rChefRivHd45cBJJQaiLLZBk8jZGIf0yo8T7BIWh0OfzQYRZS3qH1b4IVzulfN2 W3JQ== X-Gm-Message-State: AOUpUlEWS13sza1HCHHV61v4JsG+oKPbt8q3eABnrmXCylAXlnPBpacD Y3AbyRIs8esCKu9X/eutFm9B8w== X-Google-Smtp-Source: AAOMgpdp7T6gNP5ECiGEJG69IP5VwH/5wjpYM4ZugM1UMFb4zrRFvq3UPoOThfTPGYf6qfRiVdZTZg== X-Received: by 2002:a17:902:e209:: with SMTP id ce9-v6mr1069898plb.233.1532073909135; Fri, 20 Jul 2018 01:05:09 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id n18-v6sm2066812pfa.50.2018.07.20.01.04.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 20 Jul 2018 01:05:08 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, Heyi Guo Date: Fri, 20 Jul 2018 16:02:36 +0800 Message-Id: <20180720080242.3777-8-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180720080242.3777-1-ming.huang@linaro.org> References: <20180720080242.3777-1-ming.huang@linaro.org> Subject: [PATCH edk2-platforms v1 07/13] Hisilicon/PlatformPciLib: add segment for each root bridge X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 20 Jul 2018 08:05:09 -0000 From: Heyi Guo This is to prepare for switching to generic PciHostBridge driver. We are going to create a PciHostBridgeLib instance for D0x and fetch PCI root bridge informance from PlatformPciLib, so we add Segment to PCI_ROOT_BRIDGE_RESOURCE_APPETURE along with other PCI resource information. Segment numbers are kept the same as ACPI MCFG. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Heyi Guo --- Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c | 8 ++++++++ Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c | 16 ++++++++++++++++ Silicon/Hisilicon/Include/Library/PlatformPciLib.h | 1 + 3 files changed, 25 insertions(+) diff --git a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c index c58118fe5e..3a770d17bb 100644 --- a/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platform/Hisilicon/D03/Library/PlatformPciLib/PlatformPciLib.c @@ -28,6 +28,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO {// HostBridge 0 /* Port 0 */ { + 0, //Segment PCI_HB0RB0_ECAM_BASE, //ecam 0, //BusBase 31, //BusLimit @@ -44,6 +45,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 1 */ { + 1, //Segment PCI_HB0RB1_ECAM_BASE,//ecam 224, //BusBase 254, //BusLimit @@ -59,6 +61,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 2 */ { + 2, //Segment PCI_HB0RB2_ECAM_BASE, 128, //BusBase 159, //BusLimit @@ -75,6 +78,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 3 */ { + 3, //Segment PCI_HB0RB3_ECAM_BASE, 96, //BusBase 127, //BusLimit @@ -92,6 +96,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO {// HostBridge 1 /* Port 0 */ { + 4, //Segment PCI_HB1RB0_ECAM_BASE, 128, //BusBase 159, //BusLimit @@ -107,6 +112,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 1 */ { + 5, //Segment PCI_HB1RB1_ECAM_BASE, 160, //BusBase 191, //BusLimit @@ -122,6 +128,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 2 */ { + 6, //Segment PCI_HB1RB2_ECAM_BASE, 192, //BusBase 223, //BusLimit @@ -138,6 +145,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 3 */ { + 7, //Segment PCI_HB1RB3_ECAM_BASE, 224, //BusBase 255, //BusLimit diff --git a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c index c0b756ccfb..42bbdd8c98 100644 --- a/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c +++ b/Platform/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c @@ -29,6 +29,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO {// HostBridge 0 /* Port 0 */ { + 0, //Segment PCI_HB0RB0_ECAM_BASE, //ecam 0x80, //BusBase 0x87, //BusLimit @@ -44,6 +45,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 1 */ { + 1, //Segment PCI_HB0RB1_ECAM_BASE,//ecam 0x90, //BusBase 0x97, //BusLimit @@ -59,6 +61,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 2 */ { + 2, //Segment PCI_HB0RB2_ECAM_BASE, 0xF8, //BusBase 0xFF, //BusLimit @@ -75,6 +78,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 3 */ { + 3, //Segment PCI_HB0RB3_ECAM_BASE, 0xb0, //BusBase 0xb7, //BusLimit @@ -90,6 +94,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 4 */ { + 4, //Segment PCI_HB0RB4_ECAM_BASE, //ecam 0x88, //BusBase 0x8f, //BusLimit @@ -105,6 +110,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 5 */ { + 5, //Segment PCI_HB0RB5_ECAM_BASE,//ecam 0x78, //BusBase 0x7F, //BusLimit @@ -120,6 +126,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 6 */ { + 6, //Segment PCI_HB0RB6_ECAM_BASE, 0xC0, //BusBase 0xC7, //BusLimit @@ -136,6 +143,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 7 */ { + 7, //Segment PCI_HB0RB7_ECAM_BASE, 0x90, //BusBase 0x97, //BusLimit @@ -153,6 +161,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO {// HostBridge 1 /* Port 0 */ { + 8, //Segment PCI_HB1RB0_ECAM_BASE, 0x80, //BusBase 0x87, //BusLimit @@ -168,6 +177,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 1 */ { + 9, //Segment PCI_HB1RB1_ECAM_BASE, 0x90, //BusBase 0x97, //BusLimit @@ -183,6 +193,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 2 */ { + 0xa, //Segment PCI_HB1RB2_ECAM_BASE, 0x10, //BusBase 0x1f, //BusLimit @@ -199,6 +210,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 3 */ { + 0xb, //Segment PCI_HB1RB3_ECAM_BASE, 0xb0, //BusBase 0xb7, //BusLimit @@ -214,6 +226,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 4 */ { + 0xc, //Segment PCI_HB1RB4_ECAM_BASE, 0x20, //BusBase 0x2f, //BusLimit @@ -229,6 +242,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 5 */ { + 0xd, //Segment PCI_HB1RB5_ECAM_BASE, 0x30, //BusBase 0x3f, //BusLimit @@ -244,6 +258,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO }, /* Port 6 */ { + 0xe, //Segment PCI_HB1RB6_ECAM_BASE, 0xa8, //BusBase 0xaf, //BusLimit @@ -260,6 +275,7 @@ PCI_ROOT_BRIDGE_RESOURCE_APPETURE mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_RO /* Port 7 */ { + 0xf, //Segment PCI_HB1RB7_ECAM_BASE, 0xb8, //BusBase 0xbf, //BusLimit diff --git a/Silicon/Hisilicon/Include/Library/PlatformPciLib.h b/Silicon/Hisilicon/Include/Library/PlatformPciLib.h index 9d28fec375..6725a547d5 100644 --- a/Silicon/Hisilicon/Include/Library/PlatformPciLib.h +++ b/Silicon/Hisilicon/Include/Library/PlatformPciLib.h @@ -190,6 +190,7 @@ extern UINT64 PCIE_ITS_1610[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE]; typedef struct { + UINT32 Segment; UINT64 Ecam; UINT64 BusBase; UINT64 BusLimit; -- 2.17.0