From: Ming Huang <ming.huang@linaro.org>
To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org,
edk2-devel@lists.01.org, graeme.gregory@linaro.org
Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com,
wanghuiqiang@huawei.com, huangming23@huawei.com,
zhangjinsong2@huawei.com, huangdaode@hisilicon.com,
john.garry@huawei.com, xinliang.liu@linaro.org,
Ming Huang <ming.huang@linaro.org>,
Heyi Guo <heyi.guo@linaro.org>,
Michael D Kinney <michael.d.kinney@intel.com>
Subject: [PATCH edk2-platforms v2 05/12] Hisilicon/Pci: move ATU configuration to PciPlatformLib
Date: Tue, 24 Jul 2018 14:32:13 +0800 [thread overview]
Message-ID: <20180724063220.61679-6-ming.huang@linaro.org> (raw)
In-Reply-To: <20180724063220.61679-1-ming.huang@linaro.org>
we move all platform specific code to platform specific module, not
in PciHostBridge driver.
This is to prepare for switching to generic PciHostBridge driver, so
This patch add Hi161xPciPlatformLib and moves ATU initialization to
Hi161xPciPlatformLib and add api PciInitPlatform for PciPlatform driver.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Ming Huang <ming.huang@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
---
Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c | 107 -----------
Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.c | 185 ++++++++++++++++++++
Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.inf | 42 +++++
3 files changed, 227 insertions(+), 107 deletions(-)
diff --git a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
index 3f894e8eec..273a322ee4 100644
--- a/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
+++ b/Silicon/Hisilicon/Drivers/PciHostBridgeDxe/PciRootBridgeIo.c
@@ -633,112 +633,6 @@ UINT64 GetPcieCfgAddress (
}
-void SetAtuConfig0RW (
- PCI_ROOT_BRIDGE_INSTANCE *Private,
- UINT32 Index
- )
-{
- UINTN RbPciBase = Private->RbPciBar;
- UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1;
- UINT64 Cfg0Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0, 0, 0);
-
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg0Base));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg0Base >> 32));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG0);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
-
- {
- UINTN i;
- for (i=0; i<0x20; i+=4) {
- DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
- }
- }
-}
-
-void SetAtuConfig1RW (
- PCI_ROOT_BRIDGE_INSTANCE *Private,
- UINT32 Index
- )
-{
- UINTN RbPciBase = Private->RbPciBar;
- UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit, 0x1F, 0x07, 0xFFF);
- UINT64 Cfg1Base = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0);
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(Cfg1Base));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(Cfg1Base >> 32));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
-
- {
- UINTN i;
- for (i=0; i<0x20; i+=4) {
- DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
- }
- }
-}
-
-void SetAtuIoRW(UINT64 RbPciBase,UINT64 IoBase,UINT64 CpuIoRegionLimit, UINT64 CpuIoRegionBase, UINT32 Index)
-{
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_IO);
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuIoRegionBase));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)CpuIoRegionBase >> 32));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuIoRegionLimit));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(IoBase));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(IoBase) >> 32));
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
-
- {
- UINTN i;
- for (i=0; i<0x20; i+=4) {
- DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
- }
- }
-}
-
-void SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT64 CpuMemRegionBase, UINT32 Index)
-{
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_MEM);
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuMemRegionBase));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(CpuMemRegionBase) >> 32));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuMemRegionLimit));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(MemBase));
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(MemBase) >> 32));
-
- MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
-
- {
- UINTN i;
- for (i=0; i<0x20; i+=4) {
- DEBUG ((EFI_D_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
- }
- }
-}
-
-VOID InitAtu (PCI_ROOT_BRIDGE_INSTANCE *Private)
-{
- SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegionLimit, Private->CpuMemRegionBase, 0);
- SetAtuConfig0RW (Private, 1);
- SetAtuConfig1RW (Private, 2);
- SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3);
-}
-
-
BOOLEAN PcieIsLinkUp (UINT32 SocType, UINTN RbPciBar, UINTN Port)
{
UINT32 Value = 0;
@@ -861,7 +755,6 @@ RootBridgeConstructor (
Protocol->SegmentNumber = Seg;
- InitAtu (PrivateData);
Status = gBS->LocateProtocol (&gEfiMetronomeArchProtocolGuid, NULL, (VOID **)&mMetronome);
if (EFI_ERROR(Status))
diff --git a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.c b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.c
new file mode 100644
index 0000000000..de26259778
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.c
@@ -0,0 +1,185 @@
+/** @file
+*
+* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciExpressLib.h>
+#include <Library/PlatformPciLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Regs/HisiPcieV1RegOffset.h>
+
+
+STATIC
+UINT64
+GetPcieCfgAddress (
+ UINT64 Ecam,
+ UINTN Bus,
+ UINTN Device,
+ UINTN Function,
+ UINTN Reg
+ )
+{
+ return Ecam + PCI_EXPRESS_LIB_ADDRESS (Bus, Device, Function, Reg);
+}
+
+STATIC
+VOID
+SetAtuConfig0RW (
+ PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private,
+ UINT32 Index
+ )
+{
+ UINTN RbPciBase = Private->RbPciBar;
+ UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 1, 1, 0, 0) - 1;
+ UINT64 MemBase = GetPcieCfgAddress (Private->Ecam, Private->BusBase, 0, 0, 0);
+
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)MemBase);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(MemBase >> 32));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG0);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
+
+ {
+ UINTN i;
+ for (i=0; i<0x20; i+=4) {
+ DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+ }
+ }
+}
+
+STATIC
+VOID
+SetAtuConfig1RW (
+ PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private,
+ UINT32 Index
+ )
+{
+ UINTN RbPciBase = Private->RbPciBar;
+ UINT64 MemLimit = GetPcieCfgAddress (Private->Ecam, Private->BusLimit + 1, 0, 0, 0) - 1;
+ UINT64 MemBase = GetPcieCfgAddress (Private->Ecam, Private->BusBase + 2, 0, 0, 0);
+
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_CONFIG1);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)MemBase);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)(MemBase >> 32));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32) MemLimit);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, 0);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, 0);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_SHIIF_MODE);
+
+ {
+ UINTN i;
+ for (i=0; i<0x20; i+=4) {
+ DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+ }
+ }
+}
+
+STATIC
+VOID
+SetAtuIoRW (UINT64 RbPciBase,UINT64 IoBase,UINT64 CpuIoRegionLimit, UINT64 CpuIoRegionBase, UINT32 Index)
+{
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_IO);
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuIoRegionBase));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)CpuIoRegionBase >> 32));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuIoRegionLimit));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(IoBase));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(IoBase) >> 32));
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
+
+ {
+ UINTN i;
+ for (i=0; i<0x20; i+=4) {
+ DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+ }
+ }
+}
+
+STATIC
+VOID
+SetAtuMemRW(UINT64 RbPciBase,UINT64 MemBase,UINT64 CpuMemRegionLimit, UINT64 CpuMemRegionBase, UINT32 Index)
+{
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_VIEW_POINT, Index);
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL1, IATU_CTRL1_TYPE_MEM);
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LOW, (UINT32)(CpuMemRegionBase));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_HIGH, (UINT32)((UINT64)(CpuMemRegionBase) >> 32));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_BASE_LIMIT, (UINT32)(CpuMemRegionLimit));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_LOW, (UINT32)(MemBase));
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_TARGET_HIGH, (UINT32)((UINT64)(MemBase) >> 32));
+
+ MmioWrite32 (RbPciBase + IATU_OFFSET + IATU_REGION_CTRL2, IATU_NORMAL_MODE);
+
+ {
+ UINTN i;
+ for (i=0; i<0x20; i+=4) {
+ DEBUG ((DEBUG_ERROR, "[%a:%d] - Base=%p value=%x\n", __FUNCTION__, __LINE__, RbPciBase + 0x900 + i, MmioRead32(RbPciBase + 0x900 + i)));
+ }
+ }
+}
+
+VOID
+InitAtu (PCI_ROOT_BRIDGE_RESOURCE_APPETURE *Private)
+{
+ SetAtuMemRW (Private->RbPciBar, Private->PciRegionBase, Private->PciRegionLimit, Private->CpuMemRegionBase, 0);
+ SetAtuConfig0RW (Private, 1);
+ SetAtuConfig1RW (Private, 2);
+ SetAtuIoRW (Private->RbPciBar, Private->IoBase, Private->IoLimit, Private->CpuIoRegionBase, 3);
+}
+
+/*++
+
+Routine Description:
+
+ Perform Platform initialization first in PciPlatform.
+
+Arguments:
+
+Returns:
+
+ VOID.
+
+--*/
+VOID
+EFIAPI
+PciInitPlatform (
+ VOID
+ )
+{
+ UINT32 Port;
+ UINT32 HostBridgeNum = 0;
+
+ for (HostBridgeNum = 0; HostBridgeNum < PCIE_MAX_HOSTBRIDGE; HostBridgeNum++) {
+ for (Port = 0; Port < PCIE_MAX_ROOTBRIDGE; Port++) {
+ InitAtu (&mResAppeture[HostBridgeNum][Port]);
+ }
+ }
+
+ return;
+}
+
diff --git a/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.inf b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.inf
new file mode 100644
index 0000000000..274cad0abf
--- /dev/null
+++ b/Silicon/Hisilicon/Hi1610/Library/Hi161xPciPlatformLib/Hi161xPciPlatformLib.inf
@@ -0,0 +1,42 @@
+## @file
+# PCI Segment Library for Hisilicon Hi1610/Hi1616 SoC with multiple RCs
+#
+# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2018, Linaro Ltd. All rights reserved.<BR>
+# Copyright (c) 2018, Hisilicon Ltd. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001A
+ BASE_NAME = Hi161xPciPlatformLib
+ FILE_GUID = 22447df4-0baa-11e8-b6de-286ed489ee9b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciPlatformLib
+
+[Sources]
+ Hi161xPciPlatformLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+ PlatformPciLib
+
+[Protocols]
+ gEfiPciHostBridgeResourceAllocationProtocolGuid
+ gEfiPciIoProtocolGuid
+ gEfiPciRootBridgeIoProtocolGuid
--
2.17.0
next prev parent reply other threads:[~2018-07-24 6:32 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-24 6:32 [PATCH edk2-platforms v2 00/12] Switching to generic PciHostBridge driver Ming Huang
2018-07-24 6:32 ` [PATCH edk2-platforms v2 01/12] Hisilicon: Enable WARN and INFO debug message Ming Huang
2018-07-24 6:32 ` [PATCH edk2-platforms v2 02/12] Hisilicon/D05/PlatformPciLib: fix misuse of macro Ming Huang
2018-07-24 6:32 ` [PATCH edk2-platforms v2 03/12] Hisilicon/Pci: Move PciPlatform to common directory Ming Huang
2018-07-24 6:32 ` [PATCH edk2-platforms v2 04/12] Hisilicon/Pci: Add two api for PciPlatform driver Ming Huang
2018-07-24 6:32 ` Ming Huang [this message]
2018-07-24 6:32 ` [PATCH edk2-platforms v2 06/12] Hisilicon/Pci: move EnlargeAtuConfig0() to PciPlatformLib Ming Huang
2018-07-24 6:32 ` [PATCH edk2-platforms v2 07/12] Hisilicon/PlatformPciLib: add segment for each root bridge Ming Huang
2018-07-24 6:32 ` [PATCH edk2-platforms v2 08/12] Hisilicon: add PciHostBridgeLib Ming Huang
2018-07-24 6:32 ` [PATCH edk2-platforms v2 09/12] Hisilicon: add PciSegmentLib for Hi161x Ming Huang
2018-07-24 6:32 ` [PATCH edk2-platforms v2 10/12] Hisilicon/D0x: Switch to generic PciHostBridge driver Ming Huang
2018-07-24 6:32 ` [PATCH edk2-platforms v2 11/12] Hisilicon: remove platform specific PciHostBridge Ming Huang
2018-07-24 6:32 ` [PATCH edk2-platforms v2 12/12] Hisilicon/PlatformPciLib: clear redundant felds in RESOURCE_APPETURE Ming Huang
2018-07-25 11:41 ` [PATCH edk2-platforms v2 00/12] Switching to generic PciHostBridge driver Ard Biesheuvel
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