From: Ming Huang <ming.huang@linaro.org>
To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org,
edk2-devel@lists.01.org, graeme.gregory@linaro.org
Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com,
wanghuiqiang@huawei.com, huangming23@huawei.com,
zhangjinsong2@huawei.com, huangdaode@hisilicon.com,
john.garry@huawei.com, xinliang.liu@linaro.org,
Sun Yuanchen <sunyuanchen@huawei.com>,
Ming Huang <ming.huang@linaro.org>,
Heyi Guo <heyi.guo@linaro.org>
Subject: [PATCH edk2-platforms v1 25/38] Hisilicon/D0x: Update SMBIOS type9 info
Date: Tue, 24 Jul 2018 15:09:09 +0800 [thread overview]
Message-ID: <20180724070922.63362-26-ming.huang@linaro.org> (raw)
In-Reply-To: <20180724070922.63362-1-ming.huang@linaro.org>
From: Sun Yuanchen <sunyuanchen@huawei.com>
Move board level code to OemMiscLibD0x for unifying D0x.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Sun Yuanchen <sunyuanchen@huawei.com>
Signed-off-by: Ming Huang <ming.huang@linaro.org>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
---
Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 24 ++++++
Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf | 1 +
Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c | 27 +++++-
Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 1 +
Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 89 ++++++++++++++++++++
Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf | 4 +
Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c | 14 +--
Silicon/Hisilicon/Include/Library/OemMiscLib.h | 1 +
8 files changed, 148 insertions(+), 13 deletions(-)
diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c
index fa1039bda1..7ca184b666 100644
--- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c
+++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c
@@ -15,6 +15,7 @@
#include <Uefi.h>
+#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/TimerLib.h>
@@ -31,6 +32,29 @@ REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
{0xFFFF,0xFFFF,0xFFFF,0xFFFF}
};
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P[PCIEDEVICE_REPORT_MAX] = {
+ {0x79,0,0,0},
+ {0xFF,0xFF,0xFF,1},
+ {0xC1,0,0,2},
+ {0xF9,0,0,3},
+ {0xFF,0xFF,0xFF,4},
+ {0x11,0,0,5},
+ {0x31,0,0,6},
+ {0x21,0,0,7}
+};
+
+VOID
+GetPciDidVid (
+ REPORT_PCIEDIDVID2BMC *Report
+ )
+{
+ if (OemIsMpBoot ()) {
+ (VOID) CopyMem ((VOID *) Report, (VOID *) PcieDeviceToReport_2P, sizeof (PcieDeviceToReport_2P));
+ } else {
+ (VOID) CopyMem ((VOID *) Report, (VOID *) PcieDeviceToReport, sizeof (PcieDeviceToReport));
+ }
+}
+
// Right now we only support 1P
BOOLEAN OemIsSocketPresent (UINTN Socket)
{
diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
index 310bbaea84..0fa7fdf80f 100644
--- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
+++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
@@ -34,6 +34,7 @@
Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses]
+ BaseMemoryLib
PcdLib
TimerLib
diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
index b17eeada16..af3982c2c0 100644
--- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
+++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
@@ -1,7 +1,7 @@
/** @file
*
-* Copyright (c) 2016, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2016, Linaro Limited. All rights reserved.
+* Copyright (c) 2016 - 2018, Hisilicon Limited. All rights reserved.
+* Copyright (c) 2016 - 2018, Linaro Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
@@ -16,6 +16,7 @@
#include <PlatformArch.h>
#include <Uefi.h>
+#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/LpcLib.h>
@@ -37,6 +38,28 @@ REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
{0xFFFF,0xFFFF,0xFFFF,0xFFFF}
};
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P[PCIEDEVICE_REPORT_MAX] = {
+ {0x79,0,0,0},
+ {0xFF,0xFF,0xFF,1},
+ {0xC1,0,0,2},
+ {0xF9,0,0,3},
+ {0xFF,0xFF,0xFF,4},
+ {0x11,0,0,5},
+ {0x31,0,0,6},
+ {0x21,0,0,7}
+};
+
+VOID
+GetPciDidVid (
+ REPORT_PCIEDIDVID2BMC *Report
+ )
+{
+ if (OemIsMpBoot ()) {
+ (VOID) CopyMem ((VOID *) Report, (VOID *) PcieDeviceToReport_2P, sizeof (PcieDeviceToReport_2P));
+ } else {
+ (VOID) CopyMem ((VOID *) Report, (VOID *) PcieDeviceToReport, sizeof (PcieDeviceToReport));
+ }
+}
BOOLEAN OemIsSocketPresent (UINTN Socket)
{
diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
index bf44ff7440..022c3e940a 100644
--- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
+++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
@@ -33,6 +33,7 @@
Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses]
+ BaseMemoryLib
PcdLib
TimerLib
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
index 009a53b2c8..f6bc3b7e6f 100644
--- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
+++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
@@ -15,6 +15,8 @@
#include <Uefi.h>
#include <PlatformArch.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/CpldD06.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
#include <Library/LpcLib.h>
@@ -33,6 +35,93 @@ REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
{0xFFFF,0xFFFF,0xFFFF,0xFFFF}
};
+//Cpu0 Riser type is (X16 + X8) & Cpu1 Riser type is (X16 + X8)
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type1 [PCIEDEVICE_REPORT_MAX] = {
+ {0x01,0,0,0},
+ {0x03,0,0,1},
+ {0xFF,0xFF,0xFF,2},
+ {0x81,0,0,3},
+ {0x84,0,0,4},
+ {0xFF,0xFF,0xFF,5}
+};
+
+//Cpu0 Riser type is (X16 + X8) & Cpu1 Riser type is (3 * X8)
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type2 [PCIEDEVICE_REPORT_MAX] = {
+ {0x01,0,0,0},
+ {0x03,0,0,1},
+ {0xFF,0xFF,0xFF,2},
+ {0xFF,0xFF,0xFF,3},
+ {0x81,0,0,4},
+ {0x85,0,0,5}
+};
+
+//Cpu0 Riser type is (3 * X8) & Cpu1 Riser type is (X16 + X8)
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type3 [PCIEDEVICE_REPORT_MAX] = {
+ {0xFF,0xFF,0xFF,0},
+ {0x01,0,0,1},
+ {0x04,0,0,2},
+ {0x81,0,0,3},
+ {0x84,0,0,4},
+ {0xFF,0xFF,0xFF,5}
+};
+
+//Cpu0 Riser type is (3 * X8) & Cpu1 Riser type is (3 * X8)
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type4 [PCIEDEVICE_REPORT_MAX] = {
+ {0xFF,0xFF,0xFF,0},
+ {0x01,0,0,1},
+ {0x04,0,0,2},
+ {0xFF,0xFF,0xFF,3},
+ {0x81,0,0,4},
+ {0x85,0,0,5}
+};
+
+VOID
+GetPciDidVid (
+ REPORT_PCIEDIDVID2BMC *Report
+ )
+{
+ UINT32 PresentSts;
+ UINT32 CardType;
+ UINT8 Cpu0CardType = 0;
+ UINT8 Cpu1CardType = 0;
+
+ PresentSts = MmioRead32 (CPLD_BASE_ADDRESS + CPLD_RISER_PRSNT_FLAG);
+ CardType = MmioRead32 (CPLD_BASE_ADDRESS + CPLD_RISER2_BOARD_ID);
+
+ // Offset 0x40: Bit7 = 1 CPU0 Riser present
+ if ((PresentSts & BIT7) != 0) {
+ Cpu0CardType = (UINT8) (PresentSts >> 8);
+ }
+
+ // Offset 0x40: Bit6 = 1 CPU1 Riser present
+ if ((PresentSts & BIT6) != 0) {
+ Cpu1CardType = (UINT8)CardType;
+ }
+
+ if (OemIsMpBoot ()) {
+ if (Cpu0CardType == CPLD_X16_X8_BOARD_ID) {
+ if (Cpu1CardType == CPLD_X16_X8_BOARD_ID) {
+ (VOID) CopyMem ((VOID *) Report, (VOID *) PcieDeviceToReport_2P_Type1,
+ sizeof (PcieDeviceToReport_2P_Type1));
+ } else {
+ (VOID) CopyMem ((VOID *) Report, (VOID *) PcieDeviceToReport_2P_Type2,
+ sizeof (PcieDeviceToReport_2P_Type2));
+ }
+ } else {
+ if (Cpu1CardType == CPLD_X16_X8_BOARD_ID) {
+ (VOID) CopyMem ((VOID *) Report, (VOID *) PcieDeviceToReport_2P_Type3,
+ sizeof (PcieDeviceToReport_2P_Type3));
+ } else {
+ (VOID) CopyMem ((VOID *) Report, (VOID *) PcieDeviceToReport_2P_Type4,
+ sizeof (PcieDeviceToReport_2P_Type4));
+ }
+ }
+ } else {
+ (VOID) CopyMem ((VOID *) Report, (VOID *) PcieDeviceToReport, sizeof (PcieDeviceToReport));
+ }
+}
+
+
// Right now we only support 1P
BOOLEAN
OemIsSocketPresent (
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
index acb7366078..9a6d06ef45 100644
--- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
+++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
@@ -30,9 +30,13 @@
ArmPkg/ArmPkg.dec
MdeModulePkg/MdeModulePkg.dec
MdePkg/MdePkg.dec
+ Platform/Hisilicon/D06/D06.dec
Silicon/Hisilicon/HisiPkg.dec
[LibraryClasses]
+ BaseMemoryLib
+ CpldIoLib
+ IoLib
PcdLib
TimerLib
SerdesLib
diff --git a/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c b/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c
index 8d8dacd3e0..cc1131577d 100644
--- a/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c
+++ b/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c
@@ -18,12 +18,6 @@
extern SMBIOS_TABLE_TYPE9 gPcieSlotInfo[];
extern UINT8 OemGetPcieSlotNumber ();
-REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P[PCIEDEVICE_REPORT_MAX] = {
- {67,0,0,0},
- {225,0,0,3},
- {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
- {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
-};
VOID
EFIAPI
UpdateSmbiosType9Info(
@@ -41,11 +35,9 @@ UpdateSmbiosType9Info(
UINTN FunctionNumber;
UINTN Index;
REPORT_PCIEDIDVID2BMC ReportPcieDidVid[PCIEDEVICE_REPORT_MAX];
- if(OemIsMpBoot()){
- (VOID)CopyMem((VOID *)ReportPcieDidVid,(VOID *)PcieDeviceToReport_2P,sizeof(PcieDeviceToReport_2P));
- } else {
- (VOID)CopyMem((VOID *)ReportPcieDidVid,(VOID *)PcieDeviceToReport,sizeof(PcieDeviceToReport));
- }
+
+ GetPciDidVid ((VOID *) ReportPcieDidVid);
+
Status = gBS->LocateHandleBuffer (
ByProtocol,
&gEfiPciIoProtocolGuid,
diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
index 517111e762..c6eb7aed1e 100644
--- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h
+++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
@@ -30,6 +30,7 @@ typedef struct _REPORT_PCIEDIDVID2BMC{
UINTN Slot;
}REPORT_PCIEDIDVID2BMC;
extern REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX];
+extern VOID GetPciDidVid (REPORT_PCIEDIDVID2BMC *Report);
BOOLEAN OemIsSocketPresent (UINTN Socket);
VOID CoreSelectBoot(VOID);
--
2.17.0
next prev parent reply other threads:[~2018-07-24 7:20 UTC|newest]
Thread overview: 153+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-24 7:08 [PATCH edk2-platforms v1 00/38] Upload for D06 platform Ming Huang
2018-07-24 7:08 ` [PATCH edk2-platforms v1 01/38] Silicon/Hisilicon: Modify the MRC interface for other module Ming Huang
2018-08-02 14:42 ` Leif Lindholm
2018-08-05 3:35 ` Ming
2018-07-24 7:08 ` [PATCH edk2-platforms v1 02/38] Silicon/Hisilicon: Separate PlatformArch.h Ming Huang
2018-08-02 14:56 ` Leif Lindholm
2018-08-05 15:11 ` Ming
2018-07-24 7:08 ` [PATCH edk2-platforms v1 03/38] Hisilicon/D06: Add several basal file for D06 Ming Huang
2018-08-02 16:14 ` Leif Lindholm
2018-08-05 15:06 ` Ming
2018-08-06 3:01 ` Ming
2018-08-06 9:57 ` Leif Lindholm
2018-07-24 7:08 ` [PATCH edk2-platforms v1 04/38] Platform/Hisilicon/D06: Add M41T83RealTimeClockLib Ming Huang
2018-08-02 16:56 ` Leif Lindholm
2018-08-08 8:02 ` Ming
2018-08-08 9:12 ` Leif Lindholm
2018-07-24 7:08 ` [PATCH edk2-platforms v1 05/38] Platform/Hisilicon/D06: Add binary file for D06 Ming Huang
2018-08-02 17:05 ` Leif Lindholm
2018-08-07 15:04 ` Ming
2018-07-24 7:08 ` [PATCH edk2-platforms v1 06/38] Hisilicon/D06: Add OemMiscLibD06 Ming Huang
2018-08-02 17:22 ` Leif Lindholm
2018-08-08 3:49 ` Ming
2018-08-08 9:43 ` Leif Lindholm
2018-07-24 7:08 ` [PATCH edk2-platforms v1 07/38] Silicon/Hisilicon/D06: Wait for all disk ready Ming Huang
2018-08-02 17:36 ` Leif Lindholm
2018-08-08 9:02 ` Ming
2018-08-08 9:59 ` Leif Lindholm
2018-08-08 11:44 ` Ming
2018-08-08 12:53 ` Leif Lindholm
2018-08-10 1:44 ` Ming
2018-08-14 15:26 ` Leif Lindholm
2018-08-15 4:01 ` Ming
2018-08-15 13:12 ` Leif Lindholm
2018-07-24 7:08 ` [PATCH edk2-platforms v1 08/38] Silicon/Hisilicon/Acpi: Unify HisiAcipPlatformDxe Ming Huang
2018-08-02 17:39 ` Leif Lindholm
2018-07-24 7:08 ` [PATCH edk2-platforms v1 09/38] Hisilicon/D06: Add Debug Serial Port Init Driver Ming Huang
2018-08-02 18:10 ` Leif Lindholm
2018-08-08 7:37 ` Ming
2018-08-08 10:01 ` Leif Lindholm
2018-08-08 14:48 ` Ming
2018-07-24 7:08 ` [PATCH edk2-platforms v1 10/38] Hisilicon/D06: Add ACPI Tables for D06 Ming Huang
2018-08-02 18:13 ` Leif Lindholm
2018-08-02 18:24 ` Ard Biesheuvel
2018-07-24 7:08 ` [PATCH edk2-platforms v1 11/38] Hisilicon/D06: Add Hi1620OemConfigUiLib Ming Huang
2018-08-03 10:24 ` Leif Lindholm
2018-08-08 12:09 ` Ming
2018-08-11 6:35 ` Ming
2018-07-24 7:08 ` [PATCH edk2-platforms v1 12/38] Silicon/Hisilicon/D06: Stop watchdog Ming Huang
2018-08-03 10:28 ` Leif Lindholm
2018-08-08 9:49 ` Ming
2018-08-03 10:31 ` Ard Biesheuvel
2018-08-09 11:40 ` Ming
2018-08-09 11:53 ` Leif Lindholm
2018-07-24 7:08 ` [PATCH edk2-platforms v1 13/38] Silicon/Hisilicon/Acpi: Move some macro to PlatformArch.h Ming Huang
2018-08-03 10:37 ` Leif Lindholm
2018-08-08 12:22 ` Ming
2018-08-08 12:57 ` Leif Lindholm
2018-07-24 7:08 ` [PATCH edk2-platforms v1 14/38] Silicon/Hisilicon/D06: Fix I2C enable fail issue for D06 Ming Huang
2018-08-03 10:40 ` Leif Lindholm
2018-08-08 14:33 ` Ming
2018-07-24 7:08 ` [PATCH edk2-platforms v1 15/38] Silicon/Hisilicon/I2C: Optimize I2C library Ming Huang
2018-08-03 13:24 ` Leif Lindholm
2018-08-08 14:41 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 16/38] Silicon/Hisilicon/D06: Add I2C delay for HNS auto config Ming Huang
2018-08-03 13:28 ` Leif Lindholm
2018-08-09 3:59 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 17/38] Silicon/Hisilicon/D06: Optimize HNS config CDR post time Ming Huang
2018-08-03 13:30 ` Leif Lindholm
2018-08-08 14:54 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 18/38] Silicon/Hisilicon/Setup: Add Setup Item "EnableGOP" Ming Huang
2018-08-03 13:32 ` Leif Lindholm
2018-08-09 0:35 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 19/38] Hisilicon/Hi1620: Add ACPI PPTT table Ming Huang
2018-08-03 13:42 ` Leif Lindholm
2018-08-09 0:52 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 20/38] Platform/Hisilicon/D06: Enable ACPI PPTT Ming Huang
2018-08-03 13:43 ` Leif Lindholm
2018-07-24 7:09 ` [PATCH edk2-platforms v1 21/38] Silicon/Hisilicon/D0x: Move macro definition to PlatformArch.h Ming Huang
2018-08-03 13:44 ` Leif Lindholm
2018-07-24 7:09 ` [PATCH edk2-platforms v1 22/38] Platform/Hisilicon/D06: Add OemNicLib Ming Huang
2018-08-03 14:36 ` Leif Lindholm
2018-08-09 6:16 ` Ming
2018-08-09 10:19 ` Leif Lindholm
2018-08-09 14:41 ` Ming
2018-08-14 2:38 ` Ming
2018-08-14 15:48 ` Leif Lindholm
2018-08-15 11:08 ` Ming
2018-08-15 13:22 ` Leif Lindholm
2018-08-15 14:16 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 23/38] Hisilicon/D0X: Rename the global variable gDS3231RtcDevice Ming Huang
2018-08-03 15:20 ` Leif Lindholm
2018-08-09 6:22 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 24/38] Platform/Hisilicon/D06: Add OemNicConfig2P Driver Ming Huang
2018-08-03 15:23 ` Leif Lindholm
2018-08-09 6:24 ` Ming
2018-07-24 7:09 ` Ming Huang [this message]
2018-08-04 9:28 ` [PATCH edk2-platforms v1 25/38] Hisilicon/D0x: Update SMBIOS type9 info Leif Lindholm
2018-08-09 6:34 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 26/38] Silicon/Hisilicon/D0x: Move macro definition to PlatformArch.h Ming Huang
2018-08-04 9:34 ` Leif Lindholm
2018-08-09 6:37 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 27/38] Platform/Hisilicon/D06: Add EarlyConfigPeim peim Ming Huang
2018-08-04 9:59 ` Leif Lindholm
2018-08-09 7:07 ` Ming
2018-08-09 10:27 ` Leif Lindholm
2018-08-09 11:54 ` Ming
2018-08-14 2:31 ` Ming
2018-08-14 15:42 ` Leif Lindholm
2018-07-24 7:09 ` [PATCH edk2-platforms v1 28/38] Hisilicon/D0x: Unify FlashFvbDxe driver Ming Huang
2018-08-04 10:06 ` Leif Lindholm
2018-08-09 7:15 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 29/38] Platform/Hisilicon/D06: Add PciHostBridgeLib Ming Huang
2018-08-04 13:41 ` Leif Lindholm
2018-08-09 7:22 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 30/38] Hisilicon/D06: add apei driver Ming Huang
2018-08-04 14:47 ` Leif Lindholm
2018-08-10 2:46 ` Ming
2018-08-14 15:39 ` Leif Lindholm
2018-08-15 8:57 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 31/38] Silicon/Hisilicon/D06: Add some Lpc macro to LpcLib.h Ming Huang
2018-08-04 14:58 ` Leif Lindholm
2018-08-09 12:02 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 32/38] Platform/Hisilicon/D06: Add capsule upgrade support Ming Huang
2018-08-04 15:08 ` Leif Lindholm
2018-07-24 7:09 ` [PATCH edk2-platforms v1 33/38] Silicon/Hisilicon/D06: Modify for close slave core clock Ming Huang
2018-08-04 15:14 ` Leif Lindholm
2018-08-09 12:15 ` Ming
2018-08-09 12:27 ` Leif Lindholm
2018-08-10 2:05 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 34/38] Silicon/Hisilicon/D06: Add I2C Bus Exception deal function Ming Huang
2018-08-04 15:18 ` Leif Lindholm
2018-08-10 2:19 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 35/38] Silicon/Hisilicon/Setup: Support SPCR table switch Ming Huang
2018-08-04 15:20 ` Leif Lindholm
2018-08-09 14:17 ` Ming
2018-08-09 14:44 ` Leif Lindholm
2018-08-09 15:40 ` Ming
2018-08-09 15:48 ` Leif Lindholm
2018-07-24 7:09 ` [PATCH edk2-platforms v1 36/38] Silicon/Hisilicon/setup: Support SMMU switch Ming Huang
2018-08-06 9:59 ` Leif Lindholm
2018-08-09 14:19 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 37/38] Hisilicon/D06: Add PciPlatformLib Ming Huang
2018-08-06 10:01 ` Leif Lindholm
2018-08-09 14:27 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 38/38] Platform/Hisilicon/D0x: Update version string to 18.08 Ming Huang
2018-08-06 10:03 ` Leif Lindholm
2018-08-09 14:29 ` Ming
2018-08-01 21:56 ` [PATCH edk2-platforms v1 00/38] Upload for D06 platform Leif Lindholm
2018-08-02 1:46 ` Ming
2018-08-02 3:17 ` 答复: " Guoheyi
2018-08-02 10:12 ` Leif Lindholm
2018-08-02 15:36 ` Graeme Gregory
2018-08-04 14:26 ` Ming
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