From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:4864:20::542; helo=mail-pg1-x542.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pg1-x542.google.com (mail-pg1-x542.google.com [IPv6:2607:f8b0:4864:20::542]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A8D1D210C1245 for ; Tue, 24 Jul 2018 00:20:44 -0700 (PDT) Received: by mail-pg1-x542.google.com with SMTP id p23-v6so2221458pgv.13 for ; Tue, 24 Jul 2018 00:20:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QWNP2vjg50y03W64ezxmvgCjAVE1+vFRe0IHUS7mAW8=; b=XdUKBRwCZ+JIeys2AvyQT4psXlVTql04GwAk0HUYVGSPgGgaqBX8HyU2akFCd6YBD0 WzqcWmo4Rek1IIfGfPcCcuRYzGBNbXOmtW06R5gXruQeB8i95NQaazVmZTwLakcfFMgX iskaXHvU2R1XkZKAUmGw9EoZC1O3LOrHIKQFI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QWNP2vjg50y03W64ezxmvgCjAVE1+vFRe0IHUS7mAW8=; b=omsW/drCQ0RjOUuOkFVLORFam+wL+PbrHxS+X4+3snq4zuwNt5/cVAVz03kug6pbpr IuTSI8HnhGP2kthwryA3tQDEDPQqm4jTpCmOm7g1Uf6PJubq3Vs9EVPPwP+hK6egivlM dC+tL87tqvWrG0iwjOgCH3Czb/dGdpiltOAelLmkiiYwtbtW6xisAYRxSjIv/KWb/uSU Vu7rQ7FLtCzDr21ueiF3hEBWcYnpGoBvazouxns9ZJfxViJNazXa9WFt8gRccUrBqhVA PFeEY7ubhm7ilgvc3AbEgdflFfp2EMwegdLJ/BXEWbMQI3evCMv2DmHW/yfP1CbIxRoT JW5Q== X-Gm-Message-State: AOUpUlFI3hH01olyxCtBob2w+xWpDbD5L76aT7Gi62QQmO8KHJ07jPwX kNYHpGDCPjCvdySJ/r7wjkZXQA== X-Google-Smtp-Source: AAOMgpevw4vbfi4DfeqRd6QO/8ETUyvvzX3R5N4S95Z08DteBGHO6oYaES5RKOf8SBjH/BBagTcD/w== X-Received: by 2002:a65:520d:: with SMTP id o13-v6mr14965981pgp.282.1532416844051; Tue, 24 Jul 2018 00:20:44 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id t14-v6sm11449788pgu.0.2018.07.24.00.20.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Jul 2018 00:20:43 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, Sun Yuanchen , Ming Huang , Heyi Guo Date: Tue, 24 Jul 2018 15:09:10 +0800 Message-Id: <20180724070922.63362-27-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180724070922.63362-1-ming.huang@linaro.org> References: <20180724070922.63362-1-ming.huang@linaro.org> MIME-Version: 1.0 Subject: [PATCH edk2-platforms v1 26/38] Silicon/Hisilicon/D0x: Move macro definition to PlatformArch.h X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jul 2018 07:20:44 -0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit From: Sun Yuanchen Move some RAS macros definition to PlatformArch.h for unifying D0x Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Sun Yuanchen Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Silicon/Hisilicon/Hi1610/Include/PlatformArch.h | 7 +++++-- Silicon/Hisilicon/Hi1616/Include/PlatformArch.h | 4 ++++ Silicon/Hisilicon/Hi1620/Include/PlatformArch.h | 8 ++++++-- 3 files changed, 15 insertions(+), 4 deletions(-) diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h index 4843b60536..5198e3efff 100644 --- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h +++ b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h @@ -1,7 +1,7 @@ /** @file * -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. +* Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2018, Linaro Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -38,6 +38,9 @@ #define S1_BASE 0x40000000000 +#define RASC_BASE (0x5000) +#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x5C) /* RASC_CFG_INFOIDX是RASC的读取Rank统计信息配置寄存器 */ +#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xB8) /* RASC_CFG_SPLVL是RASC的Sparing水线配置寄存器 */ // // ACPI table information used to initialize tables. diff --git a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h index 49618f6559..5124714cb5 100644 --- a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h +++ b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h @@ -30,6 +30,10 @@ // Max NUMA node number for each node type #define MAX_NUM_PER_TYPE 8 +#define RASC_BASE (0x5000) +#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x5C) /* RASC_CFG_INFOIDX是RASC的读取Rank统计信息配置寄存器 */ +#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xB8) /* RASC_CFG_SPLVL是RASC的Sparing水线配置寄存器 */ + // for acpi #define NODE_IN_SOCKET 2 #define CORE_NUM_PER_SOCKET 32 diff --git a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h index 2626751a0d..f2491315a8 100644 --- a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h +++ b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h @@ -1,7 +1,7 @@ /** @file * -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. -* Copyright (c) 2015, Linaro Limited. All rights reserved. +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2015 - 2018, Linaro Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -31,6 +31,10 @@ #define MAX_NUM_PER_TYPE 8 +#define RASC_BASE (0x1800) +#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x58) /* configuration register for Rank statistical information */ +#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xD4) /* configuration register for Sparing level */ + // for acpi #define NODE_IN_SOCKET 2 #define CORE_NUM_PER_SOCKET 48 -- 2.17.0