From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::243; helo=mail-pl0-x243.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x243.google.com (mail-pl0-x243.google.com [IPv6:2607:f8b0:400e:c01::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 04107210C1255 for ; Tue, 24 Jul 2018 00:22:54 -0700 (PDT) Received: by mail-pl0-x243.google.com with SMTP id b1-v6so1363561pls.5 for ; Tue, 24 Jul 2018 00:22:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Cf9DYWT+KDHlT4VhTINDV66B9bwoIBECCN+ykVSpjzs=; b=FpUzOCqHAkMuOZtGRpYPjTquP2y7RKZgsst9cP5OUY21oDz+vczyxed/i5Y3P4e4HZ o/lXJ+qb9z1+HnvhxcGrE7Z+EW+TeV/M3DKeZf4VDXSvvVrOVkzKOFs6Gu8rpiDfeJT6 Wpgdbhp6dhh5L9JQrNA+HfU2aB/8M5mVqBzX0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Cf9DYWT+KDHlT4VhTINDV66B9bwoIBECCN+ykVSpjzs=; b=lN6vSNK8u3PJMfQOPKZYbY+iS7f6zqecvWeK7zWI+hZgln92kpaLevkmz1/AujrzJG dkntMFTjYuwlhYMb9iFevFT3mY4c1Kf9Xj5y7yb5qXT66x/hOXIt57WXGRoTs4lRl43K S4J/faKUSFLe/J7PN6vtZl7NRGU34XqWStuzc1c+jwI+l6YqAsHcnsIWA/IxvPn0ub7p gsGSZF/+pCBGsthXFoo1ILr3A31h5n7fx19o8d4HYeidkT2xgs88WJQOrdTfqL7+QLuO GfAUiacT+Q+VsmWSXEDDtk0rgGS5QRRYESVLO2R5LFjA0WNR9NG2WGBwbLCp4xvbauPQ rxpA== X-Gm-Message-State: AOUpUlHT6jhktZL7JpEPJovAy/zVH9wm7O+c+QBn5xRDfe12AVsO1rLe uc9FpQ9pZUI0CHn0VfoPxVCzHw== X-Google-Smtp-Source: AAOMgpcmiNAib64h8Y9FfcG+LWNWwcm4rfK7D0JQFIDdS6JOTErYS2H0RLnKMs/FuAQMFme7SrAhgA== X-Received: by 2002:a17:902:74c2:: with SMTP id f2-v6mr15702219plt.260.1532416973737; Tue, 24 Jul 2018 00:22:53 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id t14-v6sm11449788pgu.0.2018.07.24.00.22.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 24 Jul 2018 00:22:53 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, Ming Huang , Heyi Guo Date: Tue, 24 Jul 2018 15:09:15 +0800 Message-Id: <20180724070922.63362-32-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180724070922.63362-1-ming.huang@linaro.org> References: <20180724070922.63362-1-ming.huang@linaro.org> Subject: [PATCH edk2-platforms v1 31/38] Silicon/Hisilicon/D06: Add some Lpc macro to LpcLib.h X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Jul 2018 07:22:54 -0000 Add soem Lpc macro to LpcLib.h for D06. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang Signed-off-by: Heyi Guo --- Silicon/Hisilicon/Include/Library/LpcLib.h | 51 +++++++++++++++++++- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/Silicon/Hisilicon/Include/Library/LpcLib.h b/Silicon/Hisilicon/Include/Library/LpcLib.h index 236a52ba45..5cf08ccde1 100755 --- a/Silicon/Hisilicon/Include/Library/LpcLib.h +++ b/Silicon/Hisilicon/Include/Library/LpcLib.h @@ -1,7 +1,7 @@ /** @file * -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. +* Copyright (c) 2016-2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016-2018, Linaro Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -18,6 +18,53 @@ #include +#define PCIE_SUBSYS_IOMUX 0x201100000 +#define PCIE_SUBSYS_IOMG019 (PCIE_SUBSYS_IOMUX + 0x48) +#define PCIE_SUBSYS_IOMG020 (PCIE_SUBSYS_IOMUX + 0x4C) +#define PCIE_SUBSYS_IOMG021 (PCIE_SUBSYS_IOMUX + 0x50) +#define PCIE_SUBSYS_IOMG022 (PCIE_SUBSYS_IOMUX + 0x54) +#define PCIE_SUBSYS_IOMG023 (PCIE_SUBSYS_IOMUX + 0x58) +#define PCIE_SUBSYS_IOMG024 (PCIE_SUBSYS_IOMUX + 0x5C) +#define PCIE_SUBSYS_IOMG025 (PCIE_SUBSYS_IOMUX + 0x60) +#define PCIE_SUBSYS_IOMG028 (PCIE_SUBSYS_IOMUX + 0x6C) + +#define IO_MGMT_SUBCTRL_BASE 0x201070000 +#define SC_LPC_RESET_REQ_REG (IO_MGMT_SUBCTRL_BASE + 0x0a58) +#define SC_LPC_RESET_DREQ_REG (IO_MGMT_SUBCTRL_BASE + 0x0a5c) +#define SC_LPC_SEL (IO_MGMT_SUBCTRL_BASE + 0x2400) + + +#define LPCD06_BASE 0x201190000 +#define LPC_FIRM_SPACE0_CFG (LPCD06_BASE + 0x100) +#define LPC_FIRM_SPACE1_CFG (LPCD06_BASE + 0x104) +#define LPC_FIRM_SPACE2_CFG (LPCD06_BASE + 0x108) +#define LPC_FIRM_SPACE3_CFG (LPCD06_BASE + 0x10C) +#define LPC_FIRM_SPACE4_CFG (LPCD06_BASE + 0x110) +#define LPC_FIRM_SPACE5_CFG (LPCD06_BASE + 0x114) +#define LPC_FIRM_SPACE6_CFG (LPCD06_BASE + 0x118) +#define LPC_FIRM_SPACE7_CFG (LPCD06_BASE + 0x11C) +#define LPC_MEM_SPACE0_CFG (LPCD06_BASE + 0x120) +#define LPC_MEM_SPACE1_CFG (LPCD06_BASE + 0x124) +#define LPC_MEM_SPACE2_CFG (LPCD06_BASE + 0x128) +#define LPC_MEM_SPACE3_CFG (LPCD06_BASE + 0x12C) +#define LPC_MEM_SPACE4_CFG (LPCD06_BASE + 0x130) +#define LPC_MEM_SPACE5_CFG (LPCD06_BASE + 0x134) +#define LPC_MEM_SPACE6_CFG (LPCD06_BASE + 0x138) + +#define LPCD06_START_REG (LPCD06_BASE + 0x00) +#define LPCD06_OP_STATUS_REG (LPCD06_BASE + 0x04) +#define LPCD06_IRQ_ST_REG (LPCD06_BASE + 0x08) +#define LPCD06_OP_LEN_REG (LPCD06_BASE + 0x10) +#define LPCD06_CMD_REG (LPCD06_BASE + 0x14) +#define LPCD06_ADDR_REG (LPCD06_BASE + 0x20) +#define LPCD06_WDATA_REG (LPCD06_BASE + 0x24) +#define LPCD06_RDATA_REG (LPCD06_BASE + 0x28) + +#define LPC_SIRQ_CTR0 (LPCD06_BASE + 0x80) +#define LPC_SIRQ_CTR1 (LPCD06_BASE + 0x84) +#define LPC_SIRQ_INT_MASK (LPCD06_BASE + 0x94) + + #define PCIE_SUBSYS_IO_MUX 0xA0170000 #define PCIE_SUBSYS_IOMG033 (PCIE_SUBSYS_IO_MUX + 0x84) #define PCIE_SUBSYS_IOMG035 (PCIE_SUBSYS_IO_MUX + 0x8C) -- 2.17.0