From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::443; helo=mail-wr1-x443.google.com; envelope-from=daniel.thompson@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 0755B210BFF61 for ; Thu, 26 Jul 2018 00:36:21 -0700 (PDT) Received: by mail-wr1-x443.google.com with SMTP id g6-v6so662790wrp.0 for ; Thu, 26 Jul 2018 00:36:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=tDOwUzPU4x4PixRsrjkmbYl+yJj7F2EyAhHPcutZXf8=; b=URjapyOqnRcPfEXJZYZX9KAp8nEvpG93P9Yj5JQvqXWkrI4Ur9vcun+W7E3zs7/SYc /6e8FJyrrwpo0OIcb9JZ4fZX7e8m7kI8SZQCf7g9AKeyCHj9fhS1T8qC6Jrig5Klxk1B fgkr4anqo5P14F7lbzq0EaZsfL8sG3Pb/Nf/o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=tDOwUzPU4x4PixRsrjkmbYl+yJj7F2EyAhHPcutZXf8=; b=liMmnsnlhjIH6wfz2N1GvVRZlZye+33V8C8qwQ7sdF27bKwB0ITQS+BACDZkw7sQHg GnRe2oxU+HAoEdCWY+dwhVB4VwIkfnsVVRRs/Yq1lIsbIt1TGViXlz7UoONmE44j8FvR ojmPo1KtwhFYdpsAGUvrax9ad6uE6XAfCJjw7Up0f+B4RgG1MGGTmsq2j+AmDgxg2mS5 tSFoD6XQHjHB9MpJWcmXv1AQFYuCrogLDMXmvZX8AfRX06i29J/po41gnFUxrGtdv7H+ dXJIf9QhZqphRWnIhMAGL/lvvHNpr6nvLxV0knG/TLlT1rG8O2K/OLpJL+4cnNrowQ5w vhfA== X-Gm-Message-State: AOUpUlFicOQOr6InmDZeMnDQtQL1CBxY2SszLwNP23zr9FcLHoQeKX1l Hdt+v/5XJHTWC2/zHPKZEXnN7A== X-Google-Smtp-Source: AAOMgpc72toRcZdwYKkpMOXMvo02rH/Kj0ZwhKbIL98VjLqY4GGjW0oJNO1KyedoylFIu26J7++Hiw== X-Received: by 2002:adf:9d81:: with SMTP id p1-v6mr676485wre.12.1532590580092; Thu, 26 Jul 2018 00:36:20 -0700 (PDT) Received: from holly.lan (cpc141214-aztw34-2-0-cust773.18-1.cable.virginm.net. [86.9.19.6]) by smtp.gmail.com with ESMTPSA id v10-v6sm797692wrm.18.2018.07.26.00.36.18 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 26 Jul 2018 00:36:18 -0700 (PDT) Date: Thu, 26 Jul 2018 08:36:16 +0100 From: Daniel Thompson To: Ard Biesheuvel Cc: Sumit Garg , "edk2-devel@lists.01.org" , Patch Tracking , Leif Lindholm Message-ID: <20180726073616.ut62js3w6lxsvrvf@holly.lan> References: <1532351961-17377-1-git-send-email-sumit.garg@linaro.org> MIME-Version: 1.0 In-Reply-To: User-Agent: NeoMutt/20180716 Subject: Re: [PATCH edk2-platforms v2 1/1] Silicon/SynQuacer: add optional OP-TEE DT node X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Jul 2018 07:36:22 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Jul 25, 2018 at 12:04:58PM +0200, Ard Biesheuvel wrote: > On 23 July 2018 at 15:19, Sumit Garg wrote: > > OP-TEE is optional on Developerbox controlled via SCP firmware. To check > > if we need to delete OP-TEE DT node, we use DRAM1 region info as SCP > > firmware conditionally carves out Secure memory from DRAM1 region. > > > > Cc: Ard Biesheuvel > > Cc: Leif Lindholm > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Sumit Garg > > --- > > > > As discussed on IRC, i am not a fan of inferring the presence of > OP-TEE from the base/size values of the first DRAM region. > > Please refer to the existing PCIe code how to read a GPIO in PEI and > set a dynamic PCD accordingly, so you can use its value in > PlatformDxe. For Trusted Firmware I asked Sumit to look for the OP-TEE memory carve out rather than looking at the switches. This was based on concerns about version skew (new C-A53 firmware, old SCP firmware[1]), in particular if TF-A jumps to an OP-TEE that isn't actually loaded the system will fail in a not very transparent way (especially if the user hasn't found the debug UART behind the back panel yet). What is the consequence of passing a DT with OP-TEE present if one is not actually present? Do we at least get as far as bringing up the framebuffer before things explode? Daniel. > > > Changes since v1: > > - Add support for optional OP-TEE DT node addition > > > > Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf | 3 ++ > > Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c | 33 ++++++++++++++++++++ > > Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 7 +++++ > > 3 files changed, 43 insertions(+) > > > > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf > > index 548d62fd5c0a..46cd3f85e509 100644 > > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf > > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.inf > > @@ -35,6 +35,9 @@ [LibraryClasses] > > FdtLib > > MemoryAllocationLib > > > > +[FixedPcd] > > + gSynQuacerTokenSpaceGuid.PcdDramInfoBase > > + > > [Pcd] > > gSynQuacerTokenSpaceGuid.PcdPcieEnableMask > > gSynQuacerTokenSpaceGuid.PcdPlatformSettings > > diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c > > index 897d06743708..da1209b4a613 100644 > > --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c > > +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerDtbLoaderLib/SynQuacerDtbLoaderLib.c > > @@ -19,10 +19,13 @@ > > #include > > #include > > #include > > +#include > > #include > > > > // add enough space for three instances of 'status = "disabled"' > > #define DTB_PADDING 64 > > +// base address for OP-TEE used to determine its presence > > +#define OPTEE_BASE_ADDR 0xFC000000 > > > > STATIC > > VOID > > @@ -47,6 +50,29 @@ DisableDtNode ( > > } > > } > > > > +STATIC > > +VOID > > +DeleteDtNode ( > > + IN VOID *Dtb, > > + IN CONST CHAR8 *NodePath > > + ) > > +{ > > + INT32 Node; > > + INT32 Rc; > > + > > + Node = fdt_path_offset (Dtb, NodePath); > > + if (Node < 0) { > > + DEBUG ((DEBUG_ERROR, "%a: failed to locate DT path '%a': %a\n", > > + __FUNCTION__, NodePath, fdt_strerror (Node))); > > + return; > > + } > > + Rc = fdt_del_node (Dtb, Node); > > + if (Rc < 0) { > > + DEBUG ((DEBUG_ERROR, "%a: failed to delete node on '%a': %a\n", > > + __FUNCTION__, NodePath, fdt_strerror (Rc))); > > + } > > +} > > + > > /** > > Return a pool allocated copy of the DTB image that is appropriate for > > booting the current platform via DT. > > @@ -73,6 +99,7 @@ DtPlatformLoadDtb ( > > UINTN CopyDtbSize; > > INT32 Rc; > > UINT64 SettingsVal; > > + DRAM_INFO *DramInfo; > > SYNQUACER_PLATFORM_VARSTORE_DATA *Settings; > > > > Status = GetSectionFromAnyFv (&gDtPlatformDefaultDtbFileGuid, > > @@ -107,6 +134,12 @@ DtPlatformLoadDtb ( > > DisableDtNode (CopyDtb, "/sdhci@52300000"); > > } > > > > + DramInfo = (VOID *)(UINTN)FixedPcdGet64 (PcdDramInfoBase); > > + > > + if ((DramInfo->Entry[0].Base + DramInfo->Entry[0].Size) > OPTEE_BASE_ADDR) { > > + DeleteDtNode (CopyDtb, "/firmware/optee"); > > + } > > + > > *Dtb = CopyDtb; > > *DtbSize = CopyDtbSize; > > > > diff --git a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > > index 37d642e4b237..d109a5742793 100644 > > --- a/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > > +++ b/Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi > > @@ -574,6 +574,13 @@ > > #address-cells = <1>; > > #size-cells = <0>; > > }; > > + > > + firmware { > > + optee { > > + compatible = "linaro,optee-tz"; > > + method = "smc"; > > + }; > > + }; > > }; > > > > #include "SynQuacerCaches.dtsi" > > -- > > 2.7.4 > >