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[2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id i125-v6sm4242880wmd.23.2018.08.02.13.14.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 02 Aug 2018 13:14:20 -0700 (PDT) Date: Thu, 2 Aug 2018 21:14:19 +0100 From: Leif Lindholm To: Ard Biesheuvel Cc: Marcin Wojtas , edk2-devel-01 , "Tian, Feng" , "Kinney, Michael D" , "Gao, Liming" , Nadav Haklai , "jsd@semihalf.com" Message-ID: <20180802201419.ewh3j6x2kqdq5ccn@bivouac.eciton.net> References: <1533221396-11620-1-git-send-email-mw@semihalf.com> MIME-Version: 1.0 In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH] ArmPkg/GenericWatchdogDxe: Split 64bit register write to 2x32bit X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Aug 2018 20:14:25 -0000 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit On Thu, Aug 02, 2018 at 08:32:18PM +0200, Ard Biesheuvel wrote: > On 2 August 2018 at 17:12, Marcin Wojtas wrote: > > czw., 2 sie 2018 o 16:59 Ard Biesheuvel napisał(a): > >> > >> On 2 August 2018 at 16:49, Marcin Wojtas wrote: > >> > EDK2 code uses a single 64bit write to update SBSA watchdog > >> > compare registers, however an access to mmio registers should > >> > be 32bit for some SoCs. Current usage of MmioWrite64 resulted > >> > in an unpredicted behavior. Fix this by modifying > >> > WatchdogWriteCompareRegister routine to use two consecutive > >> > 32bit writes to Watchdog Compare Register Low and High. > >> > > >> > >> You describe it as if this is generally the case, but this is just a > >> silicon bug, right? > > > > Not sure if it's a bug, or simply SoC characterisctics to place SoC > > registers to allow only mmio32 access to 32-bit registers. In any way, > > even updated routine should be fine also for the ones capable of > > mmio64 registers access. Do you have strong objections to the change? > > > > To be fair, the SBSA v5.0 does describe this register as > > 0x010-0x013 WCV[31:0] Watchdog compare value. Read/write registers > 0x014-0x017 WCV[63:32] containing the current value in the watchdog > compare register. > > so I guess it is implied that any implementation should tolerate this > value being written as 2 32-bit quantities. > > Leif? Yep, the way the SBSA describes it, these are two separate 32-bit registers, making accessing them with a single transaction ends up being implementation defined behaviour. We should maybe add separate _HIGH and _LOW #defines for the two rather than calculating register addresses inline? But apart from that: Reviewed-by: Leif Lindholm > > > >> > >> > Contributed-under: TianoCore Contribution Agreement 1.1 > >> > Signed-off-by: Marcin Wojtas > >> > --- > >> > ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c | 6 +++++- > >> > 1 file changed, 5 insertions(+), 1 deletion(-) > >> > > >> > diff --git a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c > >> > index 3180f01..b25d210 100644 > >> > --- a/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c > >> > +++ b/ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.c > >> > @@ -56,7 +56,11 @@ WatchdogWriteCompareRegister ( > >> > UINT64 Value > >> > ) > >> > { > >> > - MmioWrite64 (GENERIC_WDOG_COMPARE_VALUE_REG, Value); > >> > + MmioWrite32 (GENERIC_WDOG_COMPARE_VALUE_REG, Value & MAX_UINT32); > >> > + MmioWrite32 ( > >> > + GENERIC_WDOG_COMPARE_VALUE_REG + sizeof (UINT32), > >> > + (Value >> 32) & MAX_UINT32 > >> > + ); > >> > } > >> > > >> > VOID > >> > -- > >> > 2.7.4 > >> >