From: Leif Lindholm <leif.lindholm@linaro.org>
To: Ming Huang <ming.huang@linaro.org>
Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org,
graeme.gregory@linaro.org, ard.biesheuvel@linaro.org,
guoheyi@huawei.com, wanghuiqiang@huawei.com,
huangming23@huawei.com, zhangjinsong2@huawei.com,
huangdaode@hisilicon.com, john.garry@huawei.com,
xinliang.liu@linaro.org, Heyi Guo <heyi.guo@linaro.org>
Subject: Re: [PATCH edk2-platforms v1 19/38] Hisilicon/Hi1620: Add ACPI PPTT table
Date: Fri, 3 Aug 2018 14:42:43 +0100 [thread overview]
Message-ID: <20180803134243.ldnetoehoz6pawn7@bivouac.eciton.net> (raw)
In-Reply-To: <20180724070922.63362-20-ming.huang@linaro.org>
On Tue, Jul 24, 2018 at 03:09:03PM +0800, Ming Huang wrote:
> From: Heyi Guo <heyi.guo@linaro.org>
>
> This driver fetches information from MADT, so it is adaptable for
> partial good and 1P/2P, since MADT is updated for different
> configurations by certain mechanism.
>
> Since L2 cache is also private resource of core, so we need to set the
> next level of cache for L1I and L1D, which is important for OS to
> parse cache hierarchy.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
> Signed-off-by: Ming Huang <ming.huang@linaro.org>
> ---
> Silicon/Hisilicon/Hi1620/Pptt/Pptt.c | 543 ++++++++++++++++++++
> Silicon/Hisilicon/Hi1620/Pptt/Pptt.h | 69 +++
> Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf | 48 ++
> 3 files changed, 660 insertions(+)
>
> diff --git a/Silicon/Hisilicon/Hi1620/Pptt/Pptt.c b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.c
> new file mode 100644
> index 0000000000..944b4b9507
> --- /dev/null
> +++ b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.c
> @@ -0,0 +1,543 @@
> +/** @file
> +*
> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
> +*
> +**/
> +
> +#include "Pptt.h"
> +
> +typedef EFI_ACPI_5_1_GIC_STRUCTURE ACPI_GIC_STRUCTURE;
> +typedef EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER ACPI_MADT_TABLE_HEADER;
> +
> +EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol = NULL;
> +EFI_ACPI_SDT_PROTOCOL *mAcpiSdtProtocol = NULL;
> +
> +EFI_ACPI_DESCRIPTION_HEADER mPpttHeader =
> + ARM_ACPI_HEADER (
> + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
> + EFI_ACPI_DESCRIPTION_HEADER,
> + EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
> + );
> +
> +EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] =
> +{
> + {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, PPTT_VENDOR_ID, 0, 0, 0, 0, 0}
> +};
> +
> +EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO];
> +
> +STATIC UINT32 mSocketOffset[MAX_SOCKET];
> +STATIC UINT32 mScclOffset[MAX_SCL];
> +STATIC UINT32 mClusterOffset[MAX_SCL][MAX_CLUSTER_PER_SCL];
> +
> +STATIC
> +VOID
> +InitCacheInfo (
> + VOID
> + )
> +{
> + UINT8 Index;
> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
> + CSSELR_DATA CsselrData;
> + CCSIDR_DATA CcsidrData;
> +
> + for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
> + CsselrData.Data = 0;
> + CcsidrData.Data = 0;
> + SetMem (
> + &Type1Attributes,
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
> + 0
> + );
> +
> + if (Index == 0) { //L1I
> + CsselrData.Bits.InD = 1;
> + CsselrData.Bits.Level = 0;
> + Type1Attributes.CacheType = 1;
> + } else if (Index == 1) {
> + Type1Attributes.CacheType = 0;
> + CsselrData.Bits.Level = Index - 1;
> + } else {
> + Type1Attributes.CacheType = 2;
> + CsselrData.Bits.Level = Index - 1;
> + }
> +
> + CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
> +
> + if (CcsidrData.Bits.Wa == 1) {
> + Type1Attributes.AllocationType = EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE;
> + if (CcsidrData.Bits.Ra == 1) {
> + Type1Attributes.AllocationType = EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE;
> + }
> + }
> +
> + if (CcsidrData.Bits.Wt == 1) {
> + Type1Attributes.WritePolicy = 1;
> + }
> + DEBUG ((DEBUG_INFO,
> + "[Acpi PPTT] Level = %x!CcsidrData = %x!\n",
> + CsselrData.Bits.Level,
> + CcsidrData.Data));
> +
> + mPpttCacheType1[Index].Type = EFI_ACPI_6_2_PPTT_TYPE_CACHE;
> + mPpttCacheType1[Index].Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE);
> + mPpttCacheType1[Index].Reserved[0] = 0;
> + mPpttCacheType1[Index].Reserved[1] = 0;
> + mPpttCacheType1[Index].Flags.SizePropertyValid = 1;
> + mPpttCacheType1[Index].Flags.NumberOfSetsValid = 1;
> + mPpttCacheType1[Index].Flags.AssociativityValid = 1;
> + mPpttCacheType1[Index].Flags.AllocationTypeValid = 1;
> + mPpttCacheType1[Index].Flags.CacheTypeValid = 1;
> + mPpttCacheType1[Index].Flags.WritePolicyValid = 1;
> + mPpttCacheType1[Index].Flags.LineSizeValid = 1;
> + mPpttCacheType1[Index].Flags.Reserved = 0;
> + mPpttCacheType1[Index].NextLevelOfCache = 0;
> +
> + if (Index != PPTT_CACHE_NO - 1) {
> + mPpttCacheType1[Index].NumberOfSets = (UINT16)CcsidrData.Bits.NumSets + 1;
> + mPpttCacheType1[Index].Associativity = (UINT16)CcsidrData.Bits.Associativity + 1;
> + mPpttCacheType1[Index].LineSize = (UINT16)( 1 << (CcsidrData.Bits.LineSize + 4));
> + mPpttCacheType1[Index].Size = mPpttCacheType1[Index].LineSize * \
> + mPpttCacheType1[Index].Associativity * \
> + mPpttCacheType1[Index].NumberOfSets;
> + CopyMem (
> + &mPpttCacheType1[Index].Attributes,
> + &Type1Attributes,
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES)
> + );
> + } else {
> + // L3 cache
> + mPpttCacheType1[Index].Size = 0x2000000; // 32MB
> + mPpttCacheType1[Index].NumberOfSets = 0x800;
> + mPpttCacheType1[Index].Associativity = 0x0F; // CacheAssociativity16Way
> + SetMem (
> + &mPpttCacheType1[Index].Attributes,
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
> + 0x0A
> + );
> + mPpttCacheType1[Index].LineSize = 0x80; // 128byte
> + }
> + }
> +}
> +
> +STATIC
> +EFI_STATUS
> +AddCoreTable (
> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
> + IN OUT UINT32 *PpttTableLengthRemain,
> + IN UINT32 Parent,
> + IN UINT32 ResourceNo,
> + IN UINT32 ProcessorId
> + )
> +{
> + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0;
> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1;
> + UINT32 *PrivateResource;
> + UINT8 Index;
> + UINT32 NextLevelCacheOffset;
> +
> + if (*PpttTableLengthRemain <
> + (sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + ResourceNo * 4)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + PpttType0->Type = 0;
> + SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0);
> + PpttType0->Flags.AcpiProcessorIdValid = EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID;
> + PpttType0->Parent= Parent;
> + PpttType0->AcpiProcessorId = ProcessorId;
> + PpttType0->NumberOfPrivateResources = ResourceNo;
> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) +
> + ResourceNo * 4;
> +
> + *PpttTableLengthRemain -= (UINTN)PpttType0->Length;
> + PpttTable->Length += PpttType0->Length;
> + PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR));
> +
> + // Add cache type structure
> + for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) {
> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + *PrivateResource = PpttTable->Length;
> + PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + gBS->CopyMem (
> + PpttType1,
> + &mPpttCacheType1[Index],
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
> + );
> + *PpttTableLengthRemain -= PpttType1->Length;
> + PpttTable->Length += PpttType1->Length;
> + }
> +
> + NextLevelCacheOffset = *(PrivateResource - 1);
> + PrivateResource = (UINT32 *)(PpttType0 + 1);
> + // Set the next level to L2 for L1I and L1D
> + PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *) PpttTable + *PrivateResource++);
> + PpttType1->NextLevelOfCache = NextLevelCacheOffset;
> + PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *) PpttTable + *PrivateResource++);
> + PpttType1->NextLevelOfCache = NextLevelCacheOffset;
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +AddClusterTable (
> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
> + IN OUT UINT32 *PpttTableLengthRemain,
> + IN UINT32 Parent,
> + IN UINT32 ResourceNo
> + )
> +{
> + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0;
> +
> + if ((*PpttTableLengthRemain) <
> + (sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + ResourceNo * 4)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + PpttType0->Type = 0;
> + SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0);
> + PpttType0->Parent= Parent;
> + PpttType0->NumberOfPrivateResources = ResourceNo;
> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) +
> + ResourceNo * 4;
> +
> + *PpttTableLengthRemain -= PpttType0->Length;
> + PpttTable->Length += PpttType0->Length;
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +AddScclTable (
> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
> + IN OUT UINT32 *PpttTableLengthRemain,
> + IN UINT32 Parent,
> + IN UINT32 ResourceNo
> + )
> +{
> + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0;
> + EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *PpttType1;
> + UINT32 *PrivateResource;
> +
> + if (*PpttTableLengthRemain <
> + (sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + ResourceNo * 4)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + PpttType0->Type = 0;
> + SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0);
> + PpttType0->Parent= Parent;
> + PpttType0->NumberOfPrivateResources = ResourceNo;
> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) +
> + ResourceNo * 4;
> +
> + *PpttTableLengthRemain -= PpttType0->Length;
> + PpttTable->Length += PpttType0->Length;
> + PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR));
> +
> + // Add cache type structure
> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + *PrivateResource = PpttTable->Length;
> + PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + gBS->CopyMem (
> + PpttType1,
> + &mPpttCacheType1[3],
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
> + );
> + *PpttTableLengthRemain -= PpttType1->Length;
> + PpttTable->Length += PpttType1->Length;
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +EFI_STATUS
> +AddSocketTable (
> + IN EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
> + IN OUT UINT32 *PpttTableLengthRemain,
> + IN UINT32 Parent,
> + IN UINT32 ResourceNo
> + )
> +{
> + EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0;
> + EFI_ACPI_6_2_PPTT_STRUCTURE_ID *PpttType2;
> + UINT32 *PrivateResource;
> + UINT8 Index;
> +
> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + PpttType0->Type = 0;
> + SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0);
> + PpttType0->Flags.PhysicalPackage = EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID;
> + PpttType0->Parent= Parent;
> + PpttType0->NumberOfPrivateResources = ResourceNo;
> + PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) +
> + ResourceNo * 4;
> + PpttTable->Length += PpttType0->Length;
> +
> + *PpttTableLengthRemain -= PpttType0->Length;
> + if (*PpttTableLengthRemain < ResourceNo * 4) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR));
> + DEBUG ((DEBUG_INFO,
> + "[Acpi PPTT] sizeof(EFI_ACPI_6_2_PPTT_STRUCTURE_ID) = %x!\n",
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)));
> +
> + for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) {
> + if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)) {
> + return EFI_OUT_OF_RESOURCES;
> + }
> + *PrivateResource = PpttTable->Length;
> + PpttType2 = (EFI_ACPI_6_2_PPTT_STRUCTURE_ID *)((UINT8 *)PpttTable +
> + PpttTable->Length);
> + gBS->CopyMem (
> + PpttType2,
> + &mPpttSocketType2[Index],
> + sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)
> + );
> + *PpttTableLengthRemain -= PpttType2->Length;
> + PpttTable->Length += PpttType2->Length;
> + }
> +
> + return EFI_SUCCESS;
> +}
> +
> +STATIC
> +VOID
> +GetAffLvl (
> + IN UINT64 Mpidr,
> + IN OUT UINT8 *Level3,
> + IN OUT UINT8 *Level2,
> + IN OUT UINT8 *Level1,
> + IN OUT UINT8 *Level0
> + )
> +{
> + *Level3 = BitFieldRead64 (Mpidr, 32, 39);
> + *Level2 = BitFieldRead64 (Mpidr, 16, 23);
> + *Level1 = BitFieldRead64 (Mpidr, 8, 15);
> + *Level0 = BitFieldRead64 (Mpidr, 0, 7);
It's a bit silly that we don't have any structure definition for
MPIDR. If you feel you have the time, please submit a patch to
ArmPkg/Include/Guid/ArmMpCoreInfo.h, adding one. Or maybe two - one
for the _UP variant and one for the _MP variant. If you don't have the
time, just a note to the universe that we should do this.
> +}
> +
> +
> +STATIC
> +VOID
> +GetApic (
> + IN ACPI_MADT_TABLE_HEADER *ApicTable,
> + IN OUT EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
> + IN UINT32 PpttTableLengthRemain
> +)
> +{
> + UINT32 Parent = 0;
> + UINT32 ResourceNo = 0;
> + ACPI_GIC_STRUCTURE *Ptr;
> + UINT8 AffLvl3 = 0;
> + UINT8 AffLvl2 = 0;
> + UINT8 AffLvl1 = 0;
> + UINT8 AffLvl0 = 0;
> + UINTN SocketIndex;
> +
> + for (Ptr = (ACPI_GIC_STRUCTURE *) (ApicTable + 1);
> + (UINTN) Ptr < (UINTN) ApicTable + ApicTable->Header.Length;
> + Ptr = (ACPI_GIC_STRUCTURE *) ((UINTN) Ptr + Ptr->Length)) {
> +
> + // Avoid dead loop due to corrupted MADT
> + if (Ptr->Length == 0) {
> + DEBUG ((DEBUG_ERROR, "[%a:%d] - Invalid MADT sub structure at 0x%x\n",
> + __FUNCTION__, __LINE__, (UINTN) Ptr - (UINTN) ApicTable));
> + break;
> + }
> +
> + if (Ptr->Type != EFI_ACPI_5_1_GIC ||
> + (Ptr->Flags & EFI_ACPI_5_1_GIC_ENABLED) == 0) {
> + continue;
> + }
> + GetAffLvl (Ptr->MPIDR, &AffLvl3, &AffLvl2, &AffLvl1, &AffLvl0);
> + // AffLvl3 is not used for Hi1620
> + // And socket index is calculated by AffLvl2
> +
> + SocketIndex = AffLvl2 / MAX_SCL_PER_SOCKET;
> + if (mSocketOffset[SocketIndex] == 0) {
> + //Add socket for type0 table
> + ResourceNo = PPTT_SOCKET_COMPONENT_NO;
> + mSocketOffset[SocketIndex] = PpttTable->Length;
> + Parent = 0;
> + AddSocketTable (
> + PpttTable,
> + &PpttTableLengthRemain,
> + Parent,
> + ResourceNo
> + );
> + }
> +
> + if (mScclOffset[AffLvl2] == 0) {
> + //Add SCCL for type0 table
> + ResourceNo = 1;
> + mScclOffset[AffLvl2] = PpttTable->Length ;
> + Parent = mSocketOffset[SocketIndex];
> + AddScclTable (
> + PpttTable,
> + &PpttTableLengthRemain,
> + Parent,
> + ResourceNo
> + );
> + }
> +
> + if (mClusterOffset[AffLvl2][AffLvl1] == 0) {
> + // Add cluster for type0 table
> + // No private resource for cluster on Hi1620
> + ResourceNo = 0;
> + mClusterOffset[AffLvl2][AffLvl1] = PpttTable->Length ;
> + Parent = mScclOffset[AffLvl2];
> + AddClusterTable (
> + PpttTable,
> + &PpttTableLengthRemain,
> + Parent,
> + ResourceNo
> + );
> + }
> +
> + //Add core for type0 table
> + ResourceNo = 3;
> + Parent = mClusterOffset[AffLvl2][AffLvl1];
> + AddCoreTable (
> + PpttTable,
> + &PpttTableLengthRemain,
> + Parent,
> + ResourceNo,
> + Ptr->AcpiProcessorUid
> + );
> + }
> +}
> +
> +
> +STATIC
> +VOID
> +PpttSetAcpiTable(
> + IN EFI_EVENT Event,
> + IN VOID *Context
> + )
> +{
> + UINTN AcpiTableHandle;
> + EFI_STATUS Status;
> + UINT8 Checksum;
> + EFI_ACPI_SDT_HEADER *Table;
> + ACPI_MADT_TABLE_HEADER *ApicTable;
> + EFI_ACPI_TABLE_VERSION TableVersion;
> + EFI_ACPI_DESCRIPTION_HEADER *PpttTable;
> + UINTN TableKey;
> + UINT32 Index0;
> + UINT32 PpttTableLengthRemain = 0;
> +
> + gBS->CloseEvent (Event);
> +
> + InitCacheInfo ();
> +
> + PpttTable = (EFI_ACPI_DESCRIPTION_HEADER *)AllocateZeroPool (PPTT_TABLE_MAX_LEN);
> + gBS->CopyMem (
> + (VOID *)PpttTable,
> + &mPpttHeader,
> + sizeof (EFI_ACPI_DESCRIPTION_HEADER)
> + );
> + PpttTableLengthRemain = PPTT_TABLE_MAX_LEN - sizeof (EFI_ACPI_DESCRIPTION_HEADER);
> +
> + for (Index0 = 0; Index0 < EFI_ACPI_MAX_NUM_TABLES; Index0++) {
> + Status = mAcpiSdtProtocol->GetAcpiTable (
> + Index0,
> + &Table,
> + &TableVersion,
> + &TableKey
> + );
> + if (EFI_ERROR (Status)) {
> + break;
> + }
> +
> + // Find APIC table
> + if (Table->Signature == EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE) {
> + break;
> + }
> +
> + }
> +
> + if (!EFI_ERROR (Status) && (Index0 != EFI_ACPI_MAX_NUM_TABLES)) {
> + ApicTable = (ACPI_MADT_TABLE_HEADER *)Table;
> +
> + GetApic (ApicTable, PpttTable, PpttTableLengthRemain);
> +
> + Checksum = CalculateCheckSum8 ((UINT8 *)(PpttTable), PpttTable->Length);
> + PpttTable->Checksum = Checksum;
> +
> + AcpiTableHandle = 0;
> + Status = mAcpiTableProtocol->InstallAcpiTable (
> + mAcpiTableProtocol,
> + PpttTable,
> + PpttTable->Length,
> + &AcpiTableHandle);
> + }
> +
> + FreePool (PpttTable);
> + return ;
> +}
> +
> +EFI_STATUS
> +EFIAPI
> +PpttEntryPoint(
> + IN EFI_HANDLE ImageHandle,
> + IN EFI_SYSTEM_TABLE *SystemTable
> + )
> +{
> + EFI_STATUS Status;
> + EFI_EVENT ReadyToBootEvent;
> +
> + Status = gBS->LocateProtocol (
> + &gEfiAcpiTableProtocolGuid,
> + NULL,
> + (VOID **)&mAcpiTableProtocol);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = gBS->LocateProtocol (
> + &gEfiAcpiSdtProtocolGuid,
> + NULL,
> + (VOID **)&mAcpiSdtProtocol);
> + ASSERT_EFI_ERROR (Status);
> +
> + Status = EfiCreateEventReadyToBootEx (
> + TPL_NOTIFY,
> + PpttSetAcpiTable,
> + NULL,
> + &ReadyToBootEvent
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + DEBUG ((DEBUG_INFO, "Acpi Pptt init done.\n"));
> +
> + return Status;
> +}
> diff --git a/Silicon/Hisilicon/Hi1620/Pptt/Pptt.h b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.h
> new file mode 100644
> index 0000000000..07e4d89fed
> --- /dev/null
> +++ b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.h
> @@ -0,0 +1,69 @@
> +/** @file
> +*
> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
> +*
> +**/
> +
> +#ifndef _PPTT_H_
> +#define _PPTT_H_
> +
> +#include <PlatformArch.h>
> +#include <IndustryStandard/Acpi.h>
> +#include <Library/ArmLib/ArmLibPrivate.h>
> +#include <Library/BaseMemoryLib.h>
> +#include <Library/DebugLib.h>
> +#include <Library/MemoryAllocationLib.h>
> +#include <Library/PcdLib.h>
> +#include <Library/UefiBootServicesTableLib.h>
> +#include <Library/UefiLib.h>
> +#include <Protocol/AcpiSystemDescriptionTable.h>
> +#include <Protocol/AcpiTable.h>
> +#include "../Hi1620AcpiTables/Hi1620Platform.h"
No relative #includes.
/
Leif
> +
> +#define PPTT_VENDOR_ID SIGNATURE_32('H', 'I', 'S', 'I')
> +
> +#define EFI_ACPI_MAX_NUM_TABLES 20
> +
> +#define MAX_SCL_PER_SOCKET MAX_DIE
> +#define MAX_SCL (MAX_SOCKET * MAX_SCL_PER_SOCKET)
> +#define MAX_CLUSTER_PER_SCL 8
> +
> +#define PPTT_TABLE_MAX_LEN 0x6000
> +#define PPTT_SOCKET_COMPONENT_NO 0x1
> +#define PPTT_CACHE_NO 0x4
> +
> +typedef union {
> + struct {
> + UINT32 InD :1;
> + UINT32 Level :3;
> + UINT32 Reserved :28;
> + } Bits;
> + UINT32 Data;
> +} CSSELR_DATA;
> +
> +typedef union {
> + struct {
> + UINT32 LineSize :3;
> + UINT32 Associativity :10;
> + UINT32 NumSets :15;
> + UINT32 Wa :1;
> + UINT32 Ra :1;
> + UINT32 Wb :1;
> + UINT32 Wt :1;
> + } Bits;
> + UINT32 Data;
> +} CCSIDR_DATA;
> +
> +#endif // _PPTT_H_
> +
> diff --git a/Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf
> new file mode 100644
> index 0000000000..f8a5ed33a4
> --- /dev/null
> +++ b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf
> @@ -0,0 +1,48 @@
> +/** @file
> +*
> +* Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> +* Copyright (c) 2018, Linaro Limited. All rights reserved.
> +*
> +* This program and the accompanying materials
> +* are licensed and made available under the terms and conditions of the BSD License
> +* which accompanies this distribution. The full text of the license may be found at
> +* http://opensource.org/licenses/bsd-license.php
> +*
> +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +*
> +* Based on the files under Platform/ARM/JunoPkg/AcpiTables/
> +*
> +**/
> +
> +[Defines]
> + INF_VERSION = 0x0001001A
> + BASE_NAME = AcpiPptt
> + FILE_GUID = 65766562-49e7-11e8-817f-286ed489ee9b
> + MODULE_TYPE = DXE_DRIVER
> + VERSION_STRING = 1.0
> + ENTRY_POINT = PpttEntryPoint
> +
> +[Sources.common]
> + Pptt.c
> +
> +[Packages]
> + ArmPkg/ArmPkg.dec
> + MdePkg/MdePkg.dec
> + Silicon/Hisilicon/HisiPkg.dec
> +
> +[LibraryClasses]
> + ArmLib
> + BaseMemoryLib
> + DebugLib
> + HobLib
> + UefiDriverEntryPoint
> + UefiRuntimeServicesTableLib
> +
> +[Protocols]
> + gEfiAcpiSdtProtocolGuid ## PROTOCOL ALWAYS_CONSUMED
> + gEfiAcpiTableProtocolGuid ## PROTOCOL ALWAYS_CONSUMED
> +
> +[Depex]
> + gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid
> +
> --
> 2.17.0
>
next prev parent reply other threads:[~2018-08-03 13:42 UTC|newest]
Thread overview: 153+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-24 7:08 [PATCH edk2-platforms v1 00/38] Upload for D06 platform Ming Huang
2018-07-24 7:08 ` [PATCH edk2-platforms v1 01/38] Silicon/Hisilicon: Modify the MRC interface for other module Ming Huang
2018-08-02 14:42 ` Leif Lindholm
2018-08-05 3:35 ` Ming
2018-07-24 7:08 ` [PATCH edk2-platforms v1 02/38] Silicon/Hisilicon: Separate PlatformArch.h Ming Huang
2018-08-02 14:56 ` Leif Lindholm
2018-08-05 15:11 ` Ming
2018-07-24 7:08 ` [PATCH edk2-platforms v1 03/38] Hisilicon/D06: Add several basal file for D06 Ming Huang
2018-08-02 16:14 ` Leif Lindholm
2018-08-05 15:06 ` Ming
2018-08-06 3:01 ` Ming
2018-08-06 9:57 ` Leif Lindholm
2018-07-24 7:08 ` [PATCH edk2-platforms v1 04/38] Platform/Hisilicon/D06: Add M41T83RealTimeClockLib Ming Huang
2018-08-02 16:56 ` Leif Lindholm
2018-08-08 8:02 ` Ming
2018-08-08 9:12 ` Leif Lindholm
2018-07-24 7:08 ` [PATCH edk2-platforms v1 05/38] Platform/Hisilicon/D06: Add binary file for D06 Ming Huang
2018-08-02 17:05 ` Leif Lindholm
2018-08-07 15:04 ` Ming
2018-07-24 7:08 ` [PATCH edk2-platforms v1 06/38] Hisilicon/D06: Add OemMiscLibD06 Ming Huang
2018-08-02 17:22 ` Leif Lindholm
2018-08-08 3:49 ` Ming
2018-08-08 9:43 ` Leif Lindholm
2018-07-24 7:08 ` [PATCH edk2-platforms v1 07/38] Silicon/Hisilicon/D06: Wait for all disk ready Ming Huang
2018-08-02 17:36 ` Leif Lindholm
2018-08-08 9:02 ` Ming
2018-08-08 9:59 ` Leif Lindholm
2018-08-08 11:44 ` Ming
2018-08-08 12:53 ` Leif Lindholm
2018-08-10 1:44 ` Ming
2018-08-14 15:26 ` Leif Lindholm
2018-08-15 4:01 ` Ming
2018-08-15 13:12 ` Leif Lindholm
2018-07-24 7:08 ` [PATCH edk2-platforms v1 08/38] Silicon/Hisilicon/Acpi: Unify HisiAcipPlatformDxe Ming Huang
2018-08-02 17:39 ` Leif Lindholm
2018-07-24 7:08 ` [PATCH edk2-platforms v1 09/38] Hisilicon/D06: Add Debug Serial Port Init Driver Ming Huang
2018-08-02 18:10 ` Leif Lindholm
2018-08-08 7:37 ` Ming
2018-08-08 10:01 ` Leif Lindholm
2018-08-08 14:48 ` Ming
2018-07-24 7:08 ` [PATCH edk2-platforms v1 10/38] Hisilicon/D06: Add ACPI Tables for D06 Ming Huang
2018-08-02 18:13 ` Leif Lindholm
2018-08-02 18:24 ` Ard Biesheuvel
2018-07-24 7:08 ` [PATCH edk2-platforms v1 11/38] Hisilicon/D06: Add Hi1620OemConfigUiLib Ming Huang
2018-08-03 10:24 ` Leif Lindholm
2018-08-08 12:09 ` Ming
2018-08-11 6:35 ` Ming
2018-07-24 7:08 ` [PATCH edk2-platforms v1 12/38] Silicon/Hisilicon/D06: Stop watchdog Ming Huang
2018-08-03 10:28 ` Leif Lindholm
2018-08-08 9:49 ` Ming
2018-08-03 10:31 ` Ard Biesheuvel
2018-08-09 11:40 ` Ming
2018-08-09 11:53 ` Leif Lindholm
2018-07-24 7:08 ` [PATCH edk2-platforms v1 13/38] Silicon/Hisilicon/Acpi: Move some macro to PlatformArch.h Ming Huang
2018-08-03 10:37 ` Leif Lindholm
2018-08-08 12:22 ` Ming
2018-08-08 12:57 ` Leif Lindholm
2018-07-24 7:08 ` [PATCH edk2-platforms v1 14/38] Silicon/Hisilicon/D06: Fix I2C enable fail issue for D06 Ming Huang
2018-08-03 10:40 ` Leif Lindholm
2018-08-08 14:33 ` Ming
2018-07-24 7:08 ` [PATCH edk2-platforms v1 15/38] Silicon/Hisilicon/I2C: Optimize I2C library Ming Huang
2018-08-03 13:24 ` Leif Lindholm
2018-08-08 14:41 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 16/38] Silicon/Hisilicon/D06: Add I2C delay for HNS auto config Ming Huang
2018-08-03 13:28 ` Leif Lindholm
2018-08-09 3:59 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 17/38] Silicon/Hisilicon/D06: Optimize HNS config CDR post time Ming Huang
2018-08-03 13:30 ` Leif Lindholm
2018-08-08 14:54 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 18/38] Silicon/Hisilicon/Setup: Add Setup Item "EnableGOP" Ming Huang
2018-08-03 13:32 ` Leif Lindholm
2018-08-09 0:35 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 19/38] Hisilicon/Hi1620: Add ACPI PPTT table Ming Huang
2018-08-03 13:42 ` Leif Lindholm [this message]
2018-08-09 0:52 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 20/38] Platform/Hisilicon/D06: Enable ACPI PPTT Ming Huang
2018-08-03 13:43 ` Leif Lindholm
2018-07-24 7:09 ` [PATCH edk2-platforms v1 21/38] Silicon/Hisilicon/D0x: Move macro definition to PlatformArch.h Ming Huang
2018-08-03 13:44 ` Leif Lindholm
2018-07-24 7:09 ` [PATCH edk2-platforms v1 22/38] Platform/Hisilicon/D06: Add OemNicLib Ming Huang
2018-08-03 14:36 ` Leif Lindholm
2018-08-09 6:16 ` Ming
2018-08-09 10:19 ` Leif Lindholm
2018-08-09 14:41 ` Ming
2018-08-14 2:38 ` Ming
2018-08-14 15:48 ` Leif Lindholm
2018-08-15 11:08 ` Ming
2018-08-15 13:22 ` Leif Lindholm
2018-08-15 14:16 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 23/38] Hisilicon/D0X: Rename the global variable gDS3231RtcDevice Ming Huang
2018-08-03 15:20 ` Leif Lindholm
2018-08-09 6:22 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 24/38] Platform/Hisilicon/D06: Add OemNicConfig2P Driver Ming Huang
2018-08-03 15:23 ` Leif Lindholm
2018-08-09 6:24 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 25/38] Hisilicon/D0x: Update SMBIOS type9 info Ming Huang
2018-08-04 9:28 ` Leif Lindholm
2018-08-09 6:34 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 26/38] Silicon/Hisilicon/D0x: Move macro definition to PlatformArch.h Ming Huang
2018-08-04 9:34 ` Leif Lindholm
2018-08-09 6:37 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 27/38] Platform/Hisilicon/D06: Add EarlyConfigPeim peim Ming Huang
2018-08-04 9:59 ` Leif Lindholm
2018-08-09 7:07 ` Ming
2018-08-09 10:27 ` Leif Lindholm
2018-08-09 11:54 ` Ming
2018-08-14 2:31 ` Ming
2018-08-14 15:42 ` Leif Lindholm
2018-07-24 7:09 ` [PATCH edk2-platforms v1 28/38] Hisilicon/D0x: Unify FlashFvbDxe driver Ming Huang
2018-08-04 10:06 ` Leif Lindholm
2018-08-09 7:15 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 29/38] Platform/Hisilicon/D06: Add PciHostBridgeLib Ming Huang
2018-08-04 13:41 ` Leif Lindholm
2018-08-09 7:22 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 30/38] Hisilicon/D06: add apei driver Ming Huang
2018-08-04 14:47 ` Leif Lindholm
2018-08-10 2:46 ` Ming
2018-08-14 15:39 ` Leif Lindholm
2018-08-15 8:57 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 31/38] Silicon/Hisilicon/D06: Add some Lpc macro to LpcLib.h Ming Huang
2018-08-04 14:58 ` Leif Lindholm
2018-08-09 12:02 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 32/38] Platform/Hisilicon/D06: Add capsule upgrade support Ming Huang
2018-08-04 15:08 ` Leif Lindholm
2018-07-24 7:09 ` [PATCH edk2-platforms v1 33/38] Silicon/Hisilicon/D06: Modify for close slave core clock Ming Huang
2018-08-04 15:14 ` Leif Lindholm
2018-08-09 12:15 ` Ming
2018-08-09 12:27 ` Leif Lindholm
2018-08-10 2:05 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 34/38] Silicon/Hisilicon/D06: Add I2C Bus Exception deal function Ming Huang
2018-08-04 15:18 ` Leif Lindholm
2018-08-10 2:19 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 35/38] Silicon/Hisilicon/Setup: Support SPCR table switch Ming Huang
2018-08-04 15:20 ` Leif Lindholm
2018-08-09 14:17 ` Ming
2018-08-09 14:44 ` Leif Lindholm
2018-08-09 15:40 ` Ming
2018-08-09 15:48 ` Leif Lindholm
2018-07-24 7:09 ` [PATCH edk2-platforms v1 36/38] Silicon/Hisilicon/setup: Support SMMU switch Ming Huang
2018-08-06 9:59 ` Leif Lindholm
2018-08-09 14:19 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 37/38] Hisilicon/D06: Add PciPlatformLib Ming Huang
2018-08-06 10:01 ` Leif Lindholm
2018-08-09 14:27 ` Ming
2018-07-24 7:09 ` [PATCH edk2-platforms v1 38/38] Platform/Hisilicon/D0x: Update version string to 18.08 Ming Huang
2018-08-06 10:03 ` Leif Lindholm
2018-08-09 14:29 ` Ming
2018-08-01 21:56 ` [PATCH edk2-platforms v1 00/38] Upload for D06 platform Leif Lindholm
2018-08-02 1:46 ` Ming
2018-08-02 3:17 ` 答复: " Guoheyi
2018-08-02 10:12 ` Leif Lindholm
2018-08-02 15:36 ` Graeme Gregory
2018-08-04 14:26 ` Ming
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