From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::444; helo=mail-wr1-x444.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x444.google.com (mail-wr1-x444.google.com [IPv6:2a00:1450:4864:20::444]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5D979210D850D for ; Fri, 3 Aug 2018 06:44:50 -0700 (PDT) Received: by mail-wr1-x444.google.com with SMTP id u12-v6so5483987wrr.4 for ; Fri, 03 Aug 2018 06:44:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=SXjsPU0WcCsvAMOo1HVMYC2NWpNpfCMf1ocD8hSf6pw=; b=XqJkBEUdx+8VXa6cwxqs1t72KK/s9WsKGESqg2a2TVB69yB6v73mu9E6bkuAFf3qeR Z4fPhPR3d0DH4PzaFu2TkSlYj4F2umQ+rULh8xQA62vFWOEZfJJIsFodskghVbyUQdcq H5TKxkaSMhNvYMPRRyejyOC3Ng/RbSEZ4CRMQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=SXjsPU0WcCsvAMOo1HVMYC2NWpNpfCMf1ocD8hSf6pw=; b=SCXJCf1ZMVgDdtOtN8VVXESCWfXmV2pAEh5wfE4Ktc8Mi3E+0Om1DIIPazUssIyqp2 W+KjIV3zMtsF65OanE4nThIO3mpKcqyIT2C2OrDQunJ86MpbYV0WDH6gyTotoYyfBu/x nEI9hSZ5DpY2yIEAwHb4OCDUmdnAeaOV+Y9aznWs40VDY5vJ9TRmddyvUFsuxCBU1lZv zHzUaVgl8EXNxH11RiD1WIcpos/hLL9cdeySX7fMrtW1FxLwprfbqNj961lQThiDoiKG CCbudqwv4svIDmFx7Ne74VFX3l/5D3ArM4O+SM5LqYuWFSyYa41EPryi2QQRgl0uPz2b d/7g== X-Gm-Message-State: AOUpUlG2kGSFIiluBs3i/MR801DhNeJSFV/8Hkcg6ayLTOW5zvGm3a/s AnLtlVQOaorBLMd8eTI9ZK3ebw== X-Google-Smtp-Source: AAOMgpfbSTKhjPxEenEoytAGltqJDzWzNUdTu/m9CY+GsDbkDdaTiZZF0FoYQcypWGTPty2iri2TGw== X-Received: by 2002:adf:f188:: with SMTP id h8-v6mr2823831wro.214.1533303888870; Fri, 03 Aug 2018 06:44:48 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id a11-v6sm4447623wrr.81.2018.08.03.06.44.47 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 03 Aug 2018 06:44:47 -0700 (PDT) Date: Fri, 3 Aug 2018 14:44:46 +0100 From: Leif Lindholm To: Ming Huang Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, Sun Yuanchen , Heyi Guo Message-ID: <20180803134446.rth2wxj5unpweyx7@bivouac.eciton.net> References: <20180724070922.63362-1-ming.huang@linaro.org> <20180724070922.63362-22-ming.huang@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180724070922.63362-22-ming.huang@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v1 21/38] Silicon/Hisilicon/D0x: Move macro definition to PlatformArch.h X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 03 Aug 2018 13:44:50 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Jul 24, 2018 at 03:09:05PM +0800, Ming Huang wrote: > From: Sun Yuanchen > > Unify MemorySubClassDxe by Moving macro definition > to PlatformArch.h > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Sun Yuanchen > Signed-off-by: Ming Huang > Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm (If you drop the extra Signed-off-by:s) / Leif > --- > Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h | 2 -- > Silicon/Hisilicon/Hi1610/Include/PlatformArch.h | 1 + > Silicon/Hisilicon/Hi1616/Include/PlatformArch.h | 1 + > Silicon/Hisilicon/Hi1620/Include/PlatformArch.h | 1 + > 4 files changed, 3 insertions(+), 2 deletions(-) > > diff --git a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h > index c35ce39d61..0c201b4870 100644 > --- a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h > +++ b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h > @@ -44,8 +44,6 @@ > > extern UINT8 MemorySubClassStrings[]; > > -#define MAX_DIMM_SIZE 32 // In GB > - > struct SPD_JEDEC_MANUFACTURER > { > UINT8 MfgIdLSB; > diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h > index 03e96cfd31..4843b60536 100644 > --- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h > +++ b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h > @@ -26,6 +26,7 @@ > #define MAX_DIMM 3 > #define MAX_RANK_CH 12 > #define MAX_RANK_DIMM 4 > +#define MAX_DIMM_SIZE 32 // In GB > // Max NUMA node number for each node type > #define MAX_NUM_PER_TYPE 8 > > diff --git a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h > index 14e9b483af..49618f6559 100644 > --- a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h > +++ b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h > @@ -26,6 +26,7 @@ > #define MAX_DIMM 3 > #define MAX_RANK_CH 12 > #define MAX_RANK_DIMM 4 > +#define MAX_DIMM_SIZE 32 // In GB > // Max NUMA node number for each node type > #define MAX_NUM_PER_TYPE 8 > > diff --git a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h > index ac90e9dfb5..2626751a0d 100644 > --- a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h > +++ b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h > @@ -26,6 +26,7 @@ > #define MAX_DIMM 2 > #define MAX_RANK_CH 8 > #define MAX_RANK_DIMM 4 > +#define MAX_DIMM_SIZE 256 // In GB > // Max NUMA node number for each node type > #define MAX_NUM_PER_TYPE 8 > > -- > 2.17.0 >