From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::442; helo=mail-wr1-x442.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 50FCE210D2261 for ; Sat, 4 Aug 2018 02:34:31 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id h9-v6so7628610wro.3 for ; Sat, 04 Aug 2018 02:34:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=+lN+V83DIUg+feTOoDdm0jxiqdwHjLbzqFuvb7vcg2Y=; b=Fd1UAwxYPCvdz2McBOvV7wIOkLep545+dagwlSYEW2lULTDR0iBAflfhPlD/qFFLyv EQQnJtef9EnXWwD/10MQPf2KVhl6ot2L7+8HFv0slqPtJuIh3Pr4WAgv1AEqb8m/cojX BNy9ox7wKqgnMbJxFfZqORrCGRdNanZqIPJCw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=+lN+V83DIUg+feTOoDdm0jxiqdwHjLbzqFuvb7vcg2Y=; b=XPuEDJnd/BHPrbM/KNciwS0frASPAo8xQM0vscbvzW/rDmxmnprgI7v6y6/VIBy3aw flSP3x9iRiQNim9vJLJwMPyvT4wusWvGY7V5NA2aA85BUsja6Kl8KNIYIZRIgZ6rTEVb dxwRblj0CzIuPUYMLhwhopx8J1OIRpvyJypSYqG3AHKK+Xido2FQYzSuyTVAyuK/TYxc c0cDhnrjtfvDja93bCoyxezclVIVZ/58mVQAvdFds7nk1yb/jiM6aPOO8UAiWMWJCHeq E1V8V7cJdUQr0o4OIGCY4YvLyEPcWh2AhK+Jhsi2UnZ5CCR3JJVL0WEheFdJfjnYVlvO tzxg== X-Gm-Message-State: AOUpUlGz0oG+xhmbBHWDyD6zqPWtEzu8Lel4rIbKqPyPbVuhSj17pG4e Bw22p+NQ/avE9FoFCY6N01EYcQ== X-Google-Smtp-Source: AAOMgpcu9Sxn3sqcPo2DHRQTawQ5ZYq8X17sGAz+xS9GIlpu3tT+16aevMLWs1w0RjwW1XGoJJpH1Q== X-Received: by 2002:a5d:458b:: with SMTP id p11-v6mr4709211wrq.122.1533375270214; Sat, 04 Aug 2018 02:34:30 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id t2-v6sm4529874wrv.63.2018.08.04.02.34.28 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 04 Aug 2018 02:34:28 -0700 (PDT) Date: Sat, 4 Aug 2018 10:34:27 +0100 From: Leif Lindholm To: Ming Huang Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, Sun Yuanchen , Heyi Guo Message-ID: <20180804093427.sfcwlzmdesm7t45b@bivouac.eciton.net> References: <20180724070922.63362-1-ming.huang@linaro.org> <20180724070922.63362-27-ming.huang@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180724070922.63362-27-ming.huang@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v1 26/38] Silicon/Hisilicon/D0x: Move macro definition to PlatformArch.h X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 04 Aug 2018 09:34:32 -0000 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit On Tue, Jul 24, 2018 at 03:09:10PM +0800, Ming Huang wrote: > From: Sun Yuanchen > > Move some RAS macros definition to PlatformArch.h for > unifying D0x Minor comments below. However, I would still prefer for this to be split up into a refactoring patch for d03/d05, and then simpley introduced when the d06 files are added. / Leif > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Sun Yuanchen > Signed-off-by: Ming Huang > Signed-off-by: Heyi Guo > --- > Silicon/Hisilicon/Hi1610/Include/PlatformArch.h | 7 +++++-- > Silicon/Hisilicon/Hi1616/Include/PlatformArch.h | 4 ++++ > Silicon/Hisilicon/Hi1620/Include/PlatformArch.h | 8 ++++++-- > 3 files changed, 15 insertions(+), 4 deletions(-) > > diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h > index 4843b60536..5198e3efff 100644 > --- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h > +++ b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h > @@ -1,7 +1,7 @@ > /** @file > * > -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. > -* Copyright (c) 2015, Linaro Limited. All rights reserved. > +* Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved. > +* Copyright (c) 2015 - 2018, Linaro Limited. All rights reserved. > * > * This program and the accompanying materials > * are licensed and made available under the terms and conditions of the BSD License > @@ -38,6 +38,9 @@ > > #define S1_BASE 0x40000000000 > > +#define RASC_BASE (0x5000) > +#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x5C) /* RASC_CFG_INFOIDX??RASC?Ķ?ȡRankͳ????Ϣ???üĴ??? */ > +#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xB8) /* RASC_CFG_SPLVL??RASC??Sparingˮ?????üĴ??? */ Character encoding issues in comment. > > // > // ACPI table information used to initialize tables. > diff --git a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h > index 49618f6559..5124714cb5 100644 > --- a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h > +++ b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h > @@ -30,6 +30,10 @@ > // Max NUMA node number for each node type > #define MAX_NUM_PER_TYPE 8 > > +#define RASC_BASE (0x5000) > +#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x5C) /* RASC_CFG_INFOIDX??RASC?Ķ?ȡRankͳ????Ϣ???üĴ??? */ > +#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xB8) /* RASC_CFG_SPLVL??RASC??Sparingˮ?????üĴ??? */ > + Character encoding issues in comment. > // for acpi > #define NODE_IN_SOCKET 2 > #define CORE_NUM_PER_SOCKET 32 > diff --git a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h > index 2626751a0d..f2491315a8 100644 > --- a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h > +++ b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h > @@ -1,7 +1,7 @@ > /** @file > * > -* Copyright (c) 2015, Hisilicon Limited. All rights reserved. > -* Copyright (c) 2015, Linaro Limited. All rights reserved. > +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. > +* Copyright (c) 2015 - 2018, Linaro Limited. All rights reserved. > * > * This program and the accompanying materials > * are licensed and made available under the terms and conditions of the BSD License > @@ -31,6 +31,10 @@ > #define MAX_NUM_PER_TYPE 8 > > > +#define RASC_BASE (0x1800) > +#define RASC_CFG_INFOIDX_REG (RASC_BASE + 0x58) /* configuration register for Rank statistical information */ > +#define RASC_CFG_SPLVL_REG (RASC_BASE + 0xD4) /* configuration register for Sparing level */ > + Much nicer comments. > // for acpi > #define NODE_IN_SOCKET 2 > #define CORE_NUM_PER_SOCKET 48 > -- > 2.17.0 >