From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::443; helo=mail-wr1-x443.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x443.google.com (mail-wr1-x443.google.com [IPv6:2a00:1450:4864:20::443]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C8042210D2268 for ; Sat, 4 Aug 2018 03:06:09 -0700 (PDT) Received: by mail-wr1-x443.google.com with SMTP id h14-v6so7634878wrw.13 for ; Sat, 04 Aug 2018 03:06:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=8WEOiTgWL1pz5Y/fahZI1bT+q+Lr7lykiaBfDbEqI4g=; b=A5vbBMW61o2NDCq4aE+fY9sfb88rWBNIhqI4JLB/i9ue6oCgFMpIwTqlpjFXcwYZ7H rg23cEDGgLq35SpG0GqTPnJ5s1e9vHu965wgrbAHTCdmzeDmgyR3LhOOxjiK3CCTkRWL /ALurcrbCLyvrRJpQuh+nplv1v9nFZ8dGNe0c= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=8WEOiTgWL1pz5Y/fahZI1bT+q+Lr7lykiaBfDbEqI4g=; b=byqUrJKT+vMUOIMr/cGino8nNbl2TsSSKSQrvKVZpZsndPv+65YXcL52jO04Uv9Er9 Nmjh9xg5T129+4BFhKQmKMQiFk28HGwOiBnB38QeKMZ4KYVp+yCg+5eRcsmvg/eeK9Er 9vK+uEqeqoh5BRCKocU6QR/u0uPFmZ1N9GL9otm29zcs3floQlw8M/JQaM51yPsZN5z3 MOSBzdGTcInjnL23iAOv+Wx1+kNck6hkXZK6P2Omglkg/5zM6UcslWwRPlBfSwsOIA5b eO99XhPA4UZnCZYtjpnEdragli221ryNM2okcUqNC47qnARDud/gjrup6rAX2ZiNiPtr OvLQ== X-Gm-Message-State: AOUpUlH4Xj5BIlEMAuihPP4qfrMWZopIRQ7ipzb4QebA272ycqSX7U/h LNkV16MO1m2H8aNaPKS/CAipCw== X-Google-Smtp-Source: AAOMgpdpA9GPss0vSHEWm1TY5sBlMgiiNw1+SedQBAS/7FBlelDLYoSZYQvqrwOgx2qO7mhXIz0hKQ== X-Received: by 2002:a5d:540d:: with SMTP id g13-v6mr5030145wrv.4.1533377167685; Sat, 04 Aug 2018 03:06:07 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id c13-v6sm4989361wrt.24.2018.08.04.03.06.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 04 Aug 2018 03:06:06 -0700 (PDT) Date: Sat, 4 Aug 2018 11:06:04 +0100 From: Leif Lindholm To: Ming Huang Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, shaochangliang , Heyi Guo Message-ID: <20180804100604.bilgcrjvilmimnoc@bivouac.eciton.net> References: <20180724070922.63362-1-ming.huang@linaro.org> <20180724070922.63362-29-ming.huang@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180724070922.63362-29-ming.huang@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v1 28/38] Hisilicon/D0x: Unify FlashFvbDxe driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 04 Aug 2018 10:06:10 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Jul 24, 2018 at 03:09:12PM +0800, Ming Huang wrote: > From: shaochangliang > > Add PcdSFCMEM0BaseAddress to D06 and switch three 32-bit macro > PcdFlashNvStorage to 64-bit for D05/D03. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: shaochangliang > Signed-off-by: Ming Huang > Signed-off-by: Heyi Guo Reviewed-by: Leif Lindholm If you reorder this patch earlier in the set, I can push this change before the rest. (But I do need it rebased, since I don't think it will apply to curren HEAD, due to other changes to d03/d05?) Note: I expect this too would break D02? / Leif > --- > Platform/Hisilicon/D03/D03.fdf | 6 +++--- > Platform/Hisilicon/D05/D05.fdf | 6 +++--- > Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c | 22 ++++++++++---------- > Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf | 7 ++++--- > 4 files changed, 21 insertions(+), 20 deletions(-) > > diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf > index cf11aeccc8..5c68846a06 100644 > --- a/Platform/Hisilicon/D03/D03.fdf > +++ b/Platform/Hisilicon/D03/D03.fdf > @@ -69,7 +69,7 @@ FILE = Platform/Hisilicon/D03/bl1.bin > FILE = Platform/Hisilicon/D03/fip.bin > > 0x002D0000|0x0000E000 > -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > DATA = { > ## This is the EFI_FIRMWARE_VOLUME_HEADER > 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > @@ -97,7 +97,7 @@ DATA = { > } > > 0x002DE000|0x00002000 > -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > #NV_FTW_WORKING > DATA = { > # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = > @@ -110,7 +110,7 @@ DATA = { > } > > 0x002E0000|0x00010000 > -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > > 0x002F0000|0x00010000 > FILE = Platform/Hisilicon/D03/CustomData.Fv > diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf > index 701804360e..989e05dfcd 100644 > --- a/Platform/Hisilicon/D05/D05.fdf > +++ b/Platform/Hisilicon/D05/D05.fdf > @@ -69,7 +69,7 @@ FILE = Platform/Hisilicon/D05/bl1.bin > FILE = Platform/Hisilicon/D05/fip.bin > > 0x002D0000|0x0000E000 > -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > DATA = { > ## This is the EFI_FIRMWARE_VOLUME_HEADER > 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, > @@ -97,7 +97,7 @@ DATA = { > } > > 0x002DE000|0x00002000 > -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > #NV_FTW_WORKING > DATA = { > # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid = > @@ -110,7 +110,7 @@ DATA = { > } > > 0x002E0000|0x00010000 > -gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > > 0x002F0000|0x00010000 > FILE = Platform/Hisilicon/D03/CustomData.Fv > diff --git a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c > index 7c6b64c33e..e18cc9e06e 100644 > --- a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c > +++ b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c > @@ -28,8 +28,8 @@ FLASH_DESCRIPTION mFlashDevices[FLASH_DEVICE_COUNT] = > { > { > // UEFI Variable Services non-volatile storage > - 0xa4000000, > - FixedPcdGet32(PcdFlashNvStorageVariableBase), > + FixedPcdGet64 (PcdSFCMEM0BaseAddress), > + FixedPcdGet64 (PcdFlashNvStorageVariableBase64), > 0x20000, > SIZE_64KB, > {0xCC2CBF29, 0x1498, 0x4CDD, {0x81, 0x71, 0xF8, 0xB6, 0xB4, 0x1D, 0x09, 0x09}} > @@ -145,8 +145,8 @@ InitializeFvAndVariableStoreHeaders ( > Headers = AllocateZeroPool(HeadersLength); > > // FirmwareVolumeHeader->FvLength is declared to have the Variable area AND the FTW working area AND the FTW Spare contiguous. > - ASSERT(PcdGet32(PcdFlashNvStorageVariableBase) + PcdGet32(PcdFlashNvStorageVariableSize) == PcdGet32(PcdFlashNvStorageFtwWorkingBase)); > - ASSERT(PcdGet32(PcdFlashNvStorageFtwWorkingBase) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) == PcdGet32(PcdFlashNvStorageFtwSpareBase)); > + ASSERT(PcdGet64(PcdFlashNvStorageVariableBase64) + PcdGet32(PcdFlashNvStorageVariableSize) == PcdGet64(PcdFlashNvStorageFtwWorkingBase64)); > + ASSERT(PcdGet64(PcdFlashNvStorageFtwWorkingBase64) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) == PcdGet64(PcdFlashNvStorageFtwSpareBase64)); > > // Check if the size of the area is at least one block size > ASSERT((PcdGet32(PcdFlashNvStorageVariableSize) > 0) && ((UINT32)PcdGet32(PcdFlashNvStorageVariableSize) / Instance->Media.BlockSize > 0)); > @@ -154,9 +154,9 @@ InitializeFvAndVariableStoreHeaders ( > ASSERT((PcdGet32(PcdFlashNvStorageFtwSpareSize) > 0) && ((UINT32)PcdGet32(PcdFlashNvStorageFtwSpareSize) / Instance->Media.BlockSize > 0)); > > // Ensure the Variable area Base Addresses are aligned on a block size boundaries > - ASSERT((UINT32)PcdGet32(PcdFlashNvStorageVariableBase) % Instance->Media.BlockSize == 0); > - ASSERT((UINT32)PcdGet32(PcdFlashNvStorageFtwWorkingBase) % Instance->Media.BlockSize == 0); > - ASSERT((UINT32)PcdGet32(PcdFlashNvStorageFtwSpareBase) % Instance->Media.BlockSize == 0); > + ASSERT((UINT32)PcdGet64(PcdFlashNvStorageVariableBase64) % Instance->Media.BlockSize == 0); > + ASSERT((UINT32)PcdGet64(PcdFlashNvStorageFtwWorkingBase64) % Instance->Media.BlockSize == 0); > + ASSERT((UINT32)PcdGet64(PcdFlashNvStorageFtwSpareBase64) % Instance->Media.BlockSize == 0); > > // > // EFI_FIRMWARE_VOLUME_HEADER > @@ -855,10 +855,10 @@ FvbInitialize ( > UINT32 FvbNumLba; > > Instance->Initialized = TRUE; > - mFlashNvStorageVariableBase = FixedPcdGet32 (PcdFlashNvStorageVariableBase); > + mFlashNvStorageVariableBase = FixedPcdGet64 (PcdFlashNvStorageVariableBase64); > > // Set the index of the first LBA for the FVB > - Instance->StartLba = (PcdGet32 (PcdFlashNvStorageVariableBase) - Instance->RegionBaseAddress) / Instance->Media.BlockSize; > + Instance->StartLba = (PcdGet64 (PcdFlashNvStorageVariableBase64) - Instance->RegionBaseAddress) / Instance->Media.BlockSize; > > // Determine if there is a valid header at the beginning of the Flash > Status = ValidateFvHeader (Instance); > @@ -1208,8 +1208,8 @@ FlashFvbInitialize ( > { > // Check if this Flash device contain the variable storage region > ContainVariableStorage = > - (FlashDevices[Index].RegionBaseAddress <= (UINT32)PcdGet32 (PcdFlashNvStorageVariableBase)) && > - ((UINT32)(PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32 (PcdFlashNvStorageVariableSize)) <= FlashDevices[Index].RegionBaseAddress + FlashDevices[Index].Size); > + (FlashDevices[Index].RegionBaseAddress <= PcdGet64 (PcdFlashNvStorageVariableBase64)) && > + ((PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvStorageVariableSize)) <= FlashDevices[Index].RegionBaseAddress + FlashDevices[Index].Size); > > Status = FlashCreateInstance ( > FlashDevices[Index].DeviceBaseAddress, > diff --git a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf > index 09ec7ce08b..f8be4741ef 100644 > --- a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf > +++ b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf > @@ -54,14 +54,15 @@ > gHisiSpiFlashProtocolGuid > > [Pcd.common] > - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64 > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize > - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64 > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize > - gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase > + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64 > gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize > > gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked > + gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress > > [Depex] > gHisiSpiFlashProtocolGuid > -- > 2.17.0 >