From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::243; helo=mail-wm0-x243.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 7813B210D93C3 for ; Sat, 4 Aug 2018 06:41:49 -0700 (PDT) Received: by mail-wm0-x243.google.com with SMTP id w24-v6so9347952wmc.1 for ; Sat, 04 Aug 2018 06:41:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=YKr77mI/cLNuTE/GPBlzFzbUswDL4Jp8cKD9+141QJs=; b=bTO85jyqVFq1VhaVZfYIzamROO9jcAdNQcbDKOaHz8f4dLRED66KhRLz/H6CqyooU+ eZ1kADPKkDxphGXyH+Wc6cwsMiF23uO6hFJewigntG+vIxZ18pcAR8KdfKttx4vXKc/W fTl2Y9/uwDFiW+RcRIKJ/YYVSVPXiUUfXhQG4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=YKr77mI/cLNuTE/GPBlzFzbUswDL4Jp8cKD9+141QJs=; b=KqX2dcjzYx2U8WoZKt9Dn6twH7FKEOKc0SfvOSwx+UlgJ0/MK4SrcrQ1TiVVqCWOZT eo/epf3AayWv8LtELDZHeOXDQKRz2cwvHxGTO+3+pzzneZprAyRkvhoGWttX7F+xYKI6 iRhRCh3LtbQk5c/q7TEF+YpJQaxcmaclq38niGvNOQ0BtTbZ1wb/f8OJI2GnQ/r1kNbn r+ShmSppRFZxgt05N1Nc4/H19uzeYqm4OqOxJBKWUNqhnbDllBwnUWlVboLMeOVwxP9h zNI/BfSTC22qGnii6lpYtoEpudzVB11LzSWcJkYYynliGgY54Sr/I9l4f+NGYN7PSjLj p2Qg== X-Gm-Message-State: AOUpUlGzf2LxFFT1KqBSdRyhU9zVCLD+3UtaGMZEpFULE12LDy2na4N+ pYnHInciXK+OYUY2+PyJlufDhQ== X-Google-Smtp-Source: AAOMgpc0y0ZPGvgVs71k3xPPfnL+g8muRZXHyq58AWhMvOjzejrDPB7huX9Ps3s6ozsP+1lfaLtH8w== X-Received: by 2002:a1c:ee15:: with SMTP id m21-v6mr7550493wmh.112.1533390107213; Sat, 04 Aug 2018 06:41:47 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id a9-v6sm5611296wrp.55.2018.08.04.06.41.45 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 04 Aug 2018 06:41:45 -0700 (PDT) Date: Sat, 4 Aug 2018 14:41:44 +0100 From: Leif Lindholm To: Ming Huang Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, Heyi Guo Message-ID: <20180804134144.nqibtuefpowjcaag@bivouac.eciton.net> References: <20180724070922.63362-1-ming.huang@linaro.org> <20180724070922.63362-30-ming.huang@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180724070922.63362-30-ming.huang@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v1 29/38] Platform/Hisilicon/D06: Add PciHostBridgeLib X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 04 Aug 2018 13:41:50 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Ard: could you give this one an additional sanity check? Some (mostly style) comments inline below. On Tue, Jul 24, 2018 at 03:09:13PM +0800, Ming Huang wrote: > PciHostBridgeLib which is need by PciHostBridgeDxe,provide > root bridges and deal with resource conflict. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ming Huang > Signed-off-by: Heyi Guo > --- > Platform/Hisilicon/D06/D06.dsc | 2 +- > Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c | 636 ++++++++++++++++++++ > Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 36 ++ > 3 files changed, 673 insertions(+), 1 deletion(-) > > diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc > index 9e4f961116..28dd7926f4 100644 > --- a/Platform/Hisilicon/D06/D06.dsc > +++ b/Platform/Hisilicon/D06/D06.dsc > @@ -422,7 +422,7 @@ > > PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf > PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf > - PciHostBridgeLib|MdeModulePkg/Library/PciHostBridgeLibNull/PciHostBridgeLibNull.inf > + PciHostBridgeLib|Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf > } > > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > diff --git a/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c > new file mode 100644 > index 0000000000..24947d08e8 > --- /dev/null > +++ b/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c > @@ -0,0 +1,636 @@ > +/** @file > + > + Copyright (c) 2018, Hisilicon Limited. All rights reserved.
> + Copyright (c) 2018, Linaro Limited. All rights reserved.
> + > + This program and the accompanying materials > + are licensed and made available under the terms and conditions of the BSD License > + which accompanies this distribution. The full text of the license may be found at > + http://opensource.org/licenses/bsd-license.php > + > + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > + > +**/ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define ENUM_HB_NUM 8 > + > +#define EFI_PCI_SUPPORT (EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \ > + EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \ > + EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | \ > + EFI_PCI_ATTRIBUTE_ISA_IO_16 | \ > + EFI_PCI_ATTRIBUTE_VGA_MEMORY | \ > + EFI_PCI_ATTRIBUTE_VGA_IO_16 | \ > + EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16) > + > +#define EFI_PCI_ATTRIBUTE EFI_PCI_SUPPORT > + > +#pragma pack(1) > +typedef struct { > + ACPI_HID_DEVICE_PATH AcpiDevicePath; > + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; > +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; > +#pragma pack () > + > +STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath [ENUM_HB_NUM] = { > +//Host Bridge 0 > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), > + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) No space after (UINT8). Space after sizeof. Extra parentheses around sizeof are completely redundant - please delete. Applies throughout this patch. > + } > + }, > + EISA_PNP_ID(0x0A03), // PCI > + 0 > + }, > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + }, > + > +//Host Bridge 2 > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), > + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) > + } > + }, > + EISA_PNP_ID(0x0A04), // PCI > + 0 > + }, > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + }, > + > +//Host Bridge 4 > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), > + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) > + } > + }, > + EISA_PNP_ID(0x0A05), // PCI > + 0 > + }, > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + }, > + > +//Host Bridge 5 > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), > + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) > + } > + }, > + EISA_PNP_ID(0x0A06), // PCI > + 0 > + }, > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + }, > + > +//Host Bridge 6 > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), > + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) > + } > + }, > + EISA_PNP_ID(0x0A07), // PCI > + 0 > + }, > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + }, > + > +//Host Bridge 8 > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), > + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) > + } > + }, > + EISA_PNP_ID(0x0A08), // PCI > + 0 > + }, > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + }, > + > +//Host Bridge 10 > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), > + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) > + } > + }, > + EISA_PNP_ID(0x0A09), // PCI > + 0 > + }, > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + }, > + > +//Host Bridge 11 > + { > + { > + { > + ACPI_DEVICE_PATH, > + ACPI_DP, > + { > + (UINT8) (sizeof(ACPI_HID_DEVICE_PATH)), > + (UINT8) ((sizeof(ACPI_HID_DEVICE_PATH)) >> 8) > + } > + }, > + EISA_PNP_ID(0x0A0A), // PCI > + 0 > + }, > + { > + END_DEVICE_PATH_TYPE, > + END_ENTIRE_DEVICE_PATH_SUBTYPE, > + { > + END_DEVICE_PATH_LENGTH, > + 0 > + } > + } > + } > +}; > + > +STATIC PCI_ROOT_BRIDGE gRootBridge [ENUM_HB_NUM] = { > +//Host Bridge 0 > + { > + 0, // Segment > + EFI_PCI_SUPPORT, // Supports > + EFI_PCI_ATTRIBUTE, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, > + { // Bus > + 00, > + 0x3F > + }, > + { // Io (32K) > + 0, > + 0x7FFF > + }, > + { // Mem (256M - 64K - 1) > + 0xE0000000, > + 0xEFFEFFFF > + }, > + { // MemAbove4G (8T + 256G) > + 0x80000000000, > + 0x83FFFFFFFFF > + }, > + { // PMem > + 0xE0000000, > + 0xEFFEFFFF > + }, > + { // PMemAbove4G > + 0x80000000000, > + 0x83FFFFFFFFF > + }, > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0] > + }, > + > + //Host Bridge 2 > + { > + 0, // Segment > + EFI_PCI_SUPPORT, // Supports > + EFI_PCI_ATTRIBUTE, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, > + { // Bus > + 0x7A, > + 0x7A > + }, > + { // Io > + MAX_UINT32, > + 0 > + }, > + { // Mem > + MAX_UINT32, > + 0 > + }, > + { // MemAbove4G > + 0x20c000000, > + 0x20c1fffff > + }, > + { // PMem > + MAX_UINT32, > + 0 > + }, > + { // PMemAbove4G > + MAX_UINT64, > + 0 > + }, > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1] > + }, > + > + //Host Bridge 4 > + { > + 0, // Segment > + EFI_PCI_SUPPORT, // Supports > + EFI_PCI_ATTRIBUTE, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, > + { // Bus > + 0x7C, > + 0x7D > + }, > + { // Io > + MAX_UINT32, > + 0 > + }, > + { // Mem > + MAX_UINT32, > + 0 > + }, > + { // MemAbove4G > + 0x120000000, > + 0x13fffffff > + }, > + { // PMem > + MAX_UINT32, > + 0 > + }, > + { // PMemAbove4G > + MAX_UINT64, > + 0 > + }, > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[2] > + }, > + > + //Host Bridge 5 > + { > + 0, // Segment > + EFI_PCI_SUPPORT, // Supports > + EFI_PCI_ATTRIBUTE, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, > + { // Bus > + 0x74, > + 0x76 > + }, > + { // Io > + MAX_UINT32, > + 0 > + }, > + { // Mem > + 0xA2000000, > + 0xA2ffffff > + }, > + { // MemAbove4G > + 0x144000000, > + 0x147ffffff > + }, > + { // PMem > + MAX_UINT32, > + 0 > + }, > + { // PMemAbove4G > + MAX_UINT64, > + 0 > + }, > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[3] > + }, > + //Host Bridge 6 > + { > + 0, // Segment > + EFI_PCI_SUPPORT, // Supports > + EFI_PCI_ATTRIBUTE, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, > + { // Bus > + 0x80, > + 0x9F > + }, > + { // Io (32K) > + 0x0, > + 0x7FFF > + }, > + { // Mem (256M - 64K -1) > + 0xF0000000, > + 0xFFFEFFFF > + }, > + { // MemAbove4G (8T + 256G) > + 0x480000000000, > + 0x483FFFFFFFFF > + }, > + { // PMem > + 0xF0000000, > + 0xFFFEFFFF > + }, > + { // PMemAbove4G > + 0x480000000000, > + 0x483FFFFFFFFF > + }, > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[4] > + }, > + > + //Host Bridge 8 > + { > + 0, // Segment > + EFI_PCI_SUPPORT, // Supports > + EFI_PCI_ATTRIBUTE, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, > + { // Bus > + 0xBA, > + 0xBA > + }, > + { // Io > + MAX_UINT32, > + 0 > + }, > + { // Mem > + MAX_UINT32, > + 0 > + }, > + { // MemAbove4G > + 0x40020c000000, > + 0x40020c1fffff > + }, > + { // PMem > + MAX_UINT32, > + 0 > + }, > + { // PMemAbove4G > + MAX_UINT64, > + 0 > + }, > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[5] > + }, > + > + //Host Bridge 10 > + { > + 0, // Segment > + EFI_PCI_SUPPORT, // Supports > + EFI_PCI_ATTRIBUTE, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, > + { // Bus > + 0xBC, > + 0xBD > + }, > + { // Io > + MAX_UINT32, > + 0 > + }, > + { // Mem > + MAX_UINT32, > + 0 > + }, > + { // MemAbove4G > + 0x400120000000, > + 0x40013fffffff > + }, > + { // PMem > + MAX_UINT32, > + 0 > + }, > + { // PMemAbove4G > + MAX_UINT64, > + 0 > + }, > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[6] > + }, > + > + //Host Bridge 11 > + { > + 0, // Segment > + EFI_PCI_SUPPORT, // Supports > + EFI_PCI_ATTRIBUTE, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, > + { // Bus > + 0xB4, > + 0xB6 > + }, > + { // Io > + MAX_UINT32, > + 0 > + }, > + { // Mem > + 0xA3000000, > + 0xA3ffffff > + }, > + { // MemAbove4G > + 0x400144000000, > + 0x400147ffffff > + }, > + { // PMem > + MAX_UINT32, > + 0 > + }, > + { // PMemAbove4G > + MAX_UINT64, > + 0 > + }, > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[7] > + } > + > +}; > + > +/** > + Return all the root bridge instances in an array. > + > + @param Count Return the count of root bridge instances. > + > + @return All the root bridge instances in an array. > + The array should be passed into PciHostBridgeFreeRootBridges() > + when it's not used. > +**/ > +PCI_ROOT_BRIDGE * > +EFIAPI > +PciHostBridgeGetRootBridges ( > + UINTN *Count > + ) > +{ > + *Count = ENUM_HB_NUM; > + > + return gRootBridge; > +} > + > +/** > + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). > + > + @param Bridges The root bridge instances array. > + @param Count The count of the array. > +**/ > +VOID > +EFIAPI > +PciHostBridgeFreeRootBridges ( > + PCI_ROOT_BRIDGE *Bridges, > + UINTN Count > + ) > +{ > + if (Bridges == NULL && Count == 0) { > + return; > + } > + ASSERT (Bridges != NULL && Count > 0); We don't need to try to figure out whether the compiler is broken. Either move that assert into the if statement or delete it. > + > + do { > + --Count; > + FreePool (Bridges[Count].DevicePath); > + } while (Count > 0); > + > + FreePool (Bridges); > +} > + > +STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = { > + L"Mem", L"I/O", L"Bus" > +}; > + > +/** > + Inform the platform that the resource conflict happens. > + > + @param HostBridgeHandle Handle of the Host Bridge. > + @param Configuration Pointer to PCI I/O and PCI memory resource > + descriptors. The Configuration contains the resources > + for all the root bridges. The resource for each root > + bridge is terminated with END descriptor and an > + additional END is appended indicating the end of the > + entire resources. The resource descriptor field > + values follow the description in > + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL > + .SubmitResources(). > +**/ > +VOID > +EFIAPI > +PciHostBridgeResourceConflict ( > + EFI_HANDLE HostBridgeHandle, > + VOID *Configuration > + ) > +{ > + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; > + UINTN RootBridgeIndex; > + > + DEBUG ((DEBUG_ERROR, "\n PciHostBridge: Resource conflict happens!\n")); > + RootBridgeIndex = 0; > + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration; > + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { > + DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++)); > + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { > + ASSERT (Descriptor->ResType < > + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr) > + ); > + DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n", > + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], > + Descriptor->AddrLen, Descriptor->AddrRangeMax > + )); > + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { > + DEBUG ((DEBUG_ERROR, " Granularity/SpecificFlag = %ld / %02x%s\n", > + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, > + ((Descriptor->SpecificFlag & > + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE > + ) != 0) ? L" (Prefetchable)" : L"" > + )); > + } > + } > + // > + // Skip the END descriptor for root bridge > + // > + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); > + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( > + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 > + ); > + } > +} > diff --git a/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf > new file mode 100644 > index 0000000000..010015d3cd > --- /dev/null > +++ b/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf > @@ -0,0 +1,36 @@ > +## @file > +# > +# Copyright (c) 2016, Hisilicon Limited. All rights reserved.
> +# Copyright (c) 2016, Linaro Limited. All rights reserved.
Bump copyright year(s)? / Leif > +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > +# > +## > + > +[Defines] > + INF_VERSION = 0x0001001A > + BASE_NAME = PciHostBridgeLib > + FILE_GUID = 61b7276a-fc67-11e5-82fd-47ea9896dd5d > + MODULE_TYPE = DXE_DRIVER > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER > + > +[Sources] > + PciHostBridgeLib.c > + > +[Packages] > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + > +[LibraryClasses] > + BaseLib > + DebugLib > + DevicePathLib > + MemoryAllocationLib > + UefiBootServicesTableLib > -- > 2.17.0 >