From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id EECC021A00AE6 for ; Sat, 4 Aug 2018 07:58:17 -0700 (PDT) Received: by mail-wm0-x241.google.com with SMTP id c14-v6so9253339wmb.4 for ; Sat, 04 Aug 2018 07:58:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=391pv/0H0TiP97vpRPC8SmMeLpVPSeZceGg39EzSCXU=; b=QFlQbfFo/Mos9ml5YgKbhdugG3jNFFPkIQ+IE06eyx5sHxSyA8/VaUXi1DBwrLOxAu 1pN9denjVbasVuBm5wUj1bDWcfmOhlJrU4W1AHMOgzk+BHSxQuPh+17a4EyesJM/hI4Y q0IDOvT48v0lRrtjrmY+rMkbIUQOpaBGbB4PI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=391pv/0H0TiP97vpRPC8SmMeLpVPSeZceGg39EzSCXU=; b=l9J16L3uaQ6H9dBiCuGQ30399gkqLyjqOUkW+heL0N5JMbnMn4dzDyM9zfuWFX9Hbk 6Ce7SnyMVtVDJ1wbvpAOeiMZflESRg0wBXvMvI6H0R6BeVVL50oNbGmYhwIv2xhwyHcJ Rot8IC416Hik5/qMNZrhc4jEktsAkIDy8WpyXxyb70+NY/67AR0e9OrSYEwSvc8QIlQQ frNp8GwbZwPeVrBn7+lgpUjXfHWq+xs0LLEJHJ3G2PG/HrQK+Cnm8AsFj3w8WJ9JQ4Oe ndJ2d5zdilbzNM0zumsMbdplw4Kj7fyuKUekFeLUo9ANYN0OQ82heEpstmm7jfGnUo2H X21A== X-Gm-Message-State: AOUpUlEFQIWF+ZwB+SPCXlQQpdzKUsicjQ4/P8fH6ZttCQRP/PJiYvET 9Ueh8ErGp+8PJN4jZ1ptHyPnXA== X-Google-Smtp-Source: AAOMgpfa07X+4jIEroDg6zgO5MTofg4dhZbJQeKvOVrJXwuJYebVX2ttAr9kc3y9PSIviZd/3qkCWA== X-Received: by 2002:a1c:9f12:: with SMTP id i18-v6mr7681931wme.124.1533394696481; Sat, 04 Aug 2018 07:58:16 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id 139-v6sm4731334wmp.4.2018.08.04.07.58.15 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sat, 04 Aug 2018 07:58:15 -0700 (PDT) Date: Sat, 4 Aug 2018 15:58:13 +0100 From: Leif Lindholm To: Ming Huang Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, Heyi Guo Message-ID: <20180804145813.3bvqznfqtinajuvm@bivouac.eciton.net> References: <20180724070922.63362-1-ming.huang@linaro.org> <20180724070922.63362-32-ming.huang@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180724070922.63362-32-ming.huang@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v1 31/38] Silicon/Hisilicon/D06: Add some Lpc macro to LpcLib.h X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 04 Aug 2018 14:58:18 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Jul 24, 2018 at 03:09:15PM +0800, Ming Huang wrote: > Add soem Lpc macro to LpcLib.h for D06. soem -> some I have no issue with this patch, but can you explain when these macros are intended to be used? And if in this set, move this patch immediately before the patch than needs it? / Leif > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ming Huang > Signed-off-by: Heyi Guo > --- > Silicon/Hisilicon/Include/Library/LpcLib.h | 51 +++++++++++++++++++- > 1 file changed, 49 insertions(+), 2 deletions(-) > > diff --git a/Silicon/Hisilicon/Include/Library/LpcLib.h b/Silicon/Hisilicon/Include/Library/LpcLib.h > index 236a52ba45..5cf08ccde1 100755 > --- a/Silicon/Hisilicon/Include/Library/LpcLib.h > +++ b/Silicon/Hisilicon/Include/Library/LpcLib.h > @@ -1,7 +1,7 @@ > /** @file > * > -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. > -* Copyright (c) 2016, Linaro Limited. All rights reserved. > +* Copyright (c) 2016-2018, Hisilicon Limited. All rights reserved. > +* Copyright (c) 2016-2018, Linaro Limited. All rights reserved. > * > * This program and the accompanying materials > * are licensed and made available under the terms and conditions of the BSD License > @@ -18,6 +18,53 @@ > > #include > > +#define PCIE_SUBSYS_IOMUX 0x201100000 > +#define PCIE_SUBSYS_IOMG019 (PCIE_SUBSYS_IOMUX + 0x48) > +#define PCIE_SUBSYS_IOMG020 (PCIE_SUBSYS_IOMUX + 0x4C) > +#define PCIE_SUBSYS_IOMG021 (PCIE_SUBSYS_IOMUX + 0x50) > +#define PCIE_SUBSYS_IOMG022 (PCIE_SUBSYS_IOMUX + 0x54) > +#define PCIE_SUBSYS_IOMG023 (PCIE_SUBSYS_IOMUX + 0x58) > +#define PCIE_SUBSYS_IOMG024 (PCIE_SUBSYS_IOMUX + 0x5C) > +#define PCIE_SUBSYS_IOMG025 (PCIE_SUBSYS_IOMUX + 0x60) > +#define PCIE_SUBSYS_IOMG028 (PCIE_SUBSYS_IOMUX + 0x6C) > + > +#define IO_MGMT_SUBCTRL_BASE 0x201070000 > +#define SC_LPC_RESET_REQ_REG (IO_MGMT_SUBCTRL_BASE + 0x0a58) > +#define SC_LPC_RESET_DREQ_REG (IO_MGMT_SUBCTRL_BASE + 0x0a5c) > +#define SC_LPC_SEL (IO_MGMT_SUBCTRL_BASE + 0x2400) > + > + > +#define LPCD06_BASE 0x201190000 > +#define LPC_FIRM_SPACE0_CFG (LPCD06_BASE + 0x100) > +#define LPC_FIRM_SPACE1_CFG (LPCD06_BASE + 0x104) > +#define LPC_FIRM_SPACE2_CFG (LPCD06_BASE + 0x108) > +#define LPC_FIRM_SPACE3_CFG (LPCD06_BASE + 0x10C) > +#define LPC_FIRM_SPACE4_CFG (LPCD06_BASE + 0x110) > +#define LPC_FIRM_SPACE5_CFG (LPCD06_BASE + 0x114) > +#define LPC_FIRM_SPACE6_CFG (LPCD06_BASE + 0x118) > +#define LPC_FIRM_SPACE7_CFG (LPCD06_BASE + 0x11C) > +#define LPC_MEM_SPACE0_CFG (LPCD06_BASE + 0x120) > +#define LPC_MEM_SPACE1_CFG (LPCD06_BASE + 0x124) > +#define LPC_MEM_SPACE2_CFG (LPCD06_BASE + 0x128) > +#define LPC_MEM_SPACE3_CFG (LPCD06_BASE + 0x12C) > +#define LPC_MEM_SPACE4_CFG (LPCD06_BASE + 0x130) > +#define LPC_MEM_SPACE5_CFG (LPCD06_BASE + 0x134) > +#define LPC_MEM_SPACE6_CFG (LPCD06_BASE + 0x138) > + > +#define LPCD06_START_REG (LPCD06_BASE + 0x00) > +#define LPCD06_OP_STATUS_REG (LPCD06_BASE + 0x04) > +#define LPCD06_IRQ_ST_REG (LPCD06_BASE + 0x08) > +#define LPCD06_OP_LEN_REG (LPCD06_BASE + 0x10) > +#define LPCD06_CMD_REG (LPCD06_BASE + 0x14) > +#define LPCD06_ADDR_REG (LPCD06_BASE + 0x20) > +#define LPCD06_WDATA_REG (LPCD06_BASE + 0x24) > +#define LPCD06_RDATA_REG (LPCD06_BASE + 0x28) > + > +#define LPC_SIRQ_CTR0 (LPCD06_BASE + 0x80) > +#define LPC_SIRQ_CTR1 (LPCD06_BASE + 0x84) > +#define LPC_SIRQ_INT_MASK (LPCD06_BASE + 0x94) > + > + > #define PCIE_SUBSYS_IO_MUX 0xA0170000 > #define PCIE_SUBSYS_IOMG033 (PCIE_SUBSYS_IO_MUX + 0x84) > #define PCIE_SUBSYS_IOMG035 (PCIE_SUBSYS_IO_MUX + 0x8C) > -- > 2.17.0 >