* [PATCH edk2-platforms 1/4] Platform/Solidrun: Add Hummingboard SmBios
2018-07-22 1:30 [PATCH edk2-platforms 0/4] Import Solidrun Hummingboard Edge package Chris Co
@ 2018-07-22 1:30 ` Chris Co
2018-08-07 12:49 ` Leif Lindholm
2018-07-22 1:30 ` [PATCH edk2-platforms 2/4] Platform/Solidrun: Add Hummingboard Peripheral Initialization Chris Co
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Chris Co @ 2018-07-22 1:30 UTC (permalink / raw)
To: edk2-devel@lists.01.org; +Cc: Michael D Kinney, Ard Biesheuvel, Leif Lindholm
This adds SMBIOS support for SolidRun's i.MX6Q Hummingboard Edge.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Christopher Co <christopher.co@microsoft.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c | 801 ++++++++++++++++++++
Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf | 54 ++
2 files changed, 855 insertions(+)
diff --git a/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c
new file mode 100644
index 000000000000..3d9632814b7f
--- /dev/null
+++ b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.c
@@ -0,0 +1,801 @@
+/** @file
+
+ Copyright (c) 2012, Apple Inc. All rights reserved.<BR>
+ Copyright (c) 2013 Linaro.org
+ Copyright (c), Microsoft Corporation. All rights reserved.
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+ Static SMBIOS Table for the SolidRun HummingBoard-Edge iMX6 Quad platform
+ Derived from EmulatorPkg package
+
+ Note SMBIOS 2.7.1 Required structures:
+ BIOS Information (Type 0)
+ System Information (Type 1)
+ Board Information (Type 2)
+ System Enclosure (Type 3)
+ Processor Information (Type 4) - CPU Driver
+ Cache Information (Type 7) - For cache that is external to processor
+ System Slots (Type 9) - If system has slots
+ Physical Memory Array (Type 16)
+ Memory Device (Type 17) - For each socketed system-memory Device
+ Memory Array Mapped Address (Type 19) - One per contiguous block per Physical Memroy Array
+ System Boot Information (Type 32)
+
+**/
+
+#include <Protocol/Smbios.h>
+#include <IndustryStandard/SmBios.h>
+#include <Guid/SmBios.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/IoLib.h>
+
+SMBIOS_TABLE_TYPE0 mBIOSInfoType0 = {
+ { EFI_SMBIOS_TYPE_BIOS_INFORMATION, sizeof (SMBIOS_TABLE_TYPE0), 0 },
+ 1, // Vendor String
+ 2, // BiosVersion String
+ 0xE000, // BiosSegment
+ 3, // BiosReleaseDate String
+ 0x7F, // BiosSize
+ { // BiosCharacteristics
+ 0, // Reserved :2;
+ 0, // Unknown :1;
+ 0, // BiosCharacteristicsNotSupported :1;
+ 0, // IsaIsSupported :1;
+ 0, // McaIsSupported :1;
+ 0, // EisaIsSupported :1;
+ 0, // PciIsSupported :1;
+ 0, // PcmciaIsSupported :1;
+ 0, // PlugAndPlayIsSupported :1;
+ 0, // ApmIsSupported :1;
+ 1, // BiosIsUpgradable :1;
+ 1, // BiosShadowingAllowed :1;
+ 0, // VlVesaIsSupported :1;
+ 0, // EscdSupportIsAvailable :1;
+ 0, // BootFromCdIsSupported :1;
+ 1, // SelectableBootIsSupported :1;
+ 0, // RomBiosIsSocketed :1;
+ 0, // BootFromPcmciaIsSupported :1;
+ 0, // EDDSpecificationIsSupported :1;
+ 0, // JapaneseNecFloppyIsSupported :1;
+ 0, // JapaneseToshibaFloppyIsSupported :1;
+ 0, // Floppy525_360IsSupported :1;
+ 0, // Floppy525_12IsSupported :1;
+ 0, // Floppy35_720IsSupported :1;
+ 0, // Floppy35_288IsSupported :1;
+ 0, // PrintScreenIsSupported :1;
+ 0, // Keyboard8042IsSupported :1;
+ 0, // SerialIsSupported :1;
+ 0, // PrinterIsSupported :1;
+ 0, // CgaMonoIsSupported :1;
+ 0, // NecPc98 :1;
+ 0 // ReservedForVendor :32;
+ },
+ { // BIOSCharacteristicsExtensionBytes[]
+ 0x81, // AcpiIsSupported :1;
+ // UsbLegacyIsSupported :1;
+ // AgpIsSupported :1;
+ // I2OBootIsSupported :1;
+ // Ls120BootIsSupported :1;
+ // AtapiZipDriveBootIsSupported :1;
+ // Boot1394IsSupported :1;
+ // SmartBatteryIsSupported :1;
+ 0x0e, // BiosBootSpecIsSupported :1;
+ // FunctionKeyNetworkBootIsSupported :1;
+ // TargetContentDistributionEnabled :1;
+ // UefiSpecificationSupported :1;
+ // VirtualMachineSupported :1;
+ // ExtensionByte2Reserved :3;
+ },
+ 0x00, // SystemBiosMajorRelease
+ 0x01, // SystemBiosMinorRelease
+ 0xFF, // EmbeddedControllerFirmwareMajorRelease
+ 0xFF, // EmbeddedControllerFirmwareMinorRelease
+};
+
+CHAR8 *mBIOSInfoType0Strings[] = {
+ "To be filled by O.E.M.", // Vendor String
+ "0.1", // BiosVersion String
+ __DATE__, // BiosReleaseDate String
+ NULL
+};
+
+SMBIOS_TABLE_TYPE1 mSysInfoType1 = {
+ { EFI_SMBIOS_TYPE_SYSTEM_INFORMATION, sizeof (SMBIOS_TABLE_TYPE1), 0 },
+ 1, // Manufacturer String
+ 2, // ProductName String
+ 3, // Version String
+ 4, // SerialNumber String
+ { 0x25EF0280, 0xEC82, 0x42B0, { 0x8F, 0xB6, 0x10, 0xAD, 0xCC, 0xC6, 0x7C, 0x02 } },
+ SystemWakeupTypePowerSwitch,
+ 5, // SKUNumber String
+ 6, // Family String
+};
+CHAR8 *mSysInfoType1Strings[] = {
+ "SolidRun",
+ "HummingBoard-Edge i4Pro",
+ "2.0",
+ "System Serial#",
+ "hb04w-e-110-00-004-0",
+ "edk2",
+ NULL
+};
+
+SMBIOS_TABLE_TYPE2 mBoardInfoType2 = {
+ { EFI_SMBIOS_TYPE_BASEBOARD_INFORMATION, sizeof (SMBIOS_TABLE_TYPE2), 0 },
+ 1, // Manufacturer String
+ 2, // ProductName String
+ 3, // Version String
+ 4, // SerialNumber String
+ 5, // AssetTag String
+ { // FeatureFlag
+ 1, // Motherboard :1;
+ 0, // RequiresDaughterCard :1;
+ 0, // Removable :1;
+ 0, // Replaceable :1;
+ 0, // HotSwappable :1;
+ 0, // Reserved :3;
+ },
+ 6, // LocationInChassis String
+ 0, // ChassisHandle;
+ BaseBoardTypeMotherBoard, // BoardType;
+ 0, // NumberOfContainedObjectHandles;
+ { 0 } // ContainedObjectHandles[1];
+};
+CHAR8 *mBoardInfoType2Strings[] = {
+ "SolidRun",
+ "HummingBoard-Edge i4Pro",
+ "2.0",
+ "Base Board Serial#",
+ "Base Board Asset Tag#",
+ "hb04w-e-110-00-004-0",
+ NULL
+};
+
+SMBIOS_TABLE_TYPE3 mEnclosureInfoType3 = {
+ { EFI_SMBIOS_TYPE_SYSTEM_ENCLOSURE, sizeof (SMBIOS_TABLE_TYPE3), 0 },
+ 1, // Manufacturer String
+ MiscChassisTypeOther, // Type;
+ 2, // Version String
+ 3, // SerialNumber String
+ 4, // AssetTag String
+ ChassisStateSafe, // BootupState;
+ ChassisStateSafe, // PowerSupplyState;
+ ChassisStateSafe, // ThermalState;
+ ChassisSecurityStatusNone, // SecurityStatus;
+ { 0, 0, 0, 0 }, // OemDefined[4];
+ 0, // Height;
+ 0, // NumberofPowerCords;
+ 0, // ContainedElementCount;
+ 0, // ContainedElementRecordLength;
+ { { 0 } }, // ContainedElements[1];
+};
+CHAR8 *mEnclosureInfoType3Strings[] = {
+ "SolidRun",
+ "2.0",
+ "Chassis Board Serial#",
+ "Chassis Board Asset Tag#",
+ NULL
+};
+
+SMBIOS_TABLE_TYPE4 mProcessorInfoType4 = {
+ { EFI_SMBIOS_TYPE_PROCESSOR_INFORMATION, sizeof (SMBIOS_TABLE_TYPE4), 0},
+ 1, // Socket String;
+ CentralProcessor, // ProcessorType;
+ ProcessorFamilyIndicatorFamily2, // ProcessorFamily;
+ 2, // ProcessorManufacture String;
+ { // ProcessorId;
+ { // PROCESSOR_SIGNATURE
+ 0, // ProcessorSteppingId:4;
+ 0, // ProcessorModel: 4;
+ 0, // ProcessorFamily: 4;
+ 0, // ProcessorType: 2;
+ 0, // ProcessorReserved1: 2;
+ 0, // ProcessorXModel: 4;
+ 0, // ProcessorXFamily: 8;
+ 0, // ProcessorReserved2: 4;
+ },
+ { // PROCESSOR_FEATURE_FLAGS
+ 0, // ProcessorFpu :1;
+ 0, // ProcessorVme :1;
+ 0, // ProcessorDe :1;
+ 0, // ProcessorPse :1;
+ 0, // ProcessorTsc :1;
+ 0, // ProcessorMsr :1;
+ 0, // ProcessorPae :1;
+ 0, // ProcessorMce :1;
+ 0, // ProcessorCx8 :1;
+ 0, // ProcessorApic :1;
+ 0, // ProcessorReserved1 :1;
+ 0, // ProcessorSep :1;
+ 0, // ProcessorMtrr :1;
+ 0, // ProcessorPge :1;
+ 0, // ProcessorMca :1;
+ 0, // ProcessorCmov :1;
+ 0, // ProcessorPat :1;
+ 0, // ProcessorPse36 :1;
+ 0, // ProcessorPsn :1;
+ 0, // ProcessorClfsh :1;
+ 0, // ProcessorReserved2 :1;
+ 0, // ProcessorDs :1;
+ 0, // ProcessorAcpi :1;
+ 0, // ProcessorMmx :1;
+ 0, // ProcessorFxsr :1;
+ 0, // ProcessorSse :1;
+ 0, // ProcessorSse2 :1;
+ 0, // ProcessorSs :1;
+ 0, // ProcessorReserved3 :1;
+ 0, // ProcessorTm :1;
+ 0, // ProcessorReserved4 :2;
+ }
+ },
+ 3, // ProcessorVersion String;
+ { // Voltage;
+ 1, // ProcessorVoltageCapability5V :1;
+ 1, // ProcessorVoltageCapability3_3V :1;
+ 1, // ProcessorVoltageCapability2_9V :1;
+ 0, // ProcessorVoltageCapabilityReserved :1;
+ 0, // ProcessorVoltageReserved :3;
+ 0 // ProcessorVoltageIndicateLegacy :1;
+ },
+ 0, // ExternalClock;
+ 1200, // MaxSpeed;
+ 792, // CurrentSpeed;
+ 0x41, // Status;
+ ProcessorUpgradeOther, // ProcessorUpgrade;
+ 0, // L1CacheHandle;
+ 0, // L2CacheHandle;
+ 0, // L3CacheHandle;
+ 4, // SerialNumber;
+ 5, // AssetTag;
+ 6, // PartNumber;
+ 0, // CoreCount;
+ 0, // EnabledCoreCount;
+ 0, // ThreadCount;
+ 0, // ProcessorCharacteristics;
+ ProcessorFamilyARMv7, // ProcessorFamily2;
+};
+
+CHAR8 *mProcessorInfoType4Strings[] = {
+ "SoM",
+ "NXP",
+ "i.MX 6Quad",
+ "1.0",
+ "1.0",
+ "1.0",
+ NULL
+};
+
+SMBIOS_TABLE_TYPE7 mCacheInfoType7I1 = {
+ { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0 },
+ 1, // SocketDesignation String
+ 0x018A, // Cache Configuration
+ 0x0020, // Maximum Size 32k
+ 0x0020, // Install Size 32k
+ { // Supported SRAM Type
+ 0, //Other :1
+ 0, //Unknown :1
+ 0, //NonBurst :1
+ 1, //Burst :1
+ 0, //PiplelineBurst :1
+ 1, //Synchronous :1
+ 0, //Asynchronous :1
+ 0 //Reserved :9
+ },
+ { // Current SRAM Type
+ 0, //Other :1
+ 0, //Unknown :1
+ 0, //NonBurst :1
+ 1, //Burst :1
+ 0, //PiplelineBurst :1
+ 1, //Synchronous :1
+ 0, //Asynchronous :1
+ 0 //Reserved :9
+ },
+ 0, // Cache Speed unknown
+ CacheErrorMultiBit, // Error Correction Multi
+ CacheTypeInstruction, // System Cache Type
+ CacheAssociativity2Way // Associativity
+};
+CHAR8 *mCacheInfoType7I1Strings[] = {
+ "L1 ICache",
+ NULL
+};
+
+SMBIOS_TABLE_TYPE7 mCacheInfoType7D1 = {
+ { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0 },
+ 1, // SocketDesignation String
+ 0x018A, // Cache Configuration
+ 0x0020, // Maximum Size 32k
+ 0x0020, // Install Size 32k
+ { // Supported SRAM Type
+ 0, //Other :1
+ 0, //Unknown :1
+ 0, //NonBurst :1
+ 1, //Burst :1
+ 0, //PiplelineBurst :1
+ 1, //Synchronous :1
+ 0, //Asynchronous :1
+ 0 //Reserved :9
+ },
+ { // Current SRAM Type
+ 0, //Other :1
+ 0, //Unknown :1
+ 0, //NonBurst :1
+ 1, //Burst :1
+ 0, //PiplelineBurst :1
+ 1, //Synchronous :1
+ 0, //Asynchronous :1
+ 0 //Reserved :9
+ },
+ 0, // Cache Speed unknown
+ CacheErrorMultiBit, // Error Correction Multi
+ CacheTypeData, // System Cache Type
+ CacheAssociativity2Way // Associativity
+};
+CHAR8 *mCacheInfoType7D1Strings[] = {
+ "L1 DCache",
+ NULL
+};
+
+SMBIOS_TABLE_TYPE7 mCacheInfoType7U2 = {
+ { EFI_SMBIOS_TYPE_CACHE_INFORMATION, sizeof (SMBIOS_TABLE_TYPE7), 0 },
+ 1, // SocketDesignation String
+ 0x018A, // Cache Configuration
+ 0x0400, // Maximum Size 1M
+ 0x0400, // Install Size 1M
+ { // Supported SRAM Type
+ 0, //Other :1
+ 0, //Unknown :1
+ 0, //NonBurst :1
+ 1, //Burst :1
+ 0, //PiplelineBurst :1
+ 1, //Synchronous :1
+ 0, //Asynchronous :1
+ 0 //Reserved :9
+ },
+ { // Current SRAM Type
+ 0, //Other :1
+ 0, //Unknown :1
+ 0, //NonBurst :1
+ 1, //Burst :1
+ 0, //PiplelineBurst :1
+ 1, //Synchronous :1
+ 0, //Asynchronous :1
+ 0 //Reserved :9
+ },
+ 0, // Cache Speed unknown
+ CacheErrorMultiBit, // Error Correction Multi
+ CacheTypeUnified, // System Cache Type
+ CacheAssociativity2Way // Associativity
+};
+CHAR8 *mCacheInfoType7U2Strings[] = {
+ "L2 UCache (PL310)",
+ NULL
+};
+
+SMBIOS_TABLE_TYPE9 mSysSlotInfoType9 = {
+ { EFI_SMBIOS_TYPE_SYSTEM_SLOTS, sizeof (SMBIOS_TABLE_TYPE9), 0 },
+ 1, // SlotDesignation String
+ SlotTypeOther, // SlotType;
+ SlotDataBusWidthOther, // SlotDataBusWidth;
+ SlotUsageAvailable, // CurrentUsage;
+ SlotLengthOther, // SlotLength;
+ 0, // SlotID;
+ { // SlotCharacteristics1;
+ 1, // CharacteristicsUnknown :1;
+ 0, // Provides50Volts :1;
+ 0, // Provides33Volts :1;
+ 0, // SharedSlot :1;
+ 0, // PcCard16Supported :1;
+ 0, // CardBusSupported :1;
+ 0, // ZoomVideoSupported :1;
+ 0, // ModemRingResumeSupported:1;
+ },
+ { // SlotCharacteristics2;
+ 0, // PmeSignalSupported :1;
+ 0, // HotPlugDevicesSupported :1;
+ 0, // SmbusSignalSupported :1;
+ 0, // Reserved :5;
+ },
+ 0, // SegmentGroupNum;
+ 0, // BusNum;
+ 0, // DevFuncNum;
+};
+CHAR8 *mSysSlotInfoType9Strings[] = {
+ "SD Card",
+ NULL
+};
+
+SMBIOS_TABLE_TYPE16 mPhyMemArrayInfoType16 = {
+ { EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, sizeof (SMBIOS_TABLE_TYPE16), 0 },
+ MemoryArrayLocationSystemBoard, // Location;
+ MemoryArrayUseSystemMemory, // Use;
+ MemoryErrorCorrectionUnknown, // MemoryErrorCorrection;
+ 0x80000000, // MaximumCapacity (2 GB);
+ 0xFFFE, // MemoryErrorInformationHandle;
+ 1, // NumberOfMemoryDevices;
+ 0x80000000ULL, // ExtendedMaximumCapacity (2 GB)
+};
+CHAR8 *mPhyMemArrayInfoType16Strings[] = {
+ NULL
+};
+
+SMBIOS_TABLE_TYPE17 mMemDevInfoType17 = {
+ { EFI_SMBIOS_TYPE_MEMORY_DEVICE, sizeof (SMBIOS_TABLE_TYPE17), 0 },
+ 0, // MemoryArrayHandle; Matches SMBIOS_TABLE_TYPE16.Handle, see PhyMemArrayInfoUpdateSmbiosType16()
+ 0xFFFE, // MemoryErrorInformationHandle;
+ 0xFFFF, // TotalWidth;
+ 0xFFFF, // DataWidth;
+ 0x0800, // Size; // When bit 15 is 0: Size in MB
+ // When bit 15 is 1: Size in KB, and continues in ExtendedSize
+ MemoryFormFactorUnknown, // FormFactor;
+ 0xff, // DeviceSet;
+ 1, // DeviceLocator String
+ 2, // BankLocator String
+ MemoryTypeDram, // MemoryType;
+ { // TypeDetail;
+ 0, // Reserved :1;
+ 0, // Other :1;
+ 1, // Unknown :1;
+ 0, // FastPaged :1;
+ 0, // StaticColumn :1;
+ 0, // PseudoStatic :1;
+ 0, // Rambus :1;
+ 0, // Synchronous :1;
+ 0, // Cmos :1;
+ 0, // Edo :1;
+ 0, // WindowDram :1;
+ 0, // CacheDram :1;
+ 0, // Nonvolatile :1;
+ 0, // Registered :1;
+ 0, // Unbuffered :1;
+ 0, // Reserved1 :1;
+ },
+ 0, // Speed;
+ 3, // Manufacturer String
+ 0, // SerialNumber String
+ 0, // AssetTag String
+ 0, // PartNumber String
+ 0, // Attributes;
+ 0, // ExtendedSize;
+ 0, // ConfiguredMemoryClockSpeed;
+};
+CHAR8 *mMemDevInfoType17Strings[] = {
+ "OS Virtual Memory",
+ "malloc",
+ "OSV",
+ NULL
+};
+
+SMBIOS_TABLE_TYPE19 mMemArrMapInfoType19 = {
+ { EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, sizeof (SMBIOS_TABLE_TYPE19), 0 },
+ 0x10000000, // StartingAddress;
+ 0x8fffffff, // EndingAddress;
+ 0, // MemoryArrayHandle;
+ 1, // PartitionWidth;
+ 0, // ExtendedStartingAddress;
+ 0, // ExtendedEndingAddress;
+};
+CHAR8 *mMemArrMapInfoType19Strings[] = {
+ NULL
+};
+
+SMBIOS_TABLE_TYPE32 mBootInfoType32 = {
+ { EFI_SMBIOS_TYPE_SYSTEM_BOOT_INFORMATION, sizeof (SMBIOS_TABLE_TYPE32), 0 },
+ { 0, 0, 0, 0, 0, 0 }, // Reserved[6];
+ BootInformationStatusNoError // BootStatus
+};
+
+CHAR8 *mBootInfoType32Strings[] = {
+ NULL
+};
+
+/**
+
+ Create SMBIOS record.
+
+ Converts a fixed SMBIOS structure and an array of pointers to strings into
+ an SMBIOS record where the strings are cat'ed on the end of the fixed record
+ and terminated via a double NULL and add to SMBIOS table.
+
+ @param Template Fixed SMBIOS structure, required.
+ @param StringPack Array of strings to convert to an SMBIOS string pack.
+ NULL is OK.
+ @param DataSmbiosHandle The new SMBIOS record handle .
+ NULL is OK.
+**/
+EFI_STATUS
+EFIAPI
+LogSmbiosData (
+ IN EFI_SMBIOS_TABLE_HEADER *Template,
+ IN CHAR8 **StringPack,
+ OUT EFI_SMBIOS_HANDLE *DataSmbiosHandle
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBIOS_PROTOCOL *Smbios;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ EFI_SMBIOS_TABLE_HEADER *Record;
+ UINTN Index;
+ UINTN StringSize;
+ UINTN Size;
+ CHAR8 *Str;
+
+ Status = gBS->LocateProtocol (&gEfiSmbiosProtocolGuid, NULL, (VOID **)&Smbios);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Calculate the size of the fixed record and optional string pack
+ Size = Template->Length;
+ if (StringPack == NULL) {
+ // At least a double null is required
+ Size += 2;
+ } else {
+ for (Index = 0; StringPack[Index] != NULL; Index++) {
+ StringSize = AsciiStrSize (StringPack[Index]);
+ Size += StringSize;
+ }
+ if (StringPack[0] == NULL) {
+ // At least a double null is required
+ Size += 1;
+ }
+
+ // Don't forget the terminating double null
+ Size += 1;
+ }
+
+ // Copy over Template
+ Record = (EFI_SMBIOS_TABLE_HEADER *)AllocateZeroPool (Size);
+ if (Record == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (Record, Template, Template->Length);
+
+ // Append string pack
+ Str = ((CHAR8 *)Record) + Record->Length;
+
+ for (Index = 0; StringPack[Index] != NULL; Index++) {
+ StringSize = AsciiStrSize (StringPack[Index]);
+ CopyMem (Str, StringPack[Index], StringSize);
+ Str += StringSize;
+ }
+
+ *Str = 0;
+ SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+ Status = Smbios->Add (
+ Smbios,
+ gImageHandle,
+ &SmbiosHandle,
+ Record
+ );
+ if ((Status == EFI_SUCCESS) && (DataSmbiosHandle != NULL)) {
+ *DataSmbiosHandle = SmbiosHandle;
+ }
+
+ ASSERT_EFI_ERROR (Status);
+ FreePool (Record);
+ return Status;
+}
+
+VOID
+BIOSInfoUpdateSmbiosType0 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mBIOSInfoType0, mBIOSInfoType0Strings, NULL);
+}
+
+VOID
+I64ToHexString(
+ IN OUT CHAR8* TargetStringSz,
+ IN UINT32 TargetStringSize,
+ IN UINT64 Value
+ )
+{
+ static CHAR8 ItoH[] = { '0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F' };
+ UINT8 StringInx;
+ INT8 NibbleInx;
+
+ ZeroMem((void*)TargetStringSz, TargetStringSize);
+
+ //
+ // Convert each nibble to hex string, starting from
+ // the highest non-zero nibble.
+ //
+ StringInx = 0;
+ for (NibbleInx = sizeof(UINT64) * 2; NibbleInx > 0; --NibbleInx) {
+ UINT64 NibbleMask = (((UINT64)0xF) << ((NibbleInx - 1) * 4));
+ UINT8 Nibble = (UINT8)((Value & NibbleMask) >> ((NibbleInx - 1) * 4));
+
+ ASSERT(Nibble <= 0xF);
+
+ if (StringInx < (TargetStringSize-1)) {
+ TargetStringSz[StringInx++] = ItoH[Nibble];
+ } else {
+ break;
+ }
+ }
+}
+
+UINT64 ObtainPlatformId(VOID)
+{
+ UINT64 BoardSerial=(UINT64)0;
+
+ // see iMX6 reference manual section 46.5.10 for OTP CFG registers description
+ const UINT32 RegOCOTP_CFG0Addr=0x021BC410; // OTP Bank0 Word1 contains lower 32 bits of the Unique ID and SJC_CHALLENGE field
+ const UINT32 RegOCOTP_CFG1Addr=0x021BC420; // OTP Bank0 Word2 contains upper 32 bits of the Unique ID and SJC_CHALLENGE field
+ BoardSerial = ((UINT64)(MmioRead32(RegOCOTP_CFG1Addr))) << 32;
+ BoardSerial = BoardSerial | ((UINT64)(MmioRead32(RegOCOTP_CFG0Addr)));
+
+ DEBUG((DEBUG_INFO, "Hummingboard Edge ser no %08X%08Xh \r\n", (UINT32)(BoardSerial>>32), (UINT32)BoardSerial));
+ return BoardSerial;
+}
+
+VOID
+SysInfoUpdateSmbiosType1 (
+ VOID
+ )
+{
+ UINT64 BoardSerial=(UINT64)0;
+ UINT32 Bank0Word3=0;
+ static CHAR8 BoardSerialString[sizeof(BoardSerial) * 2 + 1]={0x00};
+ int k=0;
+
+ const UINT32 RegOCOTP_CFG2Addr=0x021BC430;
+ BoardSerial = ObtainPlatformId();
+
+ // Update the Smbios Type1 information with the board serial string
+ I64ToHexString(&BoardSerialString[0], sizeof(BoardSerialString), BoardSerial);
+ mSysInfoType1Strings[mSysInfoType1.SerialNumber - 1] = &BoardSerialString[0];
+
+ Bank0Word3 = MmioRead32(RegOCOTP_CFG2Addr);
+ // Construct string to make UUID: fixed prefix + board serial number printed in hex
+ mSysInfoType1.Uuid.Data1=((UINT32)'H'<<24) | ((UINT32)'M'<<16) | ((UINT32)'B'<<8) | (UINT32)'E' ;
+ mSysInfoType1.Uuid.Data2=(UINT16)Bank0Word3;
+ mSysInfoType1.Uuid.Data3=(UINT16)(Bank0Word3>>16);
+
+ for(k=7; k>=0; k--) {
+ mSysInfoType1.Uuid.Data4[7-k]=(UINT8)(BoardSerial>>(k*8));
+ }
+
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER*)&mSysInfoType1, mSysInfoType1Strings, NULL);
+
+}
+
+VOID
+BoardInfoUpdateSmbiosType2 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mBoardInfoType2, mBoardInfoType2Strings, NULL);
+}
+
+VOID
+EnclosureInfoUpdateSmbiosType3 (
+ VOID
+ )
+{
+ UINT8 ChassisSerialNo=0xFF;
+ static CHAR8 ChassisBoardSerialString[sizeof(ChassisSerialNo) * 2 + 1]={0x00};
+
+ // Generate chassis number from same platform id.
+ ChassisSerialNo = (UINT8)(ObtainPlatformId() >> 40);
+ DEBUG((DEBUG_INFO, "Chassis Board Serial %02Xh \r\n", ChassisSerialNo));
+
+ I64ToHexString(&ChassisBoardSerialString[0], sizeof(ChassisBoardSerialString), ChassisSerialNo);
+ mEnclosureInfoType3Strings[mEnclosureInfoType3.SerialNumber - 1] = &ChassisBoardSerialString[0];
+
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mEnclosureInfoType3, mEnclosureInfoType3Strings, NULL);
+}
+
+VOID
+ProcessorInfoUpdateSmbiosType4 (
+ IN UINTN MaxCpus
+ )
+{
+ mProcessorInfoType4.CoreCount = (UINT8) MaxCpus;
+ mProcessorInfoType4.EnabledCoreCount = (UINT8) MaxCpus;
+ mProcessorInfoType4.ThreadCount = (UINT8) MaxCpus;
+
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mProcessorInfoType4, mProcessorInfoType4Strings, NULL);
+}
+
+VOID
+CacheInfoUpdateSmbiosType7 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7I1, mCacheInfoType7I1Strings, NULL);
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7D1, mCacheInfoType7D1Strings, NULL);
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mCacheInfoType7U2, mCacheInfoType7U2Strings, NULL);
+}
+
+VOID
+SysSlotInfoUpdateSmbiosType9 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mSysSlotInfoType9, mSysSlotInfoType9Strings, NULL);
+}
+
+VOID
+PhyMemArrayInfoUpdateSmbiosType16 (
+ VOID
+ )
+{
+ EFI_SMBIOS_HANDLE MemArraySmbiosHandle;
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mPhyMemArrayInfoType16, mPhyMemArrayInfoType16Strings, &MemArraySmbiosHandle);
+
+ // Update the memory device information
+ mMemDevInfoType17.MemoryArrayHandle = MemArraySmbiosHandle;
+}
+
+VOID
+MemDevInfoUpdateSmbiosType17 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mMemDevInfoType17, mMemDevInfoType17Strings, NULL);
+}
+
+VOID
+MemArrMapInfoUpdateSmbiosType19 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mMemArrMapInfoType19, mMemArrMapInfoType19Strings, NULL);
+}
+
+VOID
+BootInfoUpdateSmbiosType32 (
+ VOID
+ )
+{
+ LogSmbiosData ((EFI_SMBIOS_TABLE_HEADER *)&mBootInfoType32, mBootInfoType32Strings, NULL);
+}
+
+EFI_STATUS
+EFIAPI
+PlatformSmbiosDriverEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ BIOSInfoUpdateSmbiosType0();
+
+ SysInfoUpdateSmbiosType1();
+
+ BoardInfoUpdateSmbiosType2();
+
+ EnclosureInfoUpdateSmbiosType3();
+
+ ProcessorInfoUpdateSmbiosType4 (FixedPcdGet32(PcdCoreCount));
+
+ CacheInfoUpdateSmbiosType7();
+
+ SysSlotInfoUpdateSmbiosType9();
+
+ PhyMemArrayInfoUpdateSmbiosType16();
+
+ MemDevInfoUpdateSmbiosType17();
+
+ MemArrMapInfoUpdateSmbiosType19();
+
+ BootInfoUpdateSmbiosType32();
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
new file mode 100644
index 000000000000..4efcd76ffb47
--- /dev/null
+++ b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
@@ -0,0 +1,54 @@
+#/** @file
+#
+# Copyright (c) 2013 Linaro.org
+# Copyright (c), Microsoft Corporation. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformSmbiosDxe
+ FILE_GUID = 3847D23F-1D95-4772-B60C-4BBFBC4D532F
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PlatformSmbiosDriverEntryPoint
+
+[Sources]
+ PlatformSmbiosDxe.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/NXP/iMX6Pkg/iMX6Pkg.dec
+
+[LibraryClasses]
+ UefiBootServicesTableLib
+ MemoryAllocationLib
+ BaseMemoryLib
+ BaseLib
+ UefiLib
+ UefiDriverEntryPoint
+ IoLib
+ DebugLib
+ IoLib
+
+[Protocols]
+ gEfiSmbiosProtocolGuid # PROTOCOL SOMETIMES_CONSUMED
+
+[Guids]
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+[Depex]
+ gEfiSmbiosProtocolGuid
--
2.16.2.gvfs.1.33.gf5370f1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH edk2-platforms 2/4] Platform/Solidrun: Add Hummingboard Peripheral Initialization
2018-07-22 1:30 [PATCH edk2-platforms 0/4] Import Solidrun Hummingboard Edge package Chris Co
2018-07-22 1:30 ` [PATCH edk2-platforms 1/4] Platform/Solidrun: Add Hummingboard SmBios Chris Co
@ 2018-07-22 1:30 ` Chris Co
2018-07-22 1:30 ` [PATCH edk2-platforms 3/4] Platform/SolidRun: Add Hummingboard ACPI tables Chris Co
2018-07-22 1:30 ` [PATCH edk2-platforms 4/4] Platform/Solidrun: Add Hummingboard dsc and fdf files Chris Co
3 siblings, 0 replies; 8+ messages in thread
From: Chris Co @ 2018-07-22 1:30 UTC (permalink / raw)
To: edk2-devel@lists.01.org; +Cc: Michael D Kinney, Ard Biesheuvel, Leif Lindholm
This adds support to initialize the different peripherals on
the Solidrun i.MX6Q Hummingboard Edge. It will initialize the
pad mux and clocks for the different peripherals.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Christopher Co <christopher.co@microsoft.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Library/iMX6BoardLib/iMX6BoardInit.c | 1295 ++++++++++++++++++++
Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Library/iMX6BoardLib/iMX6BoardLib.inf | 96 ++
2 files changed, 1391 insertions(+)
diff --git a/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Library/iMX6BoardLib/iMX6BoardInit.c b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Library/iMX6BoardLib/iMX6BoardInit.c
new file mode 100644
index 000000000000..137d05674963
--- /dev/null
+++ b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Library/iMX6BoardLib/iMX6BoardInit.c
@@ -0,0 +1,1295 @@
+/** @file
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+* Copyright 2018 NXP
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/IoLib.h>
+#include <Library/ArmPlatformLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PrintLib.h>
+#include <Library/PcdLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/TimerLib.h>
+
+#include <iMX6.h>
+#include <iMX6ClkPwr.h>
+#include <iMX6IoMux.h>
+#include <iMX6UsbPhy.h>
+
+#include <common_macros.h>
+
+#include <IndustryStandard/Tpm20.h>
+#include <IndustryStandard/Tpm2Acpi.h>
+
+#define DEBUG_SDHC_PINMUXING 0
+
+RETURN_STATUS
+EFIAPI
+TimerConstructor (
+ VOID
+ );
+
+/*
+ Prebaked pad configurations that include mux and drive settings where
+ each enum named as IMX_<MODULE-NAME>_PADCFG contains configurations
+ for pads used by that module
+*/
+typedef enum {
+ IMX_PAD_ENET_MDIO_ENET_MDIO = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_ENABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_ENET_MDIO_ALT1_ENET_MDIO),
+
+ IMX_PAD_ENET_MDC_ENET_MDC = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_ENET_MDC_ALT1_ENET_MDC),
+
+ IMX_PAD_CFG_KEY_ROW4_GPIO4_IO15 = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PD,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_KEY_ROW4_ALT5_GPIO4_IO15),
+
+ IMX_PAD_DI0_PIN2_GPIO4_IO18 = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PD,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_DI0_PIN2_ALT5_GPIO4_IO18),
+
+ IMX_PAD_GPIO_16_ENET_REF_CLK = _IMX_MAKE_PADCFG_INPSEL(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_GPIO_16_ALT2_ENET_REF_CLK,
+ IOMUXC_ENET_REF_CLK_SELECT_INPUT,
+ GPIO16_ALT2),
+
+ IMX_PAD_RGMII_TXC_RGMII_TXC = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_RGMII_TXC_ALT1_RGMII_TXC),
+
+ IMX_PAD_RGMII_TD0_RGMII_TD0 = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_KEEP,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_RGMII_TD0_ALT1_RGMII_TD0),
+
+ IMX_PAD_RGMII_TD1_RGMII_TD1 = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_KEEP,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_RGMII_TD1_ALT1_RGMII_TD1),
+
+ IMX_PAD_RGMII_TD2_RGMII_TD2 = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_KEEP,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_RGMII_TD2_ALT1_RGMII_TD2),
+
+ IMX_PAD_RGMII_TD3_RGMII_TD3 = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_KEEP,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_RGMII_TD3_ALT1_RGMII_TD3),
+
+ IMX_PAD_RGMII_TX_CTL_RGMII_TX_CTL = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_RGMII_TX_CTL_ALT1_RGMII_TX_CTL),
+
+ IMX_PAD_ENET_REF_CLK_ENET_REF_CLK = _IMX_MAKE_PADCFG(
+ IMX_SRE_FAST,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_KEEP,
+ IMX_PUS_100K_OHM_PD,
+ IMX_HYS_DISABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_ENET_REF_CLK_ALT1_ENET_TX_CLK),
+
+ IMX_PAD_RGMII_RXC_ENET_RGMII_RXC = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_KEEP,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_RGMII_RXC_ALT1_RGMII_RXC),
+
+ IMX_PAD_RGMII_RD0_ENET_RGMII_RD0 = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_KEEP,
+ IMX_PUS_100K_OHM_PD,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_RGMII_RD0_ALT1_RGMII_RD0),
+
+ IMX_PAD_RGMII_RD1_ENET_RGMII_RD1 = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_KEEP,
+ IMX_PUS_100K_OHM_PD,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_RGMII_RD1_ALT1_RGMII_RD1),
+
+ IMX_PAD_RGMII_RD2_ENET_RGMII_RD2 = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_KEEP,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_RGMII_RD2_ALT1_RGMII_RD2),
+
+ IMX_PAD_RGMII_RD3_ENET_RGMII_RD3 = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_KEEP,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_RGMII_RD3_ALT1_RGMII_RD3),
+
+ IMX_PAD_RGMII_RX_CTL_RGMII_RX_CTL = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_KEEP,
+ IMX_PUS_100K_OHM_PD,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_RGMII_RX_CTL_ALT1_RGMII_RX_CTL),
+} IMX_ENET_PADCFG;
+
+typedef enum {
+ IMX_PAD_CFG_EIM_DATA22_GPIO3_IO22_USB_OTG_PWR = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_EIM_D22_ALT5_GPIO3_IO22),
+
+ IMX_PAD_CFG_KEY_COL4_USB_OTG_OC = _IMX_MAKE_PADCFG_INPSEL(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_LOW,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_KEY_COL4_ALT2_USB_OTG_OC,
+ IOMUXC_USB_OTG_OC_SELECT_INPUT,
+ KEY_COL4_ALT2),
+
+ IMX_PAD_CFG_GPIO0_GPIO1_IO0_USBH1_PWR = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_GPIO_0_ALT5_GPIO1_IO00),
+
+ IMX_PAD_CFG_GPIO01_USB_OTG_ID_HOST = _IMX_MAKE_PADCFG(
+ IMX_SRE_FAST,
+ IMX_DSE_90_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PD,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_GPIO_1_ALT3_USB_OTG_ID),
+
+ IMX_PAD_CFG_GPIO01_USB_OTG_ID_DEVICE = _IMX_MAKE_PADCFG(
+ IMX_SRE_FAST,
+ IMX_DSE_90_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_GPIO_1_ALT3_USB_OTG_ID),
+} IMX_EHCI_PADCFG;
+
+typedef enum {
+ IMX_PAD_CFG_SD4_DATA3_GPIO2_IO11 = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD4_DAT3_ALT5_GPIO2_IO11),
+} IMX_IMX6Q_PCIE_PADCFG;
+
+typedef enum {
+ IMX_PAD_CFG_EIM_EB3_GPIO2_IO31 = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_260_OHM,
+ IMX_SPEED_LOW,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_DISABLED,
+ IMX_SION_ENABLED,
+ IMX_IOMUXC_EIM_EB3_ALT5_GPIO2_IO31),
+
+ IMX_PAD_CFG_EIM_D21_I2C1_SCL = _IMX_MAKE_PADCFG_INPSEL(
+ IMX_SRE_FAST,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_ENABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_47K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_ENABLED,
+ IMX_IOMUXC_EIM_D21_ALT6_I2C1_SCL,
+ IOMUXC_I2C1_SCL_IN_SELECT_INPUT,
+ EIM_DATA21_ALT6),
+
+ IMX_PAD_CFG_EIM_D28_I2C1_SDA = _IMX_MAKE_PADCFG_INPSEL(
+ IMX_SRE_FAST,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_ENABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_47K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_ENABLED,
+ IMX_IOMUXC_EIM_D28_ALT1_I2C1_SDA,
+ IOMUXC_I2C1_SDA_IN_SELECT_INPUT,
+ EIM_DATA28_ALT1),
+
+ IMX_PAD_CFG_EIM_D17_I2C3_SCL = _IMX_MAKE_PADCFG_INPSEL(
+ IMX_SRE_FAST,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_ENABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_47K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_ENABLED,
+ IMX_IOMUXC_EIM_D17_ALT6_I2C3_SCL,
+ IOMUXC_I2C3_SCL_IN_SELECT_INPUT,
+ EIM_DATA17_ALT6),
+
+ IMX_PAD_CFG_EIM_D18_I2C3_SDA = _IMX_MAKE_PADCFG_INPSEL(
+ IMX_SRE_FAST,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_ENABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_47K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_ENABLED,
+ IMX_IOMUXC_EIM_D18_ALT6_I2C3_SDA,
+ IOMUXC_I2C3_SDA_IN_SELECT_INPUT,
+ EIM_DATA18_ALT6),
+} IMX_I2C_PADCFG;
+
+typedef enum {
+ IMX_PAD_CFG_GPIO_5_CCM_CLKO1 = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_GPIO_5_ALT3_CCM_CLKO1),
+
+ IMX_PAD_CFG_KEY_COL0_AUD5_TXC = _IMX_MAKE_PADCFG_INPSEL(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_KEY_COL0_ALT2_AUD5_TXC,
+ IOMUXC_AUD5_INPUT_TXCLK_AMX_SELECT_INPUT,
+ KEY_COL0_ALT2),
+
+ IMX_PAD_CFG_KEY_ROW0_AUD5_TXD = _IMX_MAKE_PADCFG_INPSEL(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_KEY_ROW0_ALT2_AUD5_TXD,
+ IOMUXC_AUD5_INPUT_DB_AMX_SELECT_INPUT,
+ KEY_ROW0_ALT2),
+
+ IMX_PAD_CFG_KEY_COL1_AUD5_TXFS = _IMX_MAKE_PADCFG_INPSEL(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_KEY_COL1_ALT2_AUD5_TXFS,
+ IOMUXC_AUD5_INPUT_TXFS_AMX_SELECT_INPUT,
+ KEY_COL1_ALT2),
+
+ IMX_PAD_CFG_DISP0_DAT19_AUD5_RXD = _IMX_MAKE_PADCFG_INPSEL(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_DISP0_DAT19_ALT3_AUD5_RXD,
+ IOMUXC_AUD5_INPUT_DA_AMX_SELECT_INPUT,
+ DISP0_DATA19_ALT3),
+} IMX_AUDIO_PADCFG;
+
+typedef enum {
+ IMX_USDHC_CMD_PAD_CTL = _IMX_MAKE_PAD_CTL(
+ IMX_SRE_FAST,
+ IMX_DSE_33_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_47K_OHM_PU,
+ IMX_HYS_ENABLED),
+
+ IMX_USDHC_CLK_PAD_CTL = _IMX_MAKE_PAD_CTL(
+ IMX_SRE_FAST,
+ IMX_DSE_33_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ 0,
+ 0,
+ IMX_HYS_ENABLED),
+
+ IMX_USDHC_DAT_PAD_CTL = _IMX_MAKE_PAD_CTL(
+ IMX_SRE_FAST,
+ IMX_DSE_33_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_47K_OHM_PU,
+ IMX_HYS_ENABLED),
+
+ IMX_USDHC_GPIO_PAD_CTL = _IMX_MAKE_PAD_CTL(
+ IMX_SRE_FAST,
+ IMX_DSE_33_OHM,
+ IMX_SPEED_LOW,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ 0,
+ 0,
+ IMX_HYS_ENABLED),
+
+ IMX_USDHC_CD_PAD_CTL = _IMX_MAKE_PAD_CTL(
+ IMX_SRE_FAST,
+ IMX_DSE_33_OHM,
+ IMX_SPEED_LOW,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_47K_OHM_PU,
+ IMX_HYS_ENABLED),
+
+ IMX_PAD_CFG_SD2_CLK_SD2_CLK = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_CLK_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD2_CLK_ALT0_SD2_CLK),
+
+ IMX_PAD_CFG_SD2_CMD_SD2_CMD = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_CMD_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD2_CMD_ALT0_SD2_CMD),
+
+ IMX_PAD_CFG_SD2_DAT0_SD2_DATA0 = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_DAT_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD2_DAT0_ALT0_SD2_DATA0),
+
+ IMX_PAD_CFG_SD2_DAT1_SD2_DATA1 = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_DAT_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD2_DAT1_ALT0_SD2_DATA1),
+
+ IMX_PAD_CFG_SD2_DAT2_SD2_DATA2 = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_DAT_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD2_DAT2_ALT0_SD2_DATA2),
+
+ IMX_PAD_CFG_SD2_DAT3_SD2_DATA3 = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_DAT_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD2_DAT3_ALT0_SD2_DATA3),
+
+ IMX_PAD_CFG_KEY_ROW1_SD2_VSELECT = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_GPIO_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_KEY_ROW1_ALT6_SD2_VSELECT),
+
+ IMX_PAD_CFG_GPIO_4_SD2_CD_B = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_CD_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_GPIO_4_ALT6_SD2_CD_B),
+
+ IMX_PAD_CFG_DISP0_DAT9_GPIO4_IO30 = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_GPIO_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_DISP0_DAT9_ALT5_GPIO4_IO30),
+} IMX_USDHC2_PADCFG;
+
+typedef enum {
+ IMX_PAD_CFG_SD3_CLK_SD3_CLK = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_CLK_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD3_CLK_ALT0_SD3_CLK),
+
+ IMX_PAD_CFG_SD3_CMD_SD3_CMD = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_CMD_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD3_CMD_ALT0_SD3_CMD),
+
+ IMX_PAD_CFG_SD3_RST_SD3_RST = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_GPIO_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD3_RST_ALT0_SD3_RESET),
+
+ IMX_PAD_CFG_SD3_DAT0_SD3_DATA0 = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_DAT_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD3_DAT0_ALT0_SD3_DATA0),
+
+ IMX_PAD_CFG_SD3_DAT1_SD3_DATA1 = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_DAT_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD3_DAT1_ALT0_SD3_DATA1),
+
+ IMX_PAD_CFG_SD3_DAT2_SD3_DATA2 = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_DAT_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD3_DAT2_ALT0_SD3_DATA2),
+
+ IMX_PAD_CFG_SD3_DAT3_SD3_DATA3 = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_DAT_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD3_DAT3_ALT0_SD3_DATA3),
+
+ IMX_PAD_CFG_SD3_DAT4_SD3_DATA4 = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_DAT_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD3_DAT4_ALT0_SD3_DATA4),
+
+ IMX_PAD_CFG_SD3_DAT5_SD3_DATA5 = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_DAT_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD3_DAT5_ALT0_SD3_DATA5),
+
+ IMX_PAD_CFG_SD3_DAT6_SD3_DATA6 = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_DAT_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD3_DAT6_ALT0_SD3_DATA6),
+
+ IMX_PAD_CFG_SD3_DAT7_SD3_DATA7 = _IMX_MAKE_PADCFG2(
+ IMX_USDHC_DAT_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD3_DAT7_ALT0_SD3_DATA7),
+} IMX_USDHC3_PADCFG;
+
+typedef enum {
+ IMX_PWM_CLK_PAD_CTL = _IMX_MAKE_PAD_CTL(
+ IMX_SRE_FAST,
+ IMX_DSE_33_OHM,
+ IMX_SPEED_LOW,
+ IMX_ODE_DISABLE,
+ IMX_PKE_DISABLE,
+ 0,
+ 0,
+ IMX_HYS_ENABLED),
+
+ IMX_PAD_CFG_DISP0_DAT8_PWM1_OUT = _IMX_MAKE_PADCFG2(
+ IMX_PWM_CLK_PAD_CTL,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_DISP0_DAT8_ALT2_PWM1_OUT),
+} IMX_PWM_PADCFG;
+
+typedef enum {
+ IMX_PAD_UART1_RX_DATA = _IMX_MAKE_PADCFG_INPSEL(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM, // 110 40_OHM - 25 Ohm @ 3.3V, 40 Ohm @ 1.8V
+ IMX_SPEED_MEDIUM, // 10 MEDIUM - Medium frequency (100, 150 MHz)
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE, // 12=1 ENABLED - Pull/Keeper Enabled
+ IMX_PUE_PULL, // 13=1 PULL - Pull Enabled
+ IMX_PUS_100K_OHM_PU, // 14-15 10 - 100K Ohm Pull Up
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_CSI0_DAT11_ALT3_UART1_RX_DATA,
+ IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT,
+ CSI0_DATA11_ALT3),
+
+ IMX_PAD_UART1_TX_DATA = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_CSI0_DAT10_ALT3_UART1_TX_DATA),
+
+ IMX_PAD_UART3_RX_DATA = _IMX_MAKE_PADCFG_INPSEL(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_EIM_D25_ALT2_UART3_RX_DATA,
+ IOMUXC_UART3_UART_RX_DATA_SELECT_INPUT,
+ EIM_DATA25_ALT2),
+
+ IMX_PAD_UART3_TX_DATA = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_EIM_D24_ALT2_UART3_TX_DATA),
+} IMX_UART_PADCFG;
+
+typedef enum {
+ IMX_PAD_CFG_SD4_DATA1_GPIO2_IO09 = _IMX_MAKE_PADCFG(
+ IMX_SRE_SLOW,
+ IMX_DSE_40_OHM,
+ IMX_SPEED_MEDIUM,
+ IMX_ODE_DISABLE,
+ IMX_PKE_ENABLE,
+ IMX_PUE_PULL,
+ IMX_PUS_100K_OHM_PU,
+ IMX_HYS_ENABLED,
+ IMX_SION_DISABLED,
+ IMX_IOMUXC_SD4_DAT1_ALT5_GPIO2_IO09),
+
+} IMX_IMX6Q_LDB_PADCFG;
+
+/**
+ Turn off clock gates which are not needed during boot. The PEP is responsible
+ to ungate clocks as needed.
+**/
+static VOID GateUnusedClocks ()
+{
+ static const IMX_CLK_GATE gatesToTurnOff[] = {
+ IMX_ASRC_CLK_ENABLE,
+ IMX_CAN1_CLK_ENABLE,
+ IMX_CAN1_SERIAL_CLK_ENABLE,
+ IMX_CAN2_CLK_ENABLE,
+ IMX_CAN2_SERIAL_CLK_ENABLE,
+ IMX_DCIC1_CLK_ENABLE,
+ IMX_DCIC2_CLK_ENABLE,
+ IMX_DTCP_CLK_ENABLE,
+ IMX_ECSPI1_CLK_ENABLE,
+ IMX_ECSPI2_CLK_ENABLE,
+ IMX_ECSPI3_CLK_ENABLE,
+ IMX_ECSPI4_CLK_ENABLE,
+ IMX_ECSPI5_CLK_ENABLE,
+ IMX_ENET_CLK_ENABLE,
+ IMX_ESAI_CLK_ENABLE,
+ IMX_I2C1_SERIAL_CLK_ENABLE,
+ IMX_I2C2_SERIAL_CLK_ENABLE,
+ IMX_I2C3_SERIAL_CLK_ENABLE,
+ IMX_IIM_CLK_ENABLE,
+ IMX_IPSYNC_IP2APB_TZASC1_IPG_MASTER_CLK_ENABLE,
+ IMX_IPSYNC_IP2APB_TZASC2_IPG_MASTER_CLK_ENABLE,
+ IMX_IPSYNC_VDOA_IPG_MASTER_CLK_ENABLE,
+ IMX_IPU1_DI1_CLK_ENABLE,
+ IMX_IPU2_CLK_ENABLE,
+ IMX_IPU2_DI0_CLK_ENABLE,
+ IMX_IPU2_DI1_CLK_ENABLE,
+ IMX_LDB_DI0_CLK_ENABLE,
+ IMX_LDB_DI1_CLK_ENABLE,
+ IMX_MIPI_CORE_CFG_CLK_ENABLE,
+ IMX_MLB_CLK_ENABLE,
+ IMX_PL301_MX6QPER1_BCHCLK_ENABLE,
+ IMX_PWM2_CLK_ENABLE,
+ IMX_PWM3_CLK_ENABLE,
+ IMX_PWM4_CLK_ENABLE,
+ IMX_RAWNAND_U_BCH_INPUT_APB_CLK_ENABLE,
+ IMX_RAWNAND_U_GPMI_BCH_INPUT_BCH_CLK_ENABLE,
+ IMX_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_CLK_ENABLE,
+ IMX_RAWNAND_U_GPMI_INPUT_APB_CLK_ENABLE,
+ IMX_SPDIF_CLK_ENABLE,
+ IMX_SSI1_CLK_ENABLE,
+ IMX_SSI2_CLK_ENABLE,
+ IMX_SSI3_CLK_ENABLE,
+ IMX_EIM_SLOW_CLK_ENABLE,
+ IMX_VDOAXICLK_CLK_ENABLE,
+ IMX_VPU_CLK_ENABLE,
+ };
+
+ ImxClkPwrSetClockGates (
+ gatesToTurnOff,
+ sizeof (gatesToTurnOff) / sizeof (gatesToTurnOff[0]),
+ IMX_CLOCK_GATE_STATE_OFF);
+}
+
+/**
+ Turn on required clocks, that are not handled by the PEP.
+**/
+static VOID UngateRequiredClocks ()
+{
+ static const IMX_CLK_GATE gatesToTurnOn[] = {
+ IMX_SDMA_CLK_ENABLE,
+ IMX_SPBA_CLK_ENABLE,
+ IMX_GPT_SERIAL_CLK_ENABLE,
+ IMX_USBOH3_CLK_ENABLE,
+ IMX_PWM1_CLK_ENABLE
+ };
+
+ ImxClkPwrSetClockGates(
+ gatesToTurnOn,
+ sizeof(gatesToTurnOn) / sizeof(gatesToTurnOn[0]),
+ IMX_CLOCK_GATE_STATE_ON);
+}
+
+static void EnetInit ()
+{
+ // Apply ENET pin-muxing configurations
+ ImxPadConfig(IMX_PAD_ENET_MDIO, IMX_PAD_ENET_MDIO_ENET_MDIO); // pad ENET_MDIO (mode ALT1)
+ ImxPadConfig(IMX_PAD_ENET_MDC, IMX_PAD_ENET_MDC_ENET_MDC); // pad ENET_MDC (mode ALT1)
+ ImxPadConfig(IMX_PAD_KEY_ROW4, IMX_PAD_CFG_KEY_ROW4_GPIO4_IO15);
+ ImxPadConfig(IMX_PAD_DI0_PIN2, IMX_PAD_DI0_PIN2_GPIO4_IO18);
+ ImxPadConfig(IMX_PAD_GPIO_16, IMX_PAD_GPIO_16_ENET_REF_CLK);
+ ImxPadConfig(IMX_PAD_ENET_REF_CLK, IMX_PAD_ENET_REF_CLK_ENET_REF_CLK); // pad ENET_REF_CLK (mode ALT1)
+ ImxPadConfig(IMX_PAD_RGMII_TD0, IMX_PAD_RGMII_TD0_RGMII_TD0); // RGMII_TD0 (ALT1)
+ ImxPadConfig(IMX_PAD_RGMII_TD1, IMX_PAD_RGMII_TD1_RGMII_TD1); // RGMII_TD1 (ALT1)
+ ImxPadConfig(IMX_PAD_RGMII_TD2, IMX_PAD_RGMII_TD2_RGMII_TD2); // RGMII_TD2 (ALT1)
+ ImxPadConfig(IMX_PAD_RGMII_TD3, IMX_PAD_RGMII_TD3_RGMII_TD3); // RGMII_TD3 (ALT1)
+ ImxPadConfig(IMX_PAD_RGMII_TXC, IMX_PAD_RGMII_TXC_RGMII_TXC); // pad RGMII_TXC (ALT1)
+ ImxPadConfig(IMX_PAD_RGMII_TX_CTL, IMX_PAD_RGMII_TX_CTL_RGMII_TX_CTL); // RGMII_TX_CTL (ALT1)
+
+ ImxPadConfig(IMX_PAD_RGMII_RD0, IMX_PAD_RGMII_RD0_ENET_RGMII_RD0); // RGMII_RD0 (ALT1)
+ ImxPadConfig(IMX_PAD_RGMII_RD1, IMX_PAD_RGMII_RD1_ENET_RGMII_RD1); // RGMII_RD1 (ALT1)
+ ImxPadConfig(IMX_PAD_RGMII_RD2, IMX_PAD_RGMII_RD2_ENET_RGMII_RD2); // RGMII_RD2 (ALT1)
+ ImxPadConfig(IMX_PAD_RGMII_RD3, IMX_PAD_RGMII_RD3_ENET_RGMII_RD3); // RGMII_RD3 (ALT1)
+ ImxPadConfig(IMX_PAD_RGMII_RXC, IMX_PAD_RGMII_RXC_ENET_RGMII_RXC); // RGMII_RXC (ALT1)
+ ImxPadConfig(IMX_PAD_RGMII_RX_CTL, IMX_PAD_RGMII_RX_CTL_RGMII_RX_CTL); // RGMII_RX_CTL (ALT1)
+
+ // Enable ENET PLL, also required for PCIe
+ {
+ UINT32 counter = 0;
+ IMX_CCM_ANALOG_PLL_ENET_REG ccmAnalogPllReg;
+ volatile IMX_CCM_ANALOG_REGISTERS *ccmAnalogRegistersPtr =
+ (IMX_CCM_ANALOG_REGISTERS *)IMX_CCM_ANALOG_BASE;
+
+ ccmAnalogPllReg.AsUint32 = MmioRead32((UINTN)&ccmAnalogRegistersPtr->PLL_ENET);
+ ccmAnalogPllReg.POWERDOWN = 0;
+ ccmAnalogPllReg.ENABLE = 1;
+
+ MmioWrite32(
+ (UINTN)&ccmAnalogRegistersPtr->PLL_ENET,
+ ccmAnalogPllReg.AsUint32);
+
+ do {
+ ccmAnalogPllReg.AsUint32 =
+ MmioRead32((UINTN)&ccmAnalogRegistersPtr->PLL_ENET);
+
+ MicroSecondDelay(100);
+ ++counter;
+ } while ((ccmAnalogPllReg.LOCK == 0) && (counter < 100));
+
+ // Enable PCIe output 125Mhz
+ ccmAnalogPllReg.BYPASS = 0;
+ ccmAnalogPllReg.ENABLE_125M = 1;
+ ccmAnalogPllReg.DIV_SELECT = PLL_ENET_DIV_SELECT_25MHZ;
+
+ MmioWrite32(
+ (UINTN)&ccmAnalogRegistersPtr->PLL_ENET,
+ ccmAnalogPllReg.AsUint32);
+
+ MicroSecondDelay(50000);
+
+ if (ccmAnalogPllReg.LOCK == 0) {
+ DEBUG ((DEBUG_ERROR, "PLL_ENET is not locked!\n"));
+ }
+ }
+}
+
+/**
+ Set SSI3 clock dividers to provide a bit clock capable of
+ providing a clock suitable for stereo 44.1 KHz playback at 32 bit
+ from PLL3 PFD2 which runs at 508.2 MHz.
+
+ We only need to scale down the PLL3 FPD2 clock by 1:15 to provide a
+ reference clock. The WDM audio class driver will later setup additional
+ dividers in the SSI3 block to provide the required bit clock rate.
+
+ This routine also handles all GPIO/PadConfig init required for audio.
+**/
+static void SetupAudio ()
+{
+ volatile IMX_CCM_REGISTERS *ccmRegisters = (IMX_CCM_REGISTERS *) IMX_CCM_BASE;
+
+ IMX_CCM_CS1CDR_REG csicdr = (IMX_CCM_CS1CDR_REG) MmioRead32((UINTN) &ccmRegisters->CS1CDR);
+
+ csicdr.ssi3_clk_pred = 0; // divide by 1.
+ csicdr.ssi3_clk_podf = (15 - 1); // divide by 15.
+
+ MmioWrite32((UINTN) &ccmRegisters->CS1CDR, csicdr.AsUint32);
+
+ // Enable output on CCM_CLKO1, select pll3_sw_clk/2 as the source.
+ IMX_CCM_CCOSR_REG ccosr = (IMX_CCM_CCOSR_REG) MmioRead32((UINTN) &ccmRegisters->CCOSR);
+
+ ccosr.CLKO1_SEL = 0;
+ ccosr.CLKO1_DIV = 0;
+ ccosr.CLKO1_EN = 1;
+
+ MmioWrite32((UINTN) &ccmRegisters->CCOSR, ccosr.AsUint32);
+
+ // Set GPIO05 alt config to ALT3 (CCM_CLKO1).
+ // This clock drives the master clock for the audio codec.
+ ImxPadConfig(IMX_PAD_GPIO_5, IMX_PAD_CFG_GPIO_5_CCM_CLKO1);
+
+ // Set alt config for KEY_COL0, KEY_ROW0, KEY_COL1, to ALT2 to select AUD5_TXC/TXD/TXFS.
+ // DSP_DAT19 is set to ALT3 for AUD5_RXD.
+ ImxPadConfig(IMX_PAD_KEY_COL0, IMX_PAD_CFG_KEY_COL0_AUD5_TXC);
+ ImxPadConfig(IMX_PAD_KEY_ROW0, IMX_PAD_CFG_KEY_ROW0_AUD5_TXD);
+ ImxPadConfig(IMX_PAD_KEY_COL1, IMX_PAD_CFG_KEY_COL1_AUD5_TXFS);
+ ImxPadConfig(IMX_PAD_DISP0_DAT19, IMX_PAD_CFG_DISP0_DAT19_AUD5_RXD);
+}
+
+/**
+ Initialize clock and power for modules on the SoC.
+**/
+VOID ImxClkPwrInit ()
+{
+ EFI_STATUS status;
+
+ GateUnusedClocks();
+ UngateRequiredClocks();
+
+ if (FeaturePcdGet (PcdGpuEnable)) {
+ status = ImxClkPwrGpuEnable ();
+ ASSERT_EFI_ERROR (status);
+ }
+
+ if (FeaturePcdGet(PcdLvdsEnable)) {
+ status = ImxClkPwrIpuLDBxEnable ();
+ ASSERT_EFI_ERROR (status);
+ }
+
+ status = ImxClkPwrIpuDIxEnable();
+ ASSERT_EFI_ERROR (status);
+
+ ASSERT_EFI_ERROR (ImxClkPwrValidateClocks ());
+}
+
+/**
+ Initialize SDHC modules on the SOC and perform required pin-muxing
+**/
+VOID SdhcInit ()
+{
+ // uSDHC2: SDCard Socket
+ ImxPadConfig(IMX_PAD_SD2_CLK, IMX_PAD_CFG_SD2_CLK_SD2_CLK);
+ ImxPadConfig(IMX_PAD_SD2_CMD, IMX_PAD_CFG_SD2_CMD_SD2_CMD);
+ ImxPadConfig(IMX_PAD_SD2_DAT0, IMX_PAD_CFG_SD2_DAT0_SD2_DATA0);
+ ImxPadConfig(IMX_PAD_SD2_DAT1, IMX_PAD_CFG_SD2_DAT1_SD2_DATA1);
+ ImxPadConfig(IMX_PAD_SD2_DAT2, IMX_PAD_CFG_SD2_DAT2_SD2_DATA2);
+ ImxPadConfig(IMX_PAD_SD2_DAT3, IMX_PAD_CFG_SD2_DAT3_SD2_DATA3);
+ ImxPadConfig(IMX_PAD_GPIO_4, IMX_PAD_CFG_GPIO_4_SD2_CD_B);
+ ImxPadConfig(IMX_PAD_KEY_ROW1, IMX_PAD_CFG_KEY_ROW1_SD2_VSELECT);
+
+#if DEBUG_SDHC_PINMUXING
+ DEBUG((DEBUG_INIT, "uSDHC2 PAD Config:\n"));
+ ImxPadDumpConfig("CLK",IMX_PAD_SD2_CLK);
+ ImxPadDumpConfig("CMD",IMX_PAD_SD2_CMD);
+ ImxPadDumpConfig("DAT0",IMX_PAD_SD2_DAT0);
+ ImxPadDumpConfig("DAT1",IMX_PAD_SD2_DAT1);
+ ImxPadDumpConfig("DAT2",IMX_PAD_SD2_DAT2);
+ ImxPadDumpConfig("DAT3",IMX_PAD_SD2_DAT3);
+ ImxPadDumpConfig("VSELECT",IMX_PAD_KEY_ROW1);
+ ImxPadDumpConfig("CD",IMX_PAD_GPIO_4);
+#endif // DEBUG_SDHC_PINMUXING
+
+ // Power-on SDCard through the GPIO signal connected to
+ // Q1 MOSFET Gate acting as a switch to SDCard VDD supply voltage
+ ImxPadConfig(IMX_PAD_DISP0_DAT9, IMX_PAD_CFG_DISP0_DAT9_GPIO4_IO30);
+ ImxGpioDirection(IMX_GPIO_BANK4, 30, IMX_GPIO_DIR_OUTPUT);
+ ImxGpioWrite(IMX_GPIO_BANK4, 30, IMX_GPIO_LOW);
+
+ // Pre-configure the GPIO ALT5 of all SD2_* pads to be input pins. This is
+ // required by the SD _DSM for slot power-cycle. The power-on/off _DSM need to
+ // disconnect all SD pins as part of the power-off sequence. This will be
+ // achieved by switching the alternate function of the SD pads from ALT0 SD2_*
+ // to ALT5 GPIO1_IO* and disable the pull-up resistors. On power-on, the SD2_*
+ // pads will be reconfigured as as ALT0 SD2_* functions and the pull-ups will
+ // be enabled again. The net effect is that all the SD pins will float and a
+ // proper SD power-cycle can be achieved.
+
+ // SD2_CLK: GPIO1_IO10
+ ImxGpioDirection(IMX_GPIO_BANK1, 10, IMX_GPIO_DIR_INPUT);
+
+ // SD2_CMD: GPIO1_IO11
+ ImxGpioDirection(IMX_GPIO_BANK1, 11, IMX_GPIO_DIR_INPUT);
+
+ // SD2_DATA0: GPIO1_IO15
+ ImxGpioDirection(IMX_GPIO_BANK1, 15, IMX_GPIO_DIR_INPUT);
+
+ // SD2_DATA1: GPIO1_IO14
+ ImxGpioDirection(IMX_GPIO_BANK1, 14, IMX_GPIO_DIR_INPUT);
+
+ // SD2_DATA2: GPIO1_IO13
+ ImxGpioDirection(IMX_GPIO_BANK1, 13, IMX_GPIO_DIR_INPUT);
+
+ // SD2_DATA3: GPIO1_IO12
+ ImxGpioDirection(IMX_GPIO_BANK1, 12, IMX_GPIO_DIR_INPUT);
+
+ // uSDHC3: eMMC Socket
+ ImxPadConfig(IMX_PAD_SD3_CLK, IMX_PAD_CFG_SD3_CLK_SD3_CLK);
+ ImxPadConfig(IMX_PAD_SD3_CMD, IMX_PAD_CFG_SD3_CMD_SD3_CMD);
+ ImxPadConfig(IMX_PAD_SD3_RST, IMX_PAD_CFG_SD3_RST_SD3_RST);
+ ImxPadConfig(IMX_PAD_SD3_DAT0, IMX_PAD_CFG_SD3_DAT0_SD3_DATA0);
+ ImxPadConfig(IMX_PAD_SD3_DAT1, IMX_PAD_CFG_SD3_DAT1_SD3_DATA1);
+ ImxPadConfig(IMX_PAD_SD3_DAT2, IMX_PAD_CFG_SD3_DAT2_SD3_DATA2);
+ ImxPadConfig(IMX_PAD_SD3_DAT3, IMX_PAD_CFG_SD3_DAT3_SD3_DATA3);
+ ImxPadConfig(IMX_PAD_SD3_DAT4, IMX_PAD_CFG_SD3_DAT4_SD3_DATA4);
+ ImxPadConfig(IMX_PAD_SD3_DAT5, IMX_PAD_CFG_SD3_DAT5_SD3_DATA5);
+ ImxPadConfig(IMX_PAD_SD3_DAT6, IMX_PAD_CFG_SD3_DAT6_SD3_DATA6);
+ ImxPadConfig(IMX_PAD_SD3_DAT7, IMX_PAD_CFG_SD3_DAT7_SD3_DATA7);
+}
+
+/**
+ Initialize EHCI modules on the SOC and perform required pin-muxing.
+ This routine also initializes PHY0(OTG) and PHY1 (USBH1).
+**/
+VOID EhciInit ()
+{
+ // Pin-mux OTG Over Current
+ ImxPadConfig(IMX_PAD_KEY_COL4, IMX_PAD_CFG_KEY_COL4_USB_OTG_OC);
+
+ // Pin-mux and enable OTG power
+ ImxPadConfig(IMX_PAD_EIM_D22, IMX_PAD_CFG_EIM_DATA22_GPIO3_IO22_USB_OTG_PWR);
+ ImxGpioDirection(IMX_GPIO_BANK3, 22, IMX_GPIO_DIR_OUTPUT);
+ ImxGpioWrite(IMX_GPIO_BANK3, 22, IMX_GPIO_HIGH);
+
+ // Pin-mux and configure USB_OTG_ID as HOST!
+ ImxPadConfig(IMX_PAD_GPIO_1, IMX_PAD_CFG_GPIO01_USB_OTG_ID_HOST);
+
+ // Configure USB_OTG_ID pin
+ volatile IMX_IOMUXC_GPR_REGISTERS* IoMuxGprRegsPtr = (IMX_IOMUXC_GPR_REGISTERS*)IOMUXC_GPR_BASE_ADDRESS;
+ IMX_IOMUXC_GPR1_REG IoMuxGpr1Reg = { MmioRead32((UINTN)&IoMuxGprRegsPtr->GPR1) };
+ IoMuxGpr1Reg.USB_OTG_ID_SEL = IMX_IOMUXC_GPR1_USB_OTG_ID_SEL_GPIO_1;
+ MmioWrite32((UINTN)&IoMuxGprRegsPtr->GPR1, IoMuxGpr1Reg.AsUint32);
+
+ // Pin-mux and enable USBH1 power
+ ImxPadConfig(IMX_PAD_GPIO_0, IMX_PAD_CFG_GPIO0_GPIO1_IO0_USBH1_PWR);
+ ImxGpioDirection(IMX_GPIO_BANK1, 0, IMX_GPIO_DIR_OUTPUT);
+ ImxGpioWrite(IMX_GPIO_BANK1, 0, IMX_GPIO_HIGH);
+
+ // Initialize PHY0 (OTG)
+ ImxUsbPhyInit(IMX_USBPHY0);
+
+ // Initialize PHY1 (USBH1)
+ ImxUsbPhyInit(IMX_USBPHY1);
+}
+
+/**
+ Initialize I2C modules on the SOC and perform required pin-muxing
+**/
+VOID I2cInit ()
+{
+ // Enable 1.8V and 3.3V power rails for sensors connected to I2C1.
+ // The SENSOR_PWR_EN on EIM_EB3 line powers the pullups on I2c1.
+ ImxPadConfig (IMX_PAD_EIM_EB3, IMX_PAD_CFG_EIM_EB3_GPIO2_IO31);
+ ImxGpioDirection(IMX_GPIO_BANK2, 31, IMX_GPIO_DIR_OUTPUT);
+ ImxGpioWrite(IMX_GPIO_BANK2, 31, IMX_GPIO_HIGH); // set GPIO2_IO31 to 1
+ DEBUG ((DEBUG_INFO, "Mux IMX_PAD_EIM_EB3 to GPIO via Alt5 and set GPIO2_IO31 to 1\r\n"));
+
+ // Configure I2C1. EIM_D21 is I2C1_SCL and EIM_D28 is I2C1_SDA. Alt6, Alt1
+ ImxPadConfig (IMX_PAD_EIM_D21, IMX_PAD_CFG_EIM_D21_I2C1_SCL);
+ ImxPadConfig (IMX_PAD_EIM_D28, IMX_PAD_CFG_EIM_D28_I2C1_SDA);
+ DEBUG ((DEBUG_INFO, "I2C1 pin muxed via EIM D28,21\r\n"));
+
+ // I2C2 is used by GOP/Windows display driver. Do not configure I2C2 SCL via KEY_COL3, SDA via KEY_ROW3
+
+ // Configure I2C3 SCL via EIM_D17, SDA via EIM_D18. Inputs Alt6
+ ImxPadConfig (IMX_PAD_EIM_D17, IMX_PAD_CFG_EIM_D17_I2C3_SCL);
+ ImxPadConfig (IMX_PAD_EIM_D18, IMX_PAD_CFG_EIM_D18_I2C3_SDA);
+ DEBUG ((DEBUG_INFO, "I2C3 pin muxed EIM_D17, 18\r\n"));
+}
+
+/**
+ Initialize SPI modules on the SOC and perform required pin-muxing
+**/
+VOID SpiInit ()
+{
+ UINT32 RegValue;
+ // On Hummingboard only ESPI2 is exposed.
+ // Configure the return path for ECSPI2_MISO
+ RegValue = MmioRead32(IOMUXC_ECSPI2_MISO_SELECT_INPUT);
+ RegValue &= ~3;
+ RegValue |= (IMX_IOMUXC_ECSPI2_MISO_EIM_OE_B_ALT2 << 0);
+ MmioWrite32(IOMUXC_ECSPI2_MISO_SELECT_INPUT, RegValue);
+}
+
+/**
+ Initialize PCI Express module on the SOC and perform required pin-muxing
+**/
+VOID PcieInit ()
+{
+ // PCIe GPIO Reset
+ ImxPadConfig(IMX_PAD_SD4_DAT3, IMX_PAD_CFG_SD4_DATA3_GPIO2_IO11);
+ ImxGpioDirection(IMX_GPIO_BANK2, 11, IMX_GPIO_DIR_OUTPUT);
+ ImxGpioWrite(IMX_GPIO_BANK2, 11, IMX_GPIO_LOW);
+}
+
+/**
+ Initialize exposed GPIO pins on carrier board. By default some
+ pins are set to CMOS inputs while others are set to Schmitt
+ triggers. Normalize them all to Schmitt trigger inputs by setting
+ the hysteresis bit (16) in the pad ctl register.
+**/
+VOID GpioInit ()
+{
+ int i;
+ IMX_PAD gpioPins[] = {
+ IMX_PAD_ENET_RX_ER,
+ IMX_PAD_EIM_A22,
+ IMX_PAD_EIM_A21,
+ IMX_PAD_EIM_A20,
+ IMX_PAD_EIM_A19,
+ IMX_PAD_EIM_A18,
+ IMX_PAD_EIM_A17,
+ IMX_PAD_EIM_A16,
+ IMX_PAD_EIM_EB0,
+ IMX_PAD_EIM_EB1,
+ IMX_PAD_EIM_DA0,
+ IMX_PAD_EIM_DA1,
+ IMX_PAD_EIM_DA2,
+ IMX_PAD_EIM_DA3,
+ IMX_PAD_EIM_DA4,
+ IMX_PAD_EIM_DA5,
+ IMX_PAD_EIM_DA6,
+ IMX_PAD_EIM_DA7,
+ IMX_PAD_EIM_DA8,
+ IMX_PAD_EIM_DA9,
+ IMX_PAD_EIM_DA10,
+ IMX_PAD_EIM_DA11,
+ IMX_PAD_EIM_DA12,
+ IMX_PAD_EIM_DA13,
+ IMX_PAD_EIM_DA14,
+ IMX_PAD_EIM_DA15,
+ IMX_PAD_EIM_D26,
+ IMX_PAD_EIM_D27,
+ IMX_PAD_EIM_D30,
+ IMX_PAD_EIM_D31,
+ IMX_PAD_EIM_A24,
+ IMX_PAD_EIM_A23,
+ IMX_PAD_GPIO_16,
+ };
+
+ for (i = 0 ; i < sizeof(gpioPins)/sizeof(IMX_PAD) ; ++i) {
+ IMX_PAD pad = gpioPins[i];
+ MmioOr32 (
+ IMX_IOMUXC_BASE + _IMX_PAD_CTL_OFFSET(pad),
+ 1 << 16);
+ }
+}
+
+/**
+ Initalize the PWM controllers
+ PWM1 is exposed through Mikrobus header
+ Pinmux pad DISP0_DAT8 to (ALT2) PWM1_OUT
+**/
+VOID PwmInit ()
+{
+ ImxPadConfig(IMX_PAD_DISP0_DAT8, IMX_PAD_CFG_DISP0_DAT8_PWM1_OUT);
+}
+
+/**
+ Initalize the UART controllers
+**/
+VOID UartInit ()
+{
+ const IMX_CLK_GATE UartClockGatesToTurnOn[] = {
+ IMX_PLL3_MAIN_CLK, // IMX_UART_CLK_ENABLE,
+ IMX_UART_CLK_ROOT // UART_SERIAL_CLK_ENABLE,
+ };
+
+ // UARTs share same Clock: PLL3 (480 MHz) -> pll3_sw_clk -> CG -> /6 -> uart_clk_root = 80 MHz
+ ImxClkPwrSetClockGates(
+ UartClockGatesToTurnOn,
+ sizeof(UartClockGatesToTurnOn) / sizeof(UartClockGatesToTurnOn[0]),
+ IMX_CLOCK_GATE_STATE_ON);
+
+ // Configure pin mux for UART 1 and UART 3
+ ImxPadConfig (IMX_PAD_CSI0_DAT11, IMX_PAD_UART1_RX_DATA);
+ ImxPadConfig (IMX_PAD_CSI0_DAT10, IMX_PAD_UART1_TX_DATA);
+ ImxPadConfig (IMX_PAD_EIM_D25, IMX_PAD_UART3_RX_DATA);
+ ImxPadConfig (IMX_PAD_EIM_D24, IMX_PAD_UART3_TX_DATA);
+
+ SerialPortInitialize ();
+ SerialPortWrite (
+ (UINT8*)SERIAL_DEBUG_PORT_INIT_MSG,
+ (UINTN)sizeof(SERIAL_DEBUG_PORT_INIT_MSG));
+}
+
+/**
+ Initialize the TPM2 control area.
+
+Note:
+ This is temporary, and is normally done in TPM2 OPTEE device lib,
+ which will takle place as soon as the TreeDxe driver is enabled.
+**/
+VOID
+Tpm2AcpiControlAreaInit ()
+{
+ EFI_PHYSICAL_ADDRESS BaseAddress;
+ UINT32 BufferSize;
+ EFI_TPM2_ACPI_CONTROL_AREA *ControlArea;
+
+ BaseAddress = PcdGet64 (PcdTpm2AcpiBufferBase);
+ BufferSize = PcdGet32 (PcdTpm2AcpiBufferSize);
+
+ if ((BaseAddress == 0) || (BufferSize == 0)) {
+ //
+ // TPM not enabled
+ //
+ return;
+ }
+
+ ASSERT (BufferSize >= EFI_PAGE_SIZE * 3);
+
+ ControlArea = (EFI_TPM2_ACPI_CONTROL_AREA *)((UINTN)BaseAddress);
+ ZeroMem(ControlArea, sizeof(EFI_TPM2_ACPI_CONTROL_AREA));
+ BufferSize = EFI_PAGE_SIZE;
+ ControlArea->Command = (UINT64)((UINTN)(ControlArea + 1));
+ ControlArea->CommandSize = BufferSize;
+ ControlArea->Response = ControlArea->Command + BufferSize;
+ ControlArea->ResponseSize = BufferSize;
+}
+
+/**
+ Initalize LVDS
+**/
+VOID LvdsInit ()
+{
+ volatile IMX_CCM_REGISTERS *ccmRegisters = (IMX_CCM_REGISTERS *) IMX_CCM_BASE;
+
+ IMX_CCM_CCGR3_REG ccgr3 = (IMX_CCM_CCGR3_REG) MmioRead32((UINTN) &ccmRegisters->CCGR[3]);
+ ccgr3.ldb_di0_clk_enable = 0x3;
+ MmioWrite32((UINTN) &ccmRegisters->CCGR[3], ccgr3.AsUint32);
+
+ // initalize backlight pin
+ ImxPadConfig(IMX_PAD_SD4_DAT1, IMX_PAD_CFG_SD4_DATA1_GPIO2_IO09);
+ ImxGpioDirection(IMX_GPIO_BANK2, 9, IMX_GPIO_DIR_OUTPUT);
+ ImxGpioWrite(IMX_GPIO_BANK2, 9, IMX_GPIO_HIGH);
+}
+
+/**
+ Initialize controllers that must setup at the early stage for iMX6 Quad
+**/
+RETURN_STATUS
+ArmPlatformInitialize (
+ IN UINTN MpId
+ )
+{
+ if (!ArmPlatformIsPrimaryCore (MpId)) {
+ return RETURN_SUCCESS;
+ }
+
+ ImxClkPwrInit ();
+
+ // initialize default UEFI debug port early so we can use its debug output
+ SerialPortInitialize ();
+ SerialPortWrite (
+ (UINT8 *)SERIAL_DEBUG_PORT_INIT_MSG,
+ (UINTN)sizeof(SERIAL_DEBUG_PORT_INIT_MSG));
+
+ // Initialize timer early on because the following init path will be calling
+ // delay functions. PrePi.c calls ArmPlatformInitialize before it calls
+ // TimerConstructor to initialize the timer.
+ TimerConstructor ();
+
+ SdhcInit ();
+ EhciInit ();
+ EnetInit ();
+ I2cInit ();
+ SpiInit ();
+ PcieInit ();
+ SetupAudio ();
+ GpioInit ();
+ PwmInit ();
+
+ if (FeaturePcdGet(PcdLvdsEnable)) {
+ LvdsInit ();
+ }
+
+ Tpm2AcpiControlAreaInit ();
+
+ return RETURN_SUCCESS;
+}
+
+/**
+ Return the current Boot Mode
+
+ This function returns the boot reason on the platform
+
+**/
+EFI_BOOT_MODE
+ArmPlatformGetBootMode (
+ VOID
+ )
+{
+ return BOOT_WITH_FULL_CONFIGURATION;
+}
diff --git a/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Library/iMX6BoardLib/iMX6BoardLib.inf b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Library/iMX6BoardLib/iMX6BoardLib.inf
new file mode 100644
index 000000000000..2df33de7a9fa
--- /dev/null
+++ b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/Library/iMX6BoardLib/iMX6BoardLib.inf
@@ -0,0 +1,96 @@
+#/* @file
+#
+# Copyright (c) Microsoft Corporation. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#*/
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = iMX6BoardLib
+ FILE_GUID = 736343a0-1d96-11e0-aaaa-0002a5d5c51b
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = ArmPlatformLib
+ DEFINE BOARD_LIB_COMMON_DIR = Silicon/NXP/iMX6Pkg/Library/iMX6BoardLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/NXP/iMXPlatformPkg/iMXPlatformPkg.dec
+ Silicon/NXP/iMX6Pkg/iMX6Pkg.dec
+ Silicon/NXP/iMXPlatformPkg/iMXPlatformPkg.dec
+ Platform/Microsoft/OpteeClientPkg/OpteeClientPkg.dec
+
+[LibraryClasses]
+ IoLib
+ ArmLib
+ MemoryAllocationLib
+ SerialPortLib
+ iMX6ClkPwrLib
+ iMX6UsbPhyLib
+
+[Sources.common]
+ $(BOARD_LIB_COMMON_DIR)/iMX6BoardHelper.S | GCC
+ $(BOARD_LIB_COMMON_DIR)/iMX6BoardMem.c
+ $(BOARD_LIB_COMMON_DIR)/iMX6QBoardCoreDef.c
+ iMX6BoardInit.c
+
+[FeaturePcd]
+ giMX6TokenSpaceGuid.PcdGpuEnable
+ giMX6TokenSpaceGuid.PcdLvdsEnable
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdFdBaseAddress
+ gArmTokenSpaceGuid.PcdFdSize
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+
+ giMX6TokenSpaceGuid.PcdFrameBufferBase
+ giMX6TokenSpaceGuid.PcdFrameBufferSize
+
+ gArmTokenSpaceGuid.PcdSystemMemoryBase
+ gArmTokenSpaceGuid.PcdSystemMemorySize
+
+ gArmTokenSpaceGuid.PcdArmPrimaryCoreMask
+ gArmTokenSpaceGuid.PcdArmPrimaryCore
+
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+ giMX6TokenSpaceGuid.PcdSrcBase
+
+ giMXPlatformTokenSpaceGuid.PcdGpioBankMemoryRange
+
+ #
+ # TrustZone private memory (?Mb OPTEE + ?Mb PSCI)
+ # This memory is managed privately by the OpTEE OS.
+ # It must match OpTEE optee_os/core/arch/arm/plat-imx/platform_config.h:
+ # CFG_DDR_TEETZ_RESERVED_START & CFG_DDR_TEETZ_RESERVED_START
+ #
+ gOpteeClientPkgTokenSpaceGuid.PcdTrustZonePrivateMemoryBase
+ gOpteeClientPkgTokenSpaceGuid.PcdTrustZonePrivateMemorySize
+
+ #
+ # TrustZone shared memory
+ # This memory is manager by the normal world but shared with the OpTEE OS.
+ # It must match OpTEE optee_os/core/arch/arm/plat-imx/platform_config.h:
+ # CFG_SHMEM_START & CFG_SHMEM_SIZE
+ #
+ gOpteeClientPkgTokenSpaceGuid.PcdTrustZoneSharedMemoryBase
+ gOpteeClientPkgTokenSpaceGuid.PcdTrustZoneSharedMemorySize
+
+ #
+ # Temporary: TPM2 control area
+ #
+ gOpteeClientPkgTokenSpaceGuid.PcdTpm2AcpiBufferBase
+ gOpteeClientPkgTokenSpaceGuid.PcdTpm2AcpiBufferSize
+
--
2.16.2.gvfs.1.33.gf5370f1
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH edk2-platforms 3/4] Platform/SolidRun: Add Hummingboard ACPI tables
2018-07-22 1:30 [PATCH edk2-platforms 0/4] Import Solidrun Hummingboard Edge package Chris Co
2018-07-22 1:30 ` [PATCH edk2-platforms 1/4] Platform/Solidrun: Add Hummingboard SmBios Chris Co
2018-07-22 1:30 ` [PATCH edk2-platforms 2/4] Platform/Solidrun: Add Hummingboard Peripheral Initialization Chris Co
@ 2018-07-22 1:30 ` Chris Co
2018-07-22 1:30 ` [PATCH edk2-platforms 4/4] Platform/Solidrun: Add Hummingboard dsc and fdf files Chris Co
3 siblings, 0 replies; 8+ messages in thread
From: Chris Co @ 2018-07-22 1:30 UTC (permalink / raw)
To: edk2-devel@lists.01.org; +Cc: Michael D Kinney, Ard Biesheuvel, Leif Lindholm
This adds ACPI table support for Solidrun i.MX6 Hummingboard Edge.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Christopher Co <christopher.co@microsoft.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
---
Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/AcpiTables.inf | 51 +++
Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/DSDT.asl | 37 ++
Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Audio.inc | 66 +++
Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-AudioCodec.inc | 29 ++
Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Pwm.inc | 30 ++
Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Rhp.inc | 201 +++++++++
Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Sdhc.inc | 436 ++++++++++++++++++++
Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Spi.inc | 42 ++
Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Uart.inc | 197 +++++++++
Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Usb.inc | 410 ++++++++++++++++++
10 files changed, 1499 insertions(+)
diff --git a/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/AcpiTables.inf b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/AcpiTables.inf
new file mode 100644
index 000000000000..cd62287b9767
--- /dev/null
+++ b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/AcpiTables.inf
@@ -0,0 +1,51 @@
+## @file
+#
+# Copyright (c) Microsoft Corporation. All rights reserved.
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformAcpiTables
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+ MODULE_TYPE = USER_DEFINED
+ VERSION_STRING = 1.0
+ DEFINE COMMON_ACPI_DIR = Silicon/NXP/iMX6Pkg/AcpiTables
+
+[Sources]
+ DSDT.asl
+ $(COMMON_ACPI_DIR)/Csrt.aslc
+ $(COMMON_ACPI_DIR)/Dbg2.aslc
+ $(COMMON_ACPI_DIR)/Fadt.aslc
+ $(COMMON_ACPI_DIR)/Madt.aslc
+ $(COMMON_ACPI_DIR)/Mcfg.aslc
+ $(COMMON_ACPI_DIR)/Tpm2.aslc
+ $(COMMON_ACPI_DIR)/Spcr.aslc
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ Silicon/NXP/iMX6Pkg/iMX6Pkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ Silicon/NXP/iMXPlatformPkg/iMXPlatformPkg.dec
+ Platform/Microsoft/OpteeClientPkg/OpteeClientPkg.dec
+
+[FixedPcd]
+ giMX6TokenSpaceGuid.PcdPcieHostConfigBase
+ giMX6TokenSpaceGuid.PcdPcieDeviceConfigBase
+ gArmPlatformTokenSpaceGuid.PcdCoreCount
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ giMXPlatformTokenSpaceGuid.PcdKdUartInstance
+ gOpteeClientPkgTokenSpaceGuid.PcdTpm2AcpiBufferBase
+ gOpteeClientPkgTokenSpaceGuid.PcdTpm2AcpiBufferSize
diff --git a/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/DSDT.asl b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/DSDT.asl
new file mode 100644
index 000000000000..e3c8b3f1a69e
--- /dev/null
+++ b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/DSDT.asl
@@ -0,0 +1,37 @@
+/*
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*/
+#define SOC_TYPE 0x00000063 // iMX6 Quad
+
+DefinitionBlock ("DSDT.aml", "DSDT", 5, "MSFT", "EDK2", 1)
+{
+ Scope (\_SB_)
+ {
+ include("Dsdt-Common.inc")
+ include("Dsdt-Platform.inc")
+ include("Dsdt-Gpio.inc")
+ include("Dsdt-Gfx.inc")
+ include("Dsdt-Usb.inc")
+ include("Dsdt-PCIe.inc")
+ include("Dsdt-Sdhc.inc")
+ include("Dsdt-Enet.inc")
+ include("Dsdt-Audio.inc")
+ include("Dsdt-AudioCodec.inc")
+ include("Dsdt-Uart.inc")
+ include("Dsdt-I2c.inc")
+ include("Dsdt-Spi.inc")
+ include("Dsdt-Rhp.inc")
+ include("Dsdt-Pwm.inc")
+ include("Dsdt-TrEE.inc")
+ } // \_SB_
+}
diff --git a/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Audio.inc b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Audio.inc
new file mode 100644
index 000000000000..18aabac8b4de
--- /dev/null
+++ b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Audio.inc
@@ -0,0 +1,66 @@
+/*
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*/
+
+Device (SSI1)
+{
+ Name (_HID, "FSCL000A")
+ Name (_UID, 0x1)
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ MEMORY32FIXED(ReadWrite, 0x02028000, 0x4000, )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 78 }
+ })
+ Return(RBUF)
+ }
+}
+
+Device (SSI2)
+{
+ Name (_HID, "FSCL000A")
+ Name (_UID, 0x2)
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ MEMORY32FIXED(ReadWrite, 0x0202C000, 0x4000, )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 79 }
+ })
+ Return(RBUF)
+ }
+}
+
+Device (SSI3)
+{
+ Name (_HID, "FSCL000A")
+ Name (_UID, 0x3)
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ MEMORY32FIXED(ReadWrite, 0x02030000, 0x4000, )
+ MEMORY32FIXED(ReadWrite, 0x021d8000, 0x38, )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 80 }
+ MsftFunctionConfig(Shared, PullDown, 0, "\\_SB.SSI3", 0, ResourceConsumer, ) { 7, 5 }
+ })
+ Return(RBUF)
+ }
+}
diff --git a/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-AudioCodec.inc b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-AudioCodec.inc
new file mode 100644
index 000000000000..73374b24d616
--- /dev/null
+++ b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-AudioCodec.inc
@@ -0,0 +1,29 @@
+/*
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*/
+
+Device (ACDK)
+{
+ Name (_HID, "SGTL5000")
+ Name (_UID, 0x0)
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ I2CSerialBus(0x0a, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.I2C1", 0, ResourceConsumer)
+ })
+ Return(RBUF)
+ }
+}
diff --git a/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Pwm.inc b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Pwm.inc
new file mode 100644
index 000000000000..f6566c75a4cb
--- /dev/null
+++ b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Pwm.inc
@@ -0,0 +1,30 @@
+/*
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*/
+
+Device (PWM1)
+{
+ Name (_HID, "FSCL000E")
+ Name (_UID, 0x1)
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ MEMORY32FIXED(ReadWrite, 0x02080000, 0x4000, )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 115 }
+ })
+ Return(RBUF)
+ }
+}
diff --git a/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Rhp.inc b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Rhp.inc
new file mode 100644
index 000000000000..fdba2e535058
--- /dev/null
+++ b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Rhp.inc
@@ -0,0 +1,201 @@
+/*
+* iMX6 Quad Resource Hub Proxy
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*/
+
+Device(RHPX)
+{
+ Name(_HID, "MSFT8000")
+ Name(_CID, "MSFT8000")
+ Name(_UID, 1)
+
+ Name(_CRS, ResourceTemplate()
+ {
+ // Index 0
+ I2CSerialBus(0xFFFF,, 0,, "\\_SB.I2C3",,,,)
+
+ // Index 1
+ SPISerialBus( // SCKL
+ // MOSI
+ // MISO
+ // CE0
+ 0, // Device selection (CE0)
+ PolarityLow, // Device selection polarity
+ FourWireMode, // wiremode
+ 8, // databit len
+ ControllerInitiated, // slave mode
+ 4000000, // connection speed
+ ClockPolarityLow, // clock polarity
+ ClockPhaseFirst, // clock phase
+ "\\_SB.SPI2", // ResourceSource: SPI bus controller name
+ 0, // ResourceSourceIndex
+ // Resource usage
+ // DescriptorName: creates name for offset of resource descriptor
+ ) // Vendor Data
+
+ // SPDIF_IN - GPIO1_IO24 PAD_ENET_RX_ER
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 24 } // 0 * 32 + 24
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 24 }
+
+ // DISP1_DATA17 - GPIO2_IO16 PAD_EIM_ADDR22
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 48 } // 1 * 32 + 16
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 48 }
+
+ // DISP1_DATA16 - GPIO2_IO17 PAD_EIM_ADDR21
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 49 } // 1 * 32 + 17
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 49 }
+
+ // DISP1_DATA15 - GPIO2_IO18 PAD_EIM_ADDR20
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 50 } // 1 * 32 + 18
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 50 }
+
+ // DISP1_DATA14 - GPIO2_IO19 PAD_EIM_ADDR19
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 51 } // 1 * 32 + 19
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 51 }
+
+ // DISP1_DATA13 - GPIO2_IO20 PAD_EIM_ADDR18
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 52 } // 1 * 32 + 20
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 52 }
+
+ // DISP1_DATA12 - GPIO2_IO21 PAD_EIM_ADDR17
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 53 } // 1 * 32 + 21
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 53 }
+
+ // DI1_DISP_CLK - GPIO2_IO22 PAD_EIM_ADDR16
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 54 } // 1 * 32 + 22
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 54 }
+
+ // DISP1_DATA11 - GPIO2_IO28 PAD_EIM_EB0
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 60 } // 1 * 32 + 28
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 60 }
+
+ // DISP1_DATA10 - GPIO2_IO29 PAD_EIM_EB1
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 61 } // 1 * 32 + 29
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 61 }
+
+ // DISP1_DATA09 - GPIO3_IO00 PAD_EIM_AD00
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 64 } // 2 * 32 + 0
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 64 }
+
+ // DISP1_DATA08 - GPIO3_IO01 PAD_EIM_AD01
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 65 } // 2 * 32 + 1
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 65 }
+
+ // DISP1_DATA07 - GPIO3_IO02 PAD_EIM_AD02
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 66 } // 2 * 32 + 2
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 66 }
+
+ // DISP1_DATA06 - GPIO3_IO03 PAD_EIM_AD03
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 67 } // 2 * 32 + 3
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 67 }
+
+ // DISP1_DATA05 - GPIO3_IO04 PAD_EIM_AD04
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 68 } // 2 * 32 + 4
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 68 }
+
+ // DISP1_DATA04 - GPIO3_IO05 PAD_EIM_AD05
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 69 } // 2 * 32 + 5
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 69 }
+
+ // DISP1_DATA03 - GPIO3_IO06 PAD_EIM_AD06
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 70 } // 2 * 32 + 6
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 70 }
+
+ // DISP1_DATA02 - GPIO3_IO07 PAD_EIM_AD07
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 71 } // 2 * 32 + 7
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 71 }
+
+ // DISP1_DATA01 - GPIO3_IO08 PAD_EIM_AD08
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 72 } // 2 * 32 + 8
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 72 }
+
+ // DISP1_DATA00 - GPIO3_IO09 PAD_EIM_AD09
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 73 } // 2 * 32 + 9
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 73 }
+
+ // DI1_PIN15 - GPIO3_IO10 PAD_EIM_AD10
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 74 } // 2 * 32 + 10
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 74 }
+
+ // DI1_PIN02 - GPIO3_IO11 PAD_EIM_AD11
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 75 } // 2 * 32 + 11
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 75 }
+
+ // DI1_PIN03 - GPIO3_IO12 PAD_EIM_AD12
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 76 } // 2 * 32 + 12
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 76 }
+
+ // DI1_D0_CS - GPIO3_IO13 PAD_EIM_AD13
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 77 } // 2 * 32 + 13
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 77 }
+
+ // DI1_D1_CS - GPIO3_IO14 PAD_EIM_AD14
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 78 } // 2 * 32 + 14
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 78 }
+
+ // DI1_PIN01 - GPIO3_IO15 PAD_EIM_AD15
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 79 } // 2 * 32 + 15
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 79 }
+
+ // DISP1_DATA22 - GPIO3_IO26 PAD_EIM_DATA26
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 90 } // 2 * 32 + 26
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 90 }
+
+ // DISP1_DATA23 - GPIO3_IO27 PAD_EIM_DATA27
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 91 } // 2 * 32 + 27
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 91 }
+
+ // DISP1_DATA21 - GPIO3_IO30 PAD_EIM_DATA30
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 94 } // 2 * 32 + 20
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 94 }
+
+ // DISP1_DATA20 - GPIO3_IO31 PAD_EIM_DATA31
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 95 } // 2 * 32 + 31
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 95 }
+
+ // DISP1_DATA19 - GPIO5_IO04 PAD_EIM_ADDR24
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 132 } // 4 * 32 + 4
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 132 }
+
+ // DISP1_DATA18 - GPIO6_IO06 PAD_EIM_ADDR23
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 166 } // 5 * 32 + 6
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 166 }
+
+ // SPDIF_OUT - GPIO7_IO12 PAD_GPIO17
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 204 } // 6 * 32 + 12
+ GpioInt(Edge, ActiveBoth, Shared, PullUp, 0, "\\_SB.GPIO",) { 204 }
+ })
+
+ Name(_DSD, Package()
+ {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package()
+ {
+ // I2C3
+ Package(2) { "bus-I2C-I2C3", Package() { 0 }},
+
+ // SPI 2
+ Package(2) { "bus-SPI-SPI2", Package() { 1 }}, // Index 1
+ Package(2) { "SPI2-MinClockInHz", 115 }, // 115 Hz
+ Package(2) { "SPI2-MaxClockInHz", 12000000 }, // 12 MHz
+ Package(2) { "SPI2-SupportedDataBitLengths", Package() { 8,16,32 }}, // Data bit length
+
+ // GPIO Pin Count and supported drive modes
+ Package (2) { "GPIO-PinCount", 206 },
+ Package (2) { "GPIO-UseDescriptorPinNumbers", 1 },
+
+ // InputHighImpedance, InputPullUp, InputPullDown, OutputCmos
+ Package (2) { "GPIO-SupportedDriveModes", 0xf },
+ }
+ })
+}
diff --git a/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Sdhc.inc b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Sdhc.inc
new file mode 100644
index 000000000000..3a46d251f931
--- /dev/null
+++ b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Sdhc.inc
@@ -0,0 +1,436 @@
+/*
+* Description: iMX6 Quad Ultra Secured Digital Host Controllers (uSDHC)
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*/
+
+// uSDHC1: WLAN SDIO Socket
+Device (SDH1)
+{
+ Name (_HID, "FSCL0008")
+ Name (_UID, 0x1)
+
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+
+ Name (_S1D, 0x1)
+ Name (_S2D, 0x1)
+ Name (_S3D, 0x1)
+ Name (_S4D, 0x1)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate () {
+ MEMORY32FIXED(ReadWrite, 0x02190000, 0x4000, )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 54 }
+ })
+ Return(RBUF)
+ }
+
+ Name (_DSD, Package()
+ {
+ ToUUID ("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301"),
+ Package ()
+ {
+ Package (2) { "BaseClockFrequencyHz", 198000000 }, // SDHC Base/Input Clock: 198MHz
+ Package (2) { "Regulator1V8Exist", 0 }, // 1.8V Switching External Circuitry: Not-Implemented
+ Package (2) { "SlotCount", 1 }, // Number of SD/MMC slots connected on the bus: 1
+ Package (2) { "RegisterBasePA", 0x02190000 } // Register base physical address
+ }
+ })
+
+ Device (SD0)
+ {
+ Method (_ADR)
+ {
+ Return (0)
+ }
+
+ Method (_RMV)
+ {
+ Return (0)
+ }
+ }
+}
+
+// uSDHC2: SDCard Socket
+Device (SDH2)
+{
+ Name (_HID, "FSCL0008")
+ Name (_UID, 0x2)
+
+ Method (_STA) {
+ Return(0xf)
+ }
+
+ Name (_S1D, 0x1)
+ Name (_S2D, 0x1)
+ Name (_S3D, 0x1)
+ Name (_S4D, 0x1)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate () {
+ MEMORY32FIXED(ReadWrite, 0x02194000, 0x4000, )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 55 }
+ })
+ Return(RBUF)
+ }
+
+ Name (_DSD, Package()
+ {
+ ToUUID ("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301"),
+ Package ()
+ {
+ Package (2) { "BaseClockFrequencyHz", 198000000 }, // SDHC Base/Input Clock: 198MHz
+ // ** Temporary disable circuitry until stability is investigated. **
+ Package (2) { "Regulator1V8Exist", 0 }, // 1.8V Switching External Circuitry: Implemented
+ Package (2) { "SlotCount", 1 }, // Number of SD/MMC slots connected on the bus: 1
+ Package (2) { "RegisterBasePA", 0x02194000 } // Register base physical address
+ }
+ })
+
+ OperationRegion (GPI4, SystemMemory, 0x020A8000, 0x4)
+
+ // SD2_CLK
+ // IOMUXC_SW_MUX_CTL_PAD_SD2_CLK
+ OperationRegion (MXCK, SystemMemory, 0x020E0354, 0x4)
+
+ // SD2_CMD
+ // IOMUXC_SW_PAD_CTL_PAD_SD2_CMD
+ OperationRegion (PDCD, SystemMemory, 0x020E0740, 0x4)
+ // IOMUXC_SW_MUX_CTL_PAD_SD2_CMD
+ OperationRegion (MXCD, SystemMemory, 0x020E0358, 0x4)
+
+ // SD2_DATA0
+ // IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0
+ OperationRegion (PDD0, SystemMemory, 0x020E0368, 0x4)
+ // IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0
+ OperationRegion (MXD0, SystemMemory, 0x020E0054, 0x4)
+
+ // SD2_DATA1
+ // IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1
+ OperationRegion (PDD1, SystemMemory, 0x020E0360, 0x4)
+ // IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1
+ OperationRegion (MXD1, SystemMemory, 0x020E004C, 0x4)
+
+ // SD2_DATA2
+ // IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2
+ OperationRegion (PDD2, SystemMemory, 0x020E0364, 0x4)
+ // IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2
+ OperationRegion (MXD2, SystemMemory, 0x020E0050, 0x4)
+
+ // SD2_DATA3
+ // IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3
+ OperationRegion (PDD3, SystemMemory, 0x020E0744, 0x4)
+ // IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3
+ OperationRegion (MXD3, SystemMemory, 0x020E035C, 0x4)
+
+ Field (GPI4, DWordAcc, NoLock, Preserve)
+ {
+ G4DR, 32, // GPIOx_DR
+ }
+
+ Field (MXCK, DWordAcc, NoLock, Preserve)
+ {
+ MCCK, 32, // IOMUXC_SW_MUX_CTL_PAD_SD2_CLK
+ }
+
+ Field (MXCD, DWordAcc, NoLock, Preserve)
+ {
+ MCCD, 32, // IOMUXC_SW_MUX_CTL_PAD_SD2_CMD
+ }
+
+ Field (MXD0, DWordAcc, NoLock, Preserve)
+ {
+ MCD0, 32, // IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0
+ }
+
+ Field (MXD1, DWordAcc, NoLock, Preserve)
+ {
+ MCD1, 32, // IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1
+ }
+
+ Field (MXD2, DWordAcc, NoLock, Preserve)
+ {
+ MCD2, 32, // IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2
+ }
+
+ Field (MXD3, DWordAcc, NoLock, Preserve)
+ {
+ MCD3, 32, // IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3
+ }
+
+ Field (PDCD, DWordAcc, NoLock, Preserve)
+ {
+ PCCD, 32, // IOMUXC_SW_PAD_CTL_PAD_SD2_CMD
+ }
+
+ Field (PDD0, DWordAcc, NoLock, Preserve)
+ {
+ PCD0, 32, // IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0
+ }
+
+ Field (PDD1, DWordAcc, NoLock, Preserve)
+ {
+ PCD1, 32, // IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1
+ }
+
+ Field (PDD2, DWordAcc, NoLock, Preserve)
+ {
+ PCD2, 32, // IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2
+ }
+
+ Field (PDD3, DWordAcc, NoLock, Preserve)
+ {
+ PCD3, 32, // IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3
+ }
+
+ // Device Specific Method takes 4 args:
+ // Arg0 : Buffer containing a UUID [16 bytes]
+ // Arg1 : Integer containing the Revision ID
+ // Arg2 : Integer containing the Function Index
+ // Arg3 : Package that contains function-specific arguments
+ Function(_DSM,{BuffObj, IntObj},{BuffObj, IntObj, IntObj, PkgObj})
+ {
+ Name (REG, 0x0);
+
+ // UUID selector
+ switch (ToBuffer (Arg0))
+ {
+ // SDHC interface identifier
+ case (ToUUID ("D4AC1EA1-BC53-416A-9B8C-481FEE75365C"))
+ {
+ // Function selector
+ switch (Arg2)
+ {
+ // Function 0: Return supported functions, based on revision
+ case (0)
+ {
+ // Version selector
+ switch (Arg1)
+ {
+ // Revision0: functions {0,1,2} supported
+ case (0) { Return (Buffer (){0x07}); }
+ default { Return (Buffer (){0x01}); }
+ }
+ }
+
+ // GPIO4_IO30 is connected to the SDSocket power MOSFET Gate
+ // Setting to HIGH turns-off power, while LOW turns-on power
+
+ // Function 1: SDSocket Power-On
+ case (1)
+ {
+ // Power-On the SD VDD
+ Store (G4DR, REG);
+ And (REG, 0xBFFFFFFF, REG);
+ Store (REG, G4DR);
+
+ // Connect all SD2 pins by switching them to SD and
+ // enable the pull-up resistor for CMD/DAT[0:3]
+
+ // SD2_CLK
+ Store (MCCK, REG);
+ And (REG, 0xF8, REG); // ALT0 SD2_CLK
+ Store (REG, MCCK);
+
+ // SD2_CMD
+ Store (MCCD, REG);
+ And (REG, 0xF8, REG); // ALT0 SD2_CMD
+ Store (REG, MCCD);
+
+ Store (PCCD, REG);
+ Or (REG, 0x1000, REG);
+ Store (REG, PCCD);
+
+ // SD2_DATA0
+ Store (MCD0, REG);
+ And (REG, 0xF8, REG); // ALT0 SD2_DATA0
+ Store (REG, MCD0);
+
+ Store (PCD0, REG);
+ Or (REG, 0x1000, REG);
+ Store (REG, PCD0);
+
+ // SD2_DATA1
+ Store (MCD1, REG);
+ And (REG, 0xF8, REG); // ALT0 SD2_DATA1
+ Store (REG, MCD1);
+
+ Store (PCD1, REG);
+ Or (REG, 0x1000, REG);
+ Store (REG, PCD1);
+
+ // SD2_DATA2
+ Store (MCD2, REG);
+ And (REG, 0xF8, REG); // ALT0 SD2_DATA2
+ Store (REG, MCD2);
+
+ Store (PCD2, REG);
+ Or (REG, 0x1000, REG);
+ Store (REG, PCD2);
+
+ // SD2_DATA3
+ Store (MCD3, REG);
+ And (REG, 0xF8, REG); // ALT0 SD2_DATA3
+ Store (REG, MCD3);
+
+ Store (PCD3, REG);
+ Or (REG, 0x1000, REG);
+ Store (REG, PCD3);
+
+ Return (0);
+ }
+
+ // Function 2: SDSocket Power-Off
+ case (2)
+ {
+ // Power-Off the SD VDD
+ Store (G4DR, REG);
+ Or (REG, 0x40000000, REG); // Set GPIO4_IO30 value
+ Store (REG, G4DR);
+
+ // Disconnect all SD2 pins by switching them to GPIO Input
+ // and disable the pull-up resistor on CMD/DAT[0:3]
+
+ // SD2_CLK
+ Store (MCCK, REG);
+ Or (REG, 0x5, REG); // ALT5 GPIO1_IO10
+ Store (REG, MCCK);
+
+ // SD2_CMD
+ Store (MCCD, REG);
+ Or (REG, 0x5, REG); // ALT5 GPIO1_IO11
+ Store (REG, MCCD);
+
+ Store (PCCD, REG);
+ And (REG, 0xEFFF, REG);
+ Store (REG, PCCD);
+
+ // SD2_DATA0
+ Store (MCD0, REG);
+ Or (REG, 0x5, REG); // ALT5 GPIO1_IO15
+ Store (REG, MCD0);
+
+ Store (PCD0, REG);
+ And (REG, 0xEFFF, REG);
+ Store (REG, PCD0);
+
+ // SD2_DATA1
+ Store (MCD1, REG);
+ Or (REG, 0x5, REG); // ALT5 GPIO1_IO14
+ Store (REG, MCD1);
+
+ Store (PCD1, REG);
+ And (REG, 0xEFFF, REG);
+ Store (REG, PCD1);
+
+ // SD2_DATA2
+ Store (MCD2, REG);
+ Or (REG, 0x5, REG); // ALT5 GPIO1_IO13
+ Store (REG, MCD2);
+
+ Store (PCD2, REG);
+ And (REG, 0xEFFF, REG);
+ Store (REG, PCD2);
+
+ // SD2_DATA3
+ Store (MCD3, REG);
+ Or (REG, 0x5, REG); // ALT5 GPIO1_IO12
+ Store (REG, MCD3);
+
+ Store (PCD3, REG);
+ And (REG, 0xEFFF, REG);
+ Store (REG, PCD3);
+
+ Return (0);
+ }
+
+ default { Return (Buffer (){0}); }
+ } // Function
+ } // {D4AC1EA1-BC53-416A-9B8C-481FEE75365C}
+
+ default { Return (Buffer (){0}); }
+ } // UUID
+ } // _DSM
+
+ Device (SD0)
+ {
+ Method (_ADR)
+ {
+ Return (0)
+ }
+
+ // Despite the SDCard is a removal device, UWF requires the
+ // boot device to be non-removable. This is required for the
+ // Windows SDCard boot scenario with UWF enabled.
+ Method (_RMV)
+ {
+ Return (0)
+ }
+ }
+}
+
+// uSDHC3: eMMC
+Device (SDH3)
+{
+ Name (_HID, "FSCL0008")
+ Name (_UID, 0x3)
+
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+
+ Name (_S1D, 0x1)
+ Name (_S2D, 0x1)
+ Name (_S3D, 0x1)
+ Name (_S4D, 0x1)
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate () {
+ MEMORY32FIXED(ReadWrite, 0x02198000, 0x4000, )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 56 }
+ })
+ Return(RBUF)
+ }
+
+ Name (_DSD, Package()
+ {
+ ToUUID ("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301"),
+ Package ()
+ {
+ Package (2) { "BaseClockFrequencyHz", 198000000 }, // SDHC Base/Input Clock: 198MHz
+ Package (2) { "Regulator1V8Exist", 0 }, // 1.8V Switching External Circuitry: N/A
+ Package (2) { "SlotCount", 1 }, // Number of SD/MMC slots connected on the bus: 1
+ Package (2) { "RegisterBasePA", 0x02198000 } // Register base physical address
+ }
+ })
+
+ Device (MMC0)
+ {
+ Method (_ADR)
+ {
+ Return (0)
+ }
+
+ // eMMC is non-removable
+ Method (_RMV)
+ {
+ Return (0)
+ }
+ }
+}
diff --git a/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Spi.inc b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Spi.inc
new file mode 100644
index 000000000000..211e4b498194
--- /dev/null
+++ b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Spi.inc
@@ -0,0 +1,42 @@
+/*
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*/
+
+Device (SPI2)
+{
+ Name (_HID, "FSCL0005")
+ Name (_UID, 0x2)
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ Name (RBUF, ResourceTemplate ()
+ {
+ MEMORY32FIXED(ReadWrite, 0x0200C000, 0x4000, )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 64 }
+
+ // CS0 (PAD_EIM_RW) GPIO2_IO26
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 58 }
+ // CS1 (PAD_EIM_LBA) GPIO2_IO27
+ GpioIO(Shared, PullUp, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer, , ) { 59 }
+
+ // MISO: PAD_EIM_OE_B (GPIO2_IO25) Alt2
+ // MOSI: PAD_EIM_CS1_B (GPIO2_IO24) Alt2
+ // SCLK: PAD_EIM_CS0_B (GPIO2_IO23) Alt2
+ MsftFunctionConfig(Exclusive, PullDown, IMX_ALT2, "\\_SB.GPIO", 0, ResourceConsumer, ) { 57, 56, 55 }
+ })
+ Return(RBUF)
+ }
+}
diff --git a/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Uart.inc b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Uart.inc
new file mode 100644
index 000000000000..0f73ee5d4b08
--- /dev/null
+++ b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Uart.inc
@@ -0,0 +1,197 @@
+/*
+* Description: iMX6 Quad UART Controllers
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*/
+
+Device (UAR1)
+{
+ Name (_HID, "FSCL0006")
+ Name (_UID, 0x1)
+ Name (_DDN, "UART1")
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ MEMORY32FIXED(ReadWrite, 0x02020000, 0x4000, )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Shared) { 58 }
+
+ // UART1_TX_DATA - CSI0_DAT10 - GPIO5_IO28 - 156
+ // UART1_RX_DATA - CSI0_DAT11 - GPIO5_IO29 - 157
+ MsftFunctionConfig(Exclusive, PullUp, IMX_ALT3, "\\_SB.GPIO", 0, ResourceConsumer, ) { 156, 157 }
+
+ // DMA channel 2, SDMA_REQ_UART1_RX for UART1 RX DMA
+ FixedDMA(SDMA_REQ_UART1_RX, 2, Width8Bit, )
+ // DMA channel 1, SDMA_REQ_UART1_TX for UART1 TX DMA
+ FixedDMA(SDMA_REQ_UART1_TX, 1, Width8Bit, )
+
+ UARTSerialBus(
+ 115200,
+ DataBitsEight,
+ StopBitsOne,
+ 0, // LinesInUse
+ LittleEndian,
+ ParityTypeNone,
+ FlowControlNone,
+ 0,
+ 0,
+ "\\_SB.CPU0",
+ 0,
+ ResourceConsumer,
+ ,)
+ })
+ Return(RBUF)
+ }
+}
+
+Device (UAR2)
+{
+ Name (_HID, "FSCL0007")
+ Name (_UID, 0x2)
+ Name (_DDN, "UART2")
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ MEMORY32FIXED(ReadWrite, 0x021E8000, 0x4000, )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 59 }
+
+ // DMA channel 4, SDMA_REQ_UART2_RX for UART2 RX DMA
+ FixedDMA(SDMA_REQ_UART2_RX, 4, Width8Bit, )
+ // DMA channel 3, SDMA_REQ_UART2_TX for UART2 TX DMA
+ FixedDMA(SDMA_REQ_UART2_TX, 3, Width8Bit, )
+
+ // UART2_TX_DATA - SD4_DAT7 - GPIO2_IO15 - 47
+ // UART2_RX_DATA - SD4_DAT4 - GPIO2_IO12 - 44
+ // UART2_CTS_B - SD4_DAT6 - GPIO2_IO14 - 46
+ // UART2_RTSB is not pinned out because it is connected to USB
+ MsftFunctionConfig(Exclusive, PullUp, IMX_ALT2, "\\_SB.GPIO", 0, ResourceConsumer, ) { 44, 46, 47 }
+
+ UARTSerialBus(
+ 115200,
+ DataBitsEight,
+ StopBitsOne,
+ 0xC0, // LinesInUse
+ LittleEndian,
+ ParityTypeNone,
+ FlowControlNone,
+ 0,
+ 0,
+ "\\_SB.CPU0",
+ 0,
+ ResourceConsumer,
+ ,)
+ })
+ Return(RBUF)
+ }
+}
+
+Device (UAR3)
+{
+ Name (_HID, "FSCL0007")
+ Name (_UID, 0x3)
+ Name (_DDN, "UART3")
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ MEMORY32FIXED(ReadWrite, 0x021EC000, 0x4000, )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 60 }
+
+ // DMA channel 6, SDMA_REQ_UART3_RX for UART3 RX DMA
+ FixedDMA(SDMA_REQ_UART3_RX, 6, Width8Bit, )
+ // DMA channel 5, SDMA_REQ_UART3_TX for UART3 TX DMA
+ FixedDMA(SDMA_REQ_UART3_TX, 5, Width8Bit, )
+
+ // UART3_TX - EIM_D24 - GPIO3_IO24 - 88
+ // UART3_RX - EIM_D25 - GPIO3_IO25 - 89
+ MsftFunctionConfig(Exclusive, PullUp, IMX_ALT2, "\\_SB.GPIO", 0, ResourceConsumer, ) { 88, 89 }
+
+ UARTSerialBus(
+ 115200,
+ DataBitsEight,
+ StopBitsOne,
+ 0, // LinesInUse
+ LittleEndian,
+ ParityTypeNone,
+ FlowControlNone,
+ 0,
+ 0,
+ "\\_SB.CPU0",
+ 0,
+ ResourceConsumer,
+ ,)
+ })
+ Return(RBUF)
+ }
+}
+
+// Connected to bluetooth module
+Device (UAR4)
+{
+ Name (_HID, "FSCL0007")
+ Name (_UID, 0x4)
+ Name (_DDN, "UART4")
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ MEMORY32FIXED(ReadWrite, 0x021F0000, 0x4000, )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 61 }
+
+ // DMA channel 8, SDMA_REQ_UART4_RX for UART4 RX DMA
+ FixedDMA(SDMA_REQ_UART4_RX, 8, Width8Bit, )
+ // DMA channel 7, SDMA_REQ_UART4_TX for UART4 TX DMA
+ FixedDMA(SDMA_REQ_UART4_TX, 7, Width8Bit, )
+
+ // UART4_TX_DATA - CSI0_DAT12 - GPIO5_IO30 - 158
+ // UART4_RX_DATA - CSI0_DAT13 - GPIO5_IO31 - 159
+ MsftFunctionConfig(Exclusive, PullUp, IMX_ALT3, "\\_SB.GPIO", 0, ResourceConsumer, ) { 158, 159 }
+
+ // UART4_RTS_B - CSI0_DAT16 - GPIO6_IO02 - 162
+ // UART4_CTS_B - CSI0_DAT17 - GPIO6_IO03 - 163
+ MsftFunctionConfig(Exclusive, PullUp, IMX_ALT3, "\\_SB.GPIO", 0, ResourceConsumer, ) { 162, 163 }
+ })
+ Return(RBUF)
+ }
+}
+
+Device (UAR5)
+{
+ Name (_HID, "FSCL0007")
+ Name (_UID, 0x5)
+ Name (_DDN, "UART5")
+ Method (_STA)
+ {
+ Return(0)
+ }
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ MEMORY32FIXED(ReadWrite, 0x021F4000, 0x4000, )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 62 }
+
+ // DMA channel 10, SDMA_REQ_UART5_RX for UART5 RX DMA
+ FixedDMA(SDMA_REQ_UART5_RX, 10, Width8Bit, )
+ // DMA channel 9, SDMA_REQ_UART5_TX for UART5 TX DMA
+ FixedDMA(SDMA_REQ_UART5_TX, 9, Width8Bit, )
+ })
+ Return(RBUF)
+ }
+}
diff --git a/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Usb.inc b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Usb.inc
new file mode 100644
index 000000000000..23d9c499f640
--- /dev/null
+++ b/Platform/SolidRun/HummingboardEdge_iMX6Q_2GB/AcpiTables/Dsdt-Usb.inc
@@ -0,0 +1,410 @@
+/*
+* Description: iMX6 Quad EHCI USB Controllers
+*
+* Copyright (c) Microsoft Corporation. All rights reserved.
+*
+* This program and the accompanying materials
+* are licensed and made available under the terms and conditions of the BSD License
+* which accompanies this distribution. The full text of the license may be found at
+* http://opensource.org/licenses/bsd-license.php
+*
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*/
+
+Device(URS0)
+{
+ Name(_HID, "PNP0C90")
+ Name(_UID, 0x0)
+
+ // URS requires device to at least be wake-able from D2 state
+ // WDF also requires that _DSW (enable & disable wake ability) to be present
+ Name(_S0W, 0x3)
+ Name(_PRW, Package() {0,0})
+ Method(_DSW, 0x3, NotSerialized) {
+
+ }
+
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ // Controller register address space. URS driver would add 0x0100
+ // offset for host mode
+ MEMORY32FIXED(ReadWrite, 0x02184000, 0x200, )
+
+ // USB_OTG_ID pin, needs to be declared as *Wake as this device is
+ // expected to be wakable. The USB PHY is capable to detect
+ // USB ID changes but the interrupt cannot be acknowledge
+ // and the behaviour is undefined based on NXP feedback. So
+ // the the only way to reliably detect USB ID changed is to
+ // either to share interrupts or assign a GPIO to detect.
+ // The URS driver does not properly handle level sensitive
+ // interrupts which can lead to an interrupt storm. Therefore we use
+ // an edge sensitive GPIO interrupt.
+ //
+ // USB_OTG_ID connected to GPIO_1 (GPIO1_IO01). Use 1ms debounce.
+ GpioInt (Edge, ActiveBoth, SharedAndWake, PullDefault, 100, "\\_SB.GPIO",) { 1 }
+ })
+ Return(RBUF)
+ }
+
+ Name (OTGR, ResourceTemplate()
+ {
+ GpioIO (Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.GPIO", 0, ResourceConsumer,,) { 1 }
+ })
+
+ Scope (\_SB_.GPIO)
+ {
+ OperationRegion (OTGP, GeneralPurposeIO, Zero, One)
+ }
+
+ Field (\_SB_.GPIO.OTGP, ByteAcc, NoLock, Preserve)
+ {
+ Connection (\_SB_.URS0.OTGR),
+ OTGF, 1
+ }
+
+ // Device Specific Method takes 4 args:
+ // Arg0 : Buffer containing a UUID [16 bytes]
+ // Arg1 : Integer containing the Revision ID
+ // Arg2 : Integer containing the Function Index
+ // Arg3 : Package that contains function-specific arguments (Unused?)
+ Method (_DSM, 0x4, NotSerialized) {
+ Name (RET, 0x0); // Declare return variable
+ Name (PVAL, 0x0); // Declare pin value variable
+
+ // Check UUID
+ switch(ToBuffer(Arg0))
+ {
+ // URS UUID
+ case(ToUUID("14EB0A6A-79ED-4B37-A8C7-84604B55C5C3"))
+ {
+ // Function index
+ switch(Arg2)
+ {
+ //
+ // Function 0: Return supported functions, based on revision
+ // Return value and revision ID lack documentation
+ //
+ case(0)
+ {
+ switch(Arg1)
+ {
+ // Revision 0: function {1,2} supported
+ case(0)
+ {
+ Return(0x03);
+ }
+ default
+ {
+ Return(0x0);
+ }
+ }
+ }
+
+ //
+ // Function 1: Read USB_OTG_ID pin value
+ //
+ // Return value
+ // 0 = UrsHardwareEventIdFloat (Function)
+ // 1 = UrsHardwareEventIdGround (Host)
+ //
+ case(1)
+ {
+ Store(OTGF, PVAL); // Read value of OTG_ID Pin
+ Store(LEqual(PVAL, 0), RET); // Complement value
+ Return(RET);
+ }
+
+ //
+ // Function 2: Read USB_OTG_ID pin value
+ //
+ // Return value
+ // 0 = UrsHardwareEventIdFloat (Function)
+ // 1 = UrsHardwareEventIdGround (Host)
+ //
+ case(2)
+ {
+ Store(OTGF, PVAL); // Read value of OTG_ID Pin
+ Store(LEqual(PVAL, 0), RET); // Complement value
+ Return(RET);
+ }
+
+ //
+ // Unknown function index
+ //
+ default
+ {
+ Return(0x0);
+ }
+ } // Function index
+ }
+
+ //
+ // Unknown UUID
+ //
+ default
+ {
+ Return(0x0);
+ }
+ } // Check UUID
+ } // _DSM
+
+ Device (USB0)
+ {
+ //
+ // The host controller device node needs to have an address of '0'
+ //
+ Name(_ADR, 0x0)
+ Name(_UID, 0x0)
+ Name (_S0W, 0x0) // D0 is the lowest supported state to wake itself up
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake) { 75 }
+ })
+ Return(RBUF)
+ }
+
+ OperationRegion (OTGM, SystemMemory, 0x02184100, 0x100)
+ Field (OTGM, WordAcc, NoLock, Preserve)
+ {
+ Offset(0x84), // skip to register 84h
+ PTSC, 32, // port status control
+ Offset(0xA8), // skip to register A8h
+ DSBM, 32, // UOG_USBMOD
+ }
+
+ Name (REG, 0x0); // Declare register read variable
+ Method (_UBF, 0x0, NotSerialized) {
+ //
+ // Reset handled by driver so no reset required here
+ //
+ Store(0x03, DSBM); // set host mode & little endian
+ Store(PTSC, REG); // read PORTSC status
+ Store(OR(REG,0x2),PTSC); // clear current PORTSC status
+ }
+ }
+
+ Device(UFN0)
+ {
+ //
+ // The function controller device node needs to have an address of '1'
+ //
+ Name(_ADR, 0x1)
+
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ Interrupt(ResourceConsumer, Level, ActiveHigh, SharedAndWake) { 75 }
+ })
+ Return(RBUF)
+ }
+
+ OperationRegion (OTGM, SystemMemory, 0x02184100, 0x100)
+ Field (OTGM, WordAcc, NoLock, Preserve)
+ {
+ Offset(0x84), // skip to register 84h
+ PTSC, 32, // port status control
+ Offset(0xA8), // skip to register A8h
+ DSBM, 32, // UOG_USBMOD
+ }
+
+ Name (REG, 0x0); // Declare register read variable
+ Method (_UBF, 0x0, NotSerialized) {
+ //
+ // Reset handled by driver so no reset required here
+ //
+ Store(0x02, DSBM); // set device mode & little endian
+ Store(PTSC, REG); // read PORTSC status
+ Store(OR(REG,0x2),PTSC); // clear current PORTSC status
+ }
+
+ //
+ // Device Specific Method takes 4 args:
+ // Arg0 : Buffer containing a UUID [16 bytes]
+ // Arg1 : Integer containing the Revision ID
+ // Arg2 : Integer containing the Function Index
+ // Arg3 : Package that contains function-specific arguments
+ //
+ Method (_DSM, 0x4, NotSerialized) {
+
+ switch(ToBuffer(Arg0))
+ {
+ // UFX Chipidea interface identifier
+ case(ToUUID("732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"))
+ {
+ // Function selector
+ switch(Arg2)
+ {
+ //
+ // Function 0: Query support
+ // Bit Description
+ // --- -------------------------------
+ // 0 Get property
+ // 1 Get properties (Function 1)
+ // 2 Set USB device state
+ //
+ case(0)
+ {
+ switch(Arg1)
+ {
+ // Revision 0: functions {0,1} supported
+ case(0)
+ {
+ Return(Buffer(){0x03});
+ }
+ default
+ {
+ Return(Buffer(){0x01});
+ }
+ }
+ }
+
+ //
+ // Function 1: Return device capabilities bitmap
+ // Bit Description
+ // --- -------------------------------
+ // 0 Attach detach
+ // 1 Software charging
+ //
+ case(1)
+ {
+ Return(0x01);
+ }
+
+ //
+ // Function 2: Get port type
+ // 0x00 Unknown port
+ // 0x01 Standard downstream
+ // 0x02 Charging downstream
+ // 0x03 Dedicated charging
+ //
+ case(2)
+ {
+ Return(0x01);
+ }
+
+ //
+ // Function 3: Set device state
+ //
+ case(3)
+ {
+ Return (Buffer(){0x0});
+ }
+
+ //
+ // Unknown function
+ //
+ default
+ {
+ Return (Buffer(){0x0});
+ }
+ }
+ }
+
+ // UFX interface identifier
+ case(ToUUID("FE56CFEB-49D5-4378-A8A2-2978DBE54AD2"))
+ {
+ // Function selector
+ switch(Arg2)
+ {
+ // Function 1: Return number of supported USB PHYSICAL endpoints
+ // Up to 8 bidirectional endpoints
+ case(1)
+ {
+ Return(8);
+ }
+ default
+ {
+ Return (Buffer(){0x0});
+ }
+ }
+ }
+
+ //
+ // Unknown UUID
+ //
+ default
+ {
+ Return(0x0);
+ }
+ } // UUID
+ } // _DSM
+ }
+}
+
+Device (USB1)
+{
+ Name (_HID, "FSCL000C")
+ Name (_CID, "PNP0D20")
+ Name (_UID, 0x1)
+ Name (_S0W, 0x0)
+
+ // USB Host controller registers
+ OperationRegion (USBH, SystemMemory, 0x02184000, 0x1000)
+ Field (USBH, DWordAcc, NoLock, Preserve)
+ {
+ Offset(0x00000344),
+ USTS, 32, // USB_UH1_USBSTS
+ Offset(0x00000348),
+ INTR, 32, // USB_UH1_USBINTR
+ Offset(0x00000384), // skip to register 0x384
+ PSC1, 32, // USB_UH1_PORTSC1
+ Offset(0x00000804), // skip to register 0x804
+ NCTL, 32, // USBNC_USB_UH1_CTRL
+ }
+
+ // USBPHY2 Registers
+ OperationRegion (PHY2, SystemMemory, 0x020CA000, 0x1000)
+ Field (PHY2, DWordAcc, NoLock, Preserve)
+ {
+ Offset(0x0000000), // skip to register 0
+ PPWD, 32, // USBPHY2_PWD
+ Offset(0x00000030), // skip to register 0x30
+ PCTL, 32, // USBPHY2_CTRL
+ Offset(0x00000034), // skip to register 0x34
+ PCTS, 32, // USBPHY2_CTRL_SET
+ Offset(0x00000038), // skip to register 0x38
+ PCTC, 32, // USBPHY2_CTRL_CLR
+ Offset(0x00000050), // skip to register 0x50
+ PDBG, 32, // USBPHY2_DEBUG
+ Offset(0x00000054), // skip to register 0x54
+ PDBS, 32, // USBPHY2_DEBUG_SET
+ Offset(0x00000058), // skip to register 0x58
+ PDBC, 32, // USBPHY2_DEBUG_CLR
+ }
+
+ // Anatop Registers
+ OperationRegion (ANAT, SystemMemory, 0x020C8000, 0x1000)
+ Field (ANAT, DWordAcc, NoLock, Preserve)
+ {
+ Offset(0x0000244), // skip to register 0x244
+ LPBS, 32, // ANADIG_USB2_LOOPBACK_SET
+ Offset(0x0000248), // skip to register 0x248
+ LPBC, 32, // ANADIG_USB2_LOOPBACK_CLR
+ }
+
+ Method (_STA)
+ {
+ Return(0xf)
+ }
+ Method (_CRS, 0x0, NotSerialized) {
+ Name (RBUF, ResourceTemplate () {
+ MEMORY32FIXED(ReadWrite, 0x02184300, 0x100, )
+ Interrupt(ResourceConsumer, Level, ActiveHigh, ExclusiveAndWake) { 72 }
+ })
+ Return(RBUF)
+ }
+
+ Method (_UBF, 0x0, NotSerialized)
+ {
+ }
+}
--
2.16.2.gvfs.1.33.gf5370f1
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