From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=192.55.52.151; helo=mga17.intel.com; envelope-from=eric.dong@intel.com; receiver=edk2-devel@lists.01.org Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AF40D21BADAB2 for ; Thu, 9 Aug 2018 21:19:26 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Aug 2018 21:19:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,218,1531810800"; d="scan'208";a="74234301" Received: from ydong10-win10.ccr.corp.intel.com ([10.239.9.125]) by orsmga003.jf.intel.com with ESMTP; 09 Aug 2018 21:19:19 -0700 From: Eric Dong To: edk2-devel@lists.01.org Cc: Laszlo Ersek , Ruiyu Ni Date: Fri, 10 Aug 2018 12:19:08 +0800 Message-Id: <20180810041909.12776-5-eric.dong@intel.com> X-Mailer: git-send-email 2.15.0.windows.1 In-Reply-To: <20180810041909.12776-1-eric.dong@intel.com> References: <20180810041909.12776-1-eric.dong@intel.com> Subject: [Patch v3 4/5] UefiCpuPkg/CpuS3DataDxe: Remove below 4G limitation. X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Aug 2018 04:19:26 -0000 Because PrepareApStartupVector() stores StackAddress to "mExchangeInfo->StackStart" (which has type (VOID*)), and because "UefiCpuPkg/PiSmmCpuDxeSmm/X64/MpFuncs.nasm" reads the latter with: add edi, StackStartAddressLocation add rax, qword [edi] mov rsp, rax mov qword [edi], rax in long-mode code. So code can remove below 4G limitation. Cc: Laszlo Ersek Cc: Ruiyu Ni Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Eric Dong --- UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c index 5b99a6e759..d18f33a5b8 100644 --- a/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c +++ b/UefiCpuPkg/CpuS3DataDxe/CpuS3Data.c @@ -46,9 +46,7 @@ typedef struct { } ACPI_CPU_DATA_EX; /** - Allocate EfiACPIMemoryNVS below 4G memory address. - - This function allocates EfiACPIMemoryNVS below 4G memory address. + Allocate EfiACPIMemoryNVS memory. @param[in] Size Size of memory to allocate. @@ -56,7 +54,7 @@ typedef struct { **/ VOID * -AllocateAcpiNvsMemoryBelow4G ( +AllocateAcpiNvsMemory ( IN UINTN Size ) { @@ -64,9 +62,8 @@ AllocateAcpiNvsMemoryBelow4G ( EFI_STATUS Status; VOID *Buffer; - Address = BASE_4GB - 1; Status = gBS->AllocatePages ( - AllocateMaxAddress, + AllocateAnyPages, EfiACPIMemoryNVS, EFI_SIZE_TO_PAGES (Size), &Address @@ -239,9 +236,13 @@ CpuS3DataInitialize ( AcpiCpuData->MtrrTable = (EFI_PHYSICAL_ADDRESS)(UINTN)&AcpiCpuDataEx->MtrrTable; // - // Allocate stack space for all CPUs + // Allocate stack space for all CPUs. + // Use ACPI NVS memory type because this data will be directly used by APs + // in S3 resume phase in long mode. Also during S3 resume, the stack buffer + // will only be used as scratch space. i.e. we won't read anything from it + // before we write to it, in PiSmmCpuDxeSemm. // - Stack = AllocateAcpiNvsMemoryBelow4G (NumberOfCpus * AcpiCpuData->StackSize); + Stack = AllocateAcpiNvsMemory (NumberOfCpus * AcpiCpuData->StackSize); ASSERT (Stack != NULL); AcpiCpuData->StackAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)Stack; -- 2.15.0.windows.1