From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::241; helo=mail-pl0-x241.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 03839210F2028 for ; Tue, 14 Aug 2018 01:11:26 -0700 (PDT) Received: by mail-pl0-x241.google.com with SMTP id w14-v6so8030698plp.6 for ; Tue, 14 Aug 2018 01:11:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iTSwOC7K+b4xTdT7j6SRG85QHZuk1/0gyX5W4IkGyX4=; b=Uloie7XI6dSBeZY53OJsQcyRR4RYfSZW5IEzcrUdmnybqmcJtNG4Y5WsGmP5UerkU4 5hDy4frPjHDGluJLx0AMkRRiYQn3Ty3qkHQwNwDR8D4ZZp1cUoZMuCrOsaJWS75fWdKW KM7xSeGb1QV6zlj28Tr6mx2FbdJcW4aYBzEJA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=iTSwOC7K+b4xTdT7j6SRG85QHZuk1/0gyX5W4IkGyX4=; b=VjN6fyeR6ABNDM2vfqOxPFIu2a4eXr4rHaxWf2Kme1bq6Fq02bHm8+UkZNG9qGZWM4 wkuscDT6BOI3zeP3LE3gXJgsE+kC1mHLrcQrpnvgb4KdTkn5mNTwTydikWVdbYsXL9y/ OZpUT2+u69mPkHYKiHU7ycGRlm2MPXjldNor5cU1cpengH0EAzN8a1kKYTqt7+vxom2q yMgjRizEnoxu5uQKF9Tt6oBSk1bnLOBXwxOgBsfd+n8NwHzAu8okexAD1Apep1r/347s qfjr/bHWkqeLcLe0KXmhaOErdSrN8qV6lBuRxe2QIWpaHygioNOZxdgivsv0z9tDR9y0 yqlA== X-Gm-Message-State: AOUpUlFaK9EUlIjsHr7CpK07ptGFl5o4h4v5h5iGypTk3iRHanKOsSAx m/lnU1/J6AyBnb44I1Z4rBYlVA== X-Google-Smtp-Source: AA+uWPyZAHA0WrSFRbIRoANemSFHVgWlpHeRgmC0d18IUS4g57jzVEZKOUuwgTAwu66xJKa7z/3mtA== X-Received: by 2002:a17:902:48c8:: with SMTP id u8-v6mr19574282plh.152.1534234286705; Tue, 14 Aug 2018 01:11:26 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id h130-v6sm72905670pgc.88.2018.08.14.01.11.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 14 Aug 2018 01:11:26 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, Ming Huang Date: Tue, 14 Aug 2018 16:08:55 +0800 Message-Id: <20180814080903.50466-36-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180814080903.50466-1-ming.huang@linaro.org> References: <20180814080903.50466-1-ming.huang@linaro.org> Subject: [PATCH edk2-platforms v2 35/43] Silicon/Hisilicon/D06: Add some Lpc macro to LpcLib.h X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Aug 2018 08:11:27 -0000 Add some Lpc macro to LpcLib.h for D06. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Silicon/Hisilicon/Include/Library/LpcLib.h | 51 +++++++++++++++++++- 1 file changed, 49 insertions(+), 2 deletions(-) diff --git a/Silicon/Hisilicon/Include/Library/LpcLib.h b/Silicon/Hisilicon/Include/Library/LpcLib.h index 236a52ba45..5cf08ccde1 100755 --- a/Silicon/Hisilicon/Include/Library/LpcLib.h +++ b/Silicon/Hisilicon/Include/Library/LpcLib.h @@ -1,7 +1,7 @@ /** @file * -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. -* Copyright (c) 2016, Linaro Limited. All rights reserved. +* Copyright (c) 2016-2018, Hisilicon Limited. All rights reserved. +* Copyright (c) 2016-2018, Linaro Limited. All rights reserved. * * This program and the accompanying materials * are licensed and made available under the terms and conditions of the BSD License @@ -18,6 +18,53 @@ #include +#define PCIE_SUBSYS_IOMUX 0x201100000 +#define PCIE_SUBSYS_IOMG019 (PCIE_SUBSYS_IOMUX + 0x48) +#define PCIE_SUBSYS_IOMG020 (PCIE_SUBSYS_IOMUX + 0x4C) +#define PCIE_SUBSYS_IOMG021 (PCIE_SUBSYS_IOMUX + 0x50) +#define PCIE_SUBSYS_IOMG022 (PCIE_SUBSYS_IOMUX + 0x54) +#define PCIE_SUBSYS_IOMG023 (PCIE_SUBSYS_IOMUX + 0x58) +#define PCIE_SUBSYS_IOMG024 (PCIE_SUBSYS_IOMUX + 0x5C) +#define PCIE_SUBSYS_IOMG025 (PCIE_SUBSYS_IOMUX + 0x60) +#define PCIE_SUBSYS_IOMG028 (PCIE_SUBSYS_IOMUX + 0x6C) + +#define IO_MGMT_SUBCTRL_BASE 0x201070000 +#define SC_LPC_RESET_REQ_REG (IO_MGMT_SUBCTRL_BASE + 0x0a58) +#define SC_LPC_RESET_DREQ_REG (IO_MGMT_SUBCTRL_BASE + 0x0a5c) +#define SC_LPC_SEL (IO_MGMT_SUBCTRL_BASE + 0x2400) + + +#define LPCD06_BASE 0x201190000 +#define LPC_FIRM_SPACE0_CFG (LPCD06_BASE + 0x100) +#define LPC_FIRM_SPACE1_CFG (LPCD06_BASE + 0x104) +#define LPC_FIRM_SPACE2_CFG (LPCD06_BASE + 0x108) +#define LPC_FIRM_SPACE3_CFG (LPCD06_BASE + 0x10C) +#define LPC_FIRM_SPACE4_CFG (LPCD06_BASE + 0x110) +#define LPC_FIRM_SPACE5_CFG (LPCD06_BASE + 0x114) +#define LPC_FIRM_SPACE6_CFG (LPCD06_BASE + 0x118) +#define LPC_FIRM_SPACE7_CFG (LPCD06_BASE + 0x11C) +#define LPC_MEM_SPACE0_CFG (LPCD06_BASE + 0x120) +#define LPC_MEM_SPACE1_CFG (LPCD06_BASE + 0x124) +#define LPC_MEM_SPACE2_CFG (LPCD06_BASE + 0x128) +#define LPC_MEM_SPACE3_CFG (LPCD06_BASE + 0x12C) +#define LPC_MEM_SPACE4_CFG (LPCD06_BASE + 0x130) +#define LPC_MEM_SPACE5_CFG (LPCD06_BASE + 0x134) +#define LPC_MEM_SPACE6_CFG (LPCD06_BASE + 0x138) + +#define LPCD06_START_REG (LPCD06_BASE + 0x00) +#define LPCD06_OP_STATUS_REG (LPCD06_BASE + 0x04) +#define LPCD06_IRQ_ST_REG (LPCD06_BASE + 0x08) +#define LPCD06_OP_LEN_REG (LPCD06_BASE + 0x10) +#define LPCD06_CMD_REG (LPCD06_BASE + 0x14) +#define LPCD06_ADDR_REG (LPCD06_BASE + 0x20) +#define LPCD06_WDATA_REG (LPCD06_BASE + 0x24) +#define LPCD06_RDATA_REG (LPCD06_BASE + 0x28) + +#define LPC_SIRQ_CTR0 (LPCD06_BASE + 0x80) +#define LPC_SIRQ_CTR1 (LPCD06_BASE + 0x84) +#define LPC_SIRQ_INT_MASK (LPCD06_BASE + 0x94) + + #define PCIE_SUBSYS_IO_MUX 0xA0170000 #define PCIE_SUBSYS_IOMG033 (PCIE_SUBSYS_IO_MUX + 0x84) #define PCIE_SUBSYS_IOMG035 (PCIE_SUBSYS_IO_MUX + 0x8C) -- 2.17.0