From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::241; helo=mail-pl0-x241.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x241.google.com (mail-pl0-x241.google.com [IPv6:2607:f8b0:400e:c01::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 94517210F2544 for ; Tue, 14 Aug 2018 01:11:43 -0700 (PDT) Received: by mail-pl0-x241.google.com with SMTP id b90-v6so8044252plb.0 for ; Tue, 14 Aug 2018 01:11:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dPwuA9svVO/960rahvTTDA8WB6UGBMspAj+4E3t/334=; b=XjxhdvgU4nxtm71HjHiFapsLh3ZwkjOFQ4H7WxFif3uGQxVLVYzr1OuoSOzwDRR0mz FPoHjz7PuAR9hRxMmAoT3LgHcxEWRS9/WS8FrI/mfUlAnSclyzTKI555cMAeGuxT8CS9 8o996edeoIpKFusqJuGzWGLqkktcnH8JFbQfE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dPwuA9svVO/960rahvTTDA8WB6UGBMspAj+4E3t/334=; b=hrvhvQWsjn/XWdnOO+xCwG4Lopsun0E0M8Akon0idERgjBDdhnkhKDnipNCyFKd6Gf UwrsDECoPXUfA32+C3bNSXdsf5haLGkUxNOIM0r/389U/l++nIch/dEXaLOPYgIsbYky 9jeAkoKr/1WwjywFneQ0ItQpiWyvy59/hE1W/RvDgS2BPFlNhYQwfdOevMG/jsC6yLlW kyZWRnHAOLU6ccpXt1BvxLy1TKI2d4u6YS1cIFMqII3+3qMLcOIcc31gTQUZVpwmcXgZ Bzpo7g8F8gZku1WgBjC+9YDgTAmZHPQBGoqOCeBjYH/8/Cm9faFEQdZ3OxyujA2wYwrL 9r7Q== X-Gm-Message-State: AOUpUlGgc1vTno2td1OcLL8rOzmr1ltaRm4mBrvm1qzapiJeZOw/Jrpz Qe0GcOB/flXKSaioLHsxbxP3iQ4c3LY= X-Google-Smtp-Source: AA+uWPwCpyBc6nQ2LHxC60kNl9/lCSNm+4dQFPSfNODa+NU7Tbie4IoIUdlT87jZ44K3PuR2LCyMcA== X-Received: by 2002:a17:902:22:: with SMTP id 31-v6mr19557805pla.190.1534234303340; Tue, 14 Aug 2018 01:11:43 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id h130-v6sm72905670pgc.88.2018.08.14.01.11.40 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 14 Aug 2018 01:11:42 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, Ming Huang Date: Tue, 14 Aug 2018 16:09:00 +0800 Message-Id: <20180814080903.50466-41-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180814080903.50466-1-ming.huang@linaro.org> References: <20180814080903.50466-1-ming.huang@linaro.org> Subject: [PATCH edk2-platforms v2 40/43] Silicon/Hisilicon/setup: Support SMMU switch X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Aug 2018 08:11:43 -0000 Select without SMMU iort while SMMU item is disable, Select with SMMU iort while SMMU item is enable. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c | 88 ++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c index 32878ca4f9..e0c29e0f57 100644 --- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c +++ b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c @@ -24,6 +24,90 @@ #define CORECOUNT(X) ((X) * CORE_NUM_PER_SOCKET) +#define FIELD_IORT_NODE_OFFSET 40 + +typedef enum { + NodeTypeIts = 0, + NodeTypeNameComponent, + NodeTypePciRC, + NodeTypeSmmuV1, + NodeTypeSmmuV3, + NodeTypePMCG +} IORT_NODE_TYPE; + +#pragma pack(1) +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 IdMapNumber; + UINT32 IdArrayOffset; +} IORT_NODE_HEAD; +#pragma pack() + +BOOLEAN +IsIortWithSmmu ( + IN EFI_ACPI_DESCRIPTION_HEADER *TableHeader + ) +{ + UINT32 *NodeOffset; + UINT32 NextOffset; + IORT_NODE_HEAD *Node; + + NodeOffset = (UINT32 *)((UINT8 *)TableHeader + FIELD_IORT_NODE_OFFSET); + NextOffset = *NodeOffset; + + while (NextOffset < TableHeader->Length) { + Node = (IORT_NODE_HEAD *)((UINT8 *)TableHeader + NextOffset); + NextOffset += Node->Length; + + if ((Node->Type == NodeTypeSmmuV1) || (Node->Type == NodeTypeSmmuV3)) { + return TRUE; + } + } + + return FALSE; +} + +EFI_STATUS +SelectIort ( + IN EFI_ACPI_DESCRIPTION_HEADER *TableHeader + ) +{ + EFI_STATUS Status; + UINTN Size; + OEM_CONFIG_DATA Configuration; + + Configuration.EnableSmmu = 0; + Size = sizeof (OEM_CONFIG_DATA); + Status = gRT->GetVariable ( + OEM_CONFIG_NAME, + &gOemConfigGuid, + NULL, + &Size, + &Configuration + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Get OemConfig variable (%r).\n", Status)); + } + + Status = EFI_SUCCESS; + if (IsIortWithSmmu (TableHeader)) { + if (!Configuration.EnableSmmu) { + Status = EFI_ABORTED; + } + } else { + if (Configuration.EnableSmmu) { + Status = EFI_ABORTED; + } + } + DEBUG ((DEBUG_INFO, "SmmuEnable=%x, return %r for Iort table.\n", + Configuration.EnableSmmu, Status)); + + return Status; +} + STATIC VOID RemoveUnusedMemoryNode ( @@ -151,6 +235,10 @@ UpdateAcpiTable ( case EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE: Status = UpdateSlit (TableHeader); break; + + case EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE: + Status = SelectIort (TableHeader); + break; case EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE: Status = IsNeedSpcr (TableHeader); break; -- 2.17.0