From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 9328B210E8D7B for ; Wed, 15 Aug 2018 06:29:32 -0700 (PDT) Received: by mail-wm0-x242.google.com with SMTP id n11-v6so1351502wmc.2 for ; Wed, 15 Aug 2018 06:29:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=6KEgGH8Ad3cQ283DglRBp0Fhni3KsPsmGBgZ8donO2I=; b=gx7mAi23YSV3f2/c23f/Y6TXSqYGwbmlKzfTLDfs7lYaHwr4mO5NlPj/Aug5tyD/WV U9MO3kMMZlAIdZoTcmA8+sp+U/4VqoQ3yjV2HyfvcKAd9b6Fl3j2ZTK21IhXcv5XnRzd YxfGmm8fS7ilbIVphQay1MMhYezt9CysAJK8w= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=6KEgGH8Ad3cQ283DglRBp0Fhni3KsPsmGBgZ8donO2I=; b=k9+kgGd6p3PWtNbSKzR9m94+0v1cxrNcEJXKlr3NVOh3d+CNAykAADwtuQlySnA16H 4AeyQ8HffACYeO+1718I++qc9zuGWTJRx5oj5HckOz6pOIeL9c/zBHotSve+sgYK4T8d Bt23vF0gcrUUlu2SICPlC0cokzyfNAKFkcv87z5hgev5JNFdKq6chIA3IDhTey7Br+WG fOsHM61AXdXVLFRGaakItjCmj9xT8K45hGV7Xeuc6+eqKmWOD0xq3SMGaU+pFvMuCqdE TR9WffE1DSgsh2gQbpqwj2qCYtSsn9M7+lr7cZeNmvNN61iRVDd3T8Vd657GU8ME5EIz uPxQ== X-Gm-Message-State: AOUpUlGRHj124hmNz4oTQaLZbKzmF0ZJ5r7juok52qQfwRLg3X0mqLWZ 3AkS+LtE+IZSa4PvSRh/wEwt+Q== X-Google-Smtp-Source: AA+uWPyWafzi/OzSwK0VJfjZOV4Nooq51Wa5kNHxon+YUCI4Q30ESkKfgTZla09qKaa3vyJVnQxYbQ== X-Received: by 2002:a1c:c3c4:: with SMTP id t187-v6mr14345909wmf.123.1534339770888; Wed, 15 Aug 2018 06:29:30 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id a9-v6sm30384120wrp.55.2018.08.15.06.29.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 15 Aug 2018 06:29:29 -0700 (PDT) Date: Wed, 15 Aug 2018 14:29:27 +0100 From: Leif Lindholm To: Haojian Zhuang Cc: edk2-devel@lists.01.org, Ard Biesheuvel Message-ID: <20180815132927.33dhuiefcxo2dz4b@bivouac.eciton.net> References: <1533890975-13055-1-git-send-email-haojian.zhuang@linaro.org> <1533890975-13055-2-git-send-email-haojian.zhuang@linaro.org> MIME-Version: 1.0 In-Reply-To: <1533890975-13055-2-git-send-email-haojian.zhuang@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH v1 edk-platforms 1/3] Silicon/Hi3660: fix LDO9_VSET register definition X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 15 Aug 2018 13:29:33 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Haojian, On Fri, Aug 10, 2018 at 04:49:33PM +0800, Haojian Zhuang wrote: > Fix the LDO9_VSET register definition in PMIC. Could you add some more detail to the commit message, please?: What register was accidentally read/written before? Does this change resolve a user-visible issue or just a hypothetical one? / Leif > Cc: Leif Lindholm > Cc: Ard Biesheuvel > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Haojian Zhuang > --- > Silicon/Hisilicon/Hi3660/Include/Hi3660.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Silicon/Hisilicon/Hi3660/Include/Hi3660.h b/Silicon/Hisilicon/Hi3660/Include/Hi3660.h > index 5fbf32267657..6e0587f7783a 100644 > --- a/Silicon/Hisilicon/Hi3660/Include/Hi3660.h > +++ b/Silicon/Hisilicon/Hi3660/Include/Hi3660.h > @@ -58,7 +58,7 @@ > #define USB3OTG_PHY_CR_CAP_ADDR (1 << 0) > > #define PMU_REG_BASE 0xFFF34000 > -#define PMIC_LDO9_VSET_REG (PMU_REG_BASE + (0x068 << 2)) > +#define PMIC_LDO9_VSET_REG (PMU_REG_BASE + (0x06b << 2)) > #define LDO9_VSET_MASK (7 << 0) > > #define PMIC_LDO16_ONOFF_ECO_REG (PMU_REG_BASE + (0x078 << 2)) > -- > 2.7.4 >