From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:4864:20::442; helo=mail-wr1-x442.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr1-x442.google.com (mail-wr1-x442.google.com [IPv6:2a00:1450:4864:20::442]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AA0FB203B99D7 for ; Thu, 16 Aug 2018 02:23:32 -0700 (PDT) Received: by mail-wr1-x442.google.com with SMTP id e7-v6so3493293wrs.9 for ; Thu, 16 Aug 2018 02:23:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=JiutGNk2F5+ctdvHWUtIiq+CMR0q8R3Ftju2NNoZYIo=; b=fQU1qq6ryDbN/iTRUHlL2y4UpigvK0Db/8A7iz+Jyi+Jh2qHKoc8DgNCPwrfKyt5i1 YLqOGAp8ueQKO0fJ523sNQrzKZcmsWL1GwzLXeeNBvC9Mcw6KymSICasaw/e8CMIsXok 1j1FhLnsW+3I2iWAaQcHCmVk1524lCjW3vKeQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=JiutGNk2F5+ctdvHWUtIiq+CMR0q8R3Ftju2NNoZYIo=; b=ef9Vb3NSvtHYVlbScmx95X5XCFCbLOX9RLfaYhaK78rTisNeUYpDW5akO96iqx+46H T7dJ2bx0lZfEBXeQtHuUo9kbdjaESnsJN++JiAIgu+kyqPdro11FLDc0rM8ZfUcM0lHn yJsJtDsOzCPl/zDvgqRUOJo0iUjD4Z1s6ceECz6r1OrRtKmMjqIaPpvQDST9gHeB1pj/ zlrIBTesBsPcvRyzDazefBk12dAntqWvlcMTOXNm5Fwi8xIbrgSlZPn9YAAGH1+HpHJz Z+H/EXyARcpNEpFUR4eKc8JKoCQQCIqxqHtEkgYzo9qZA8l4xiOZ+VplEHslRiC/i3Al 3iOg== X-Gm-Message-State: AOUpUlHoji62JXtwrvIOKuwZFms/8n3wzSGLWur3NSC5onC6ygJHKtXS HReIVeBVLab2eP0qGJmWDVrguw== X-Google-Smtp-Source: AA+uWPw7yzdsSJiUoX8TDTOXbNwtoFdIlgAuz752p7r0Wv+W6FrKgE9xjALBVUWJ/lF6114eJv4EMQ== X-Received: by 2002:a5d:4b50:: with SMTP id w16-v6mr18405367wrs.87.1534411410738; Thu, 16 Aug 2018 02:23:30 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id a6-v6sm1060453wmf.22.2018.08.16.02.23.29 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 16 Aug 2018 02:23:29 -0700 (PDT) Date: Thu, 16 Aug 2018 10:23:28 +0100 From: Leif Lindholm To: Haojian Zhuang Cc: edk2-devel@lists.01.org, Ard Biesheuvel Message-ID: <20180816092328.npzcx7xk5xobq2ye@bivouac.eciton.net> References: <1534384166-15673-1-git-send-email-haojian.zhuang@linaro.org> <1534384166-15673-2-git-send-email-haojian.zhuang@linaro.org> MIME-Version: 1.0 In-Reply-To: <1534384166-15673-2-git-send-email-haojian.zhuang@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH v2 edk-platforms 1/3] Silicon/Hi3660: fix LDO9_VSET register definition X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Aug 2018 09:23:33 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Thu, Aug 16, 2018 at 09:49:24AM +0800, Haojian Zhuang wrote: > Fix the LDO9_VSET register definition in PMIC. LDO9 is used > by Designware SD controller. Without this fix, SD controller > fails to operate SD card since lack of right voltage setting. > > Cc: Leif Lindholm > Cc: Ard Biesheuvel > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Haojian Zhuang Reviewed-by: Leif Lindholm Pushed as d11581e5fd. > --- > Silicon/Hisilicon/Hi3660/Include/Hi3660.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/Silicon/Hisilicon/Hi3660/Include/Hi3660.h b/Silicon/Hisilicon/Hi3660/Include/Hi3660.h > index 5fbf32267657..6e0587f7783a 100644 > --- a/Silicon/Hisilicon/Hi3660/Include/Hi3660.h > +++ b/Silicon/Hisilicon/Hi3660/Include/Hi3660.h > @@ -58,7 +58,7 @@ > #define USB3OTG_PHY_CR_CAP_ADDR (1 << 0) > > #define PMU_REG_BASE 0xFFF34000 > -#define PMIC_LDO9_VSET_REG (PMU_REG_BASE + (0x068 << 2)) > +#define PMIC_LDO9_VSET_REG (PMU_REG_BASE + (0x06b << 2)) > #define LDO9_VSET_MASK (7 << 0) > > #define PMIC_LDO16_ONOFF_ECO_REG (PMU_REG_BASE + (0x078 << 2)) > -- > 2.7.4 >