From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2607:f8b0:400e:c01::243; helo=mail-pl0-x243.google.com; envelope-from=ming.huang@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-pl0-x243.google.com (mail-pl0-x243.google.com [IPv6:2607:f8b0:400e:c01::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 45EFD210F41C4 for ; Thu, 16 Aug 2018 05:14:57 -0700 (PDT) Received: by mail-pl0-x243.google.com with SMTP id f6-v6so2026539plo.1 for ; Thu, 16 Aug 2018 05:14:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=dPwuA9svVO/960rahvTTDA8WB6UGBMspAj+4E3t/334=; b=FDhVx0Q6RHf5vP6wwXuyuEt46We398me2pNHJ3oEm9259TsL/NCZljoKhT+uCwEUsa 1OrFqVLESX74zfsUhcEoyiRAhoYVf3KgSgjzPicWBV0NDfsjH4pL5iIzAhFVwTxgCt/K PibRDYcWEktWEYDOO+kdFbGQ3zn/X+3Tq4sQw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=dPwuA9svVO/960rahvTTDA8WB6UGBMspAj+4E3t/334=; b=TJWO8TMZKy3yZ5MMtu6CpOHwlvJuJKQIFhdJXx4L54iH308p5wTHjxG6JV31Pmejat VQlEWIPsGi48iKssSGg20aZwlhinZh31vVe4+/nOhbKe45VTKwbMXjknP274mQ0F+jIG +P2lQRYAnQGG+niss7QvkMa30/q6tHKsgMostE+PgeM9CGmiQKIlSYU9WxcOupQit+vh BQEJgxDMq9RQTi+d1FvElMhypIDO8cGEOrRKtsCdRcWSHlrjOc3GyW02n0wVEDksuC2p 4ptB3LMk+W/rXEfVRy+sRjApVHhMpKc3sCTdCKXrzK9b7wk3AnPyrvQKNRjO4rD9YnOw qXKA== X-Gm-Message-State: AOUpUlFW+pUVxO/lBiaNVV0VJS9HUoBFuxksZ1T56m3OOviEtFi42WjC GArx/7yhWDMI0rwgtyq5HSbh1g== X-Google-Smtp-Source: AA+uWPxKYQej2DiQCe9kcfX1RtLt14WrKMOMbivnc7Yyg99LjzdeYvtjwrZSe157xySMwyIUSTs8JQ== X-Received: by 2002:a17:902:6909:: with SMTP id j9-v6mr28486291plk.196.1534421697035; Thu, 16 Aug 2018 05:14:57 -0700 (PDT) Received: from localhost.localdomain ([120.31.149.194]) by smtp.gmail.com with ESMTPSA id j27-v6sm46736311pfj.91.2018.08.16.05.14.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 16 Aug 2018 05:14:56 -0700 (PDT) From: Ming Huang To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org Cc: ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, Ming Huang Date: Thu, 16 Aug 2018 20:12:36 +0800 Message-Id: <20180816121239.44129-34-ming.huang@linaro.org> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180816121239.44129-1-ming.huang@linaro.org> References: <20180816121239.44129-1-ming.huang@linaro.org> Subject: [PATCH edk2-platforms v3 33/36] Silicon/Hisilicon/setup: Support SMMU switch X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Aug 2018 12:14:57 -0000 Select without SMMU iort while SMMU item is disable, Select with SMMU iort while SMMU item is enable. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ming Huang --- Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c | 88 ++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c index 32878ca4f9..e0c29e0f57 100644 --- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c +++ b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c @@ -24,6 +24,90 @@ #define CORECOUNT(X) ((X) * CORE_NUM_PER_SOCKET) +#define FIELD_IORT_NODE_OFFSET 40 + +typedef enum { + NodeTypeIts = 0, + NodeTypeNameComponent, + NodeTypePciRC, + NodeTypeSmmuV1, + NodeTypeSmmuV3, + NodeTypePMCG +} IORT_NODE_TYPE; + +#pragma pack(1) +typedef struct { + UINT8 Type; + UINT16 Length; + UINT8 Revision; + UINT32 Reserved; + UINT32 IdMapNumber; + UINT32 IdArrayOffset; +} IORT_NODE_HEAD; +#pragma pack() + +BOOLEAN +IsIortWithSmmu ( + IN EFI_ACPI_DESCRIPTION_HEADER *TableHeader + ) +{ + UINT32 *NodeOffset; + UINT32 NextOffset; + IORT_NODE_HEAD *Node; + + NodeOffset = (UINT32 *)((UINT8 *)TableHeader + FIELD_IORT_NODE_OFFSET); + NextOffset = *NodeOffset; + + while (NextOffset < TableHeader->Length) { + Node = (IORT_NODE_HEAD *)((UINT8 *)TableHeader + NextOffset); + NextOffset += Node->Length; + + if ((Node->Type == NodeTypeSmmuV1) || (Node->Type == NodeTypeSmmuV3)) { + return TRUE; + } + } + + return FALSE; +} + +EFI_STATUS +SelectIort ( + IN EFI_ACPI_DESCRIPTION_HEADER *TableHeader + ) +{ + EFI_STATUS Status; + UINTN Size; + OEM_CONFIG_DATA Configuration; + + Configuration.EnableSmmu = 0; + Size = sizeof (OEM_CONFIG_DATA); + Status = gRT->GetVariable ( + OEM_CONFIG_NAME, + &gOemConfigGuid, + NULL, + &Size, + &Configuration + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Get OemConfig variable (%r).\n", Status)); + } + + Status = EFI_SUCCESS; + if (IsIortWithSmmu (TableHeader)) { + if (!Configuration.EnableSmmu) { + Status = EFI_ABORTED; + } + } else { + if (Configuration.EnableSmmu) { + Status = EFI_ABORTED; + } + } + DEBUG ((DEBUG_INFO, "SmmuEnable=%x, return %r for Iort table.\n", + Configuration.EnableSmmu, Status)); + + return Status; +} + STATIC VOID RemoveUnusedMemoryNode ( @@ -151,6 +235,10 @@ UpdateAcpiTable ( case EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE: Status = UpdateSlit (TableHeader); break; + + case EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE: + Status = SelectIort (TableHeader); + break; case EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE: Status = IsNeedSpcr (TableHeader); break; -- 2.17.0