[PATCH v3 0/2] UefiCpuPkg: [CVE-2017-5715] Stuff RSB before RSM

[PATCH v3 0/2] UefiCpuPkg: [CVE-2017-5715] Stuff RSB before RSM

[Hao Wu]

V3 changes:
A. Add relating CVE issue number to the commits' subject line.

B. Keep the URL links within log messages unwrapped.

C. Add TianoCore Bugzilla link reference to each commits.

D. Mention further actions should be taken after pushing the series in log
   messages.

E. Refine file description comments for StuffRsb.inc files.

V2 changes:
A. Refine commit log message to clarify the purpose of the series

B. Extract the RSB stuffing logic to INC files to avoid code duplication:
When compiling .NASM source files, the current build rule does not support
including files other than the .NASM file directory, this series will
duplicate the StuffRsb.inc file together with the .NASM files at this
moment.

Please consider this approach as the first stage, I have filed a Bugzilla
for adding $(INC)-like support when compiling .NASM files:
https://bugzilla.tianocore.org/show_bug.cgi?id=1085

After the above support is added, the next step will be taken to remove
those duplicated StuffRsb.inc files and put it under a common include
directory like:
UefiCpuPkg/Include/

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>

Hao Wu (2):
  UefiCpuPkg/PiSmmCpuDxeSmm: [CVE-2017-5715] Stuff RSB before RSM
  UefiCpuPkg/SmmCpuFeaturesLib: [CVE-2017-5715] Stuff RSB before RSM

 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm     |  3 ++
 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm | 10 ++--
 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/StuffRsb.inc      | 55 ++++++++++++++++++++
 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm      |  3 ++
 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm  |  8 ++-
 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/StuffRsb.inc       | 55 ++++++++++++++++++++
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm                |  3 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm                 |  3 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/StuffRsb.inc                 | 55 ++++++++++++++++++++
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm                 |  3 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm                  |  3 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/StuffRsb.inc                  | 55 ++++++++++++++++++++
 12 files changed, 251 insertions(+), 5 deletions(-)
 create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/StuffRsb.inc
 create mode 100644 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/StuffRsb.inc
 create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/StuffRsb.inc
 create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/X64/StuffRsb.inc

-- 
2.12.0.windows.1

[PATCH v3 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: [CVE-2017-5715] Stuff RSB before RSM

[Hao Wu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1093

Return Stack Buffer (RSB) is used to predict the target of RET
instructions. When the RSB underflows, some processors may fall back to
using branch predictors. This might impact software using the retpoline
mitigation strategy on those processors.

This commit will add RSB stuffing logic before returning from SMM (the RSM
instruction) to avoid interfering with non-SMM usage of the retpoline
technique.

After the stuffing, RSB entries will contain a trap like:

@SpecTrap:
    pause
    lfence
    jmp     @SpecTrap

A more detailed explanation of the purpose of commit is under the
'Branch target injection mitigation' section of the below link:
https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation

Please note that this commit requires further actions (BZ 1091) to remove
the duplicated 'StuffRsb.inc' files and merge them into one under a
UefiCpuPkg package-level directory (such as UefiCpuPkg/Include/).

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1091

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
---
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm |  3 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm  |  3 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/StuffRsb.inc  | 55 ++++++++++++++++++++
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm  |  3 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm   |  3 ++
 UefiCpuPkg/PiSmmCpuDxeSmm/X64/StuffRsb.inc   | 55 ++++++++++++++++++++
 6 files changed, 122 insertions(+)

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
index 509e7a0a66..6bbc339c53 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
@@ -18,6 +18,8 @@
 ;
 ;-------------------------------------------------------------------------------
 
+%include "StuffRsb.inc"
+
 %define MSR_IA32_MISC_ENABLE 0x1A0
 %define MSR_EFER      0xc0000080
 %define MSR_EFER_XD   0x800
@@ -204,6 +206,7 @@ ASM_PFX(SmiHandler):
     wrmsr
 
 .7:
+    StuffRsb32
     rsm
 
 ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index 5ff3cd2e73..322b1ab556 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -18,6 +18,8 @@
 ;
 ;-------------------------------------------------------------------------------
 
+%include "StuffRsb.inc"
+
 extern ASM_PFX(SmmInitHandler)
 extern ASM_PFX(mRebasedFlag)
 extern ASM_PFX(mSmmRelocationOriginalAddress)
@@ -75,6 +77,7 @@ BITS 32
     mov     esp, strict dword 0         ; source operand will be patched
 ASM_PFX(gPatchSmmInitStack):
     call    ASM_PFX(SmmInitHandler)
+    StuffRsb32
     rsm
 
 BITS 16
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/StuffRsb.inc b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/StuffRsb.inc
new file mode 100644
index 0000000000..14267c3fde
--- /dev/null
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/StuffRsb.inc
@@ -0,0 +1,55 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Abstract:
+;
+;   This file provides macro definitions for stuffing the Return Stack Buffer (RSB).
+;
+;------------------------------------------------------------------------------
+
+%define RSB_STUFF_ENTRIES 0x20
+
+;
+; parameters:
+; @param 1: register to use as counter (e.g. IA32:eax, X64:rax)
+; @param 2: stack pointer to restore   (IA32:esp, X64:rsp)
+; @param 3: the size of a stack frame  (IA32:4, X64:8)
+;
+%macro StuffRsb 3
+      mov     %1, RSB_STUFF_ENTRIES / 2
+  %%Unroll1:
+      call    %%Unroll2
+  %%SpecTrap1:
+      pause
+      lfence
+      jmp     %%SpecTrap1
+  %%Unroll2:
+      call    %%StuffLoop
+  %%SpecTrap2:
+      pause
+      lfence
+      jmp     %%SpecTrap2
+  %%StuffLoop:
+      dec     %1
+      jnz     %%Unroll1
+      add     %2, RSB_STUFF_ENTRIES * %3 ; Restore the stack pointer
+%endmacro
+
+;
+; RSB stuffing macros for IA32 and X64
+;
+%macro StuffRsb32 0
+      StuffRsb     eax, esp, 4
+%endmacro
+
+%macro StuffRsb64 0
+      StuffRsb     rax, rsp, 8
+%endmacro
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
index 97c7b01d0d..315d0f8670 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
@@ -18,6 +18,8 @@
 ;
 ;-------------------------------------------------------------------------------
 
+%include "StuffRsb.inc"
+
 ;
 ; Variables referrenced by C code
 ;
@@ -217,6 +219,7 @@ _SmiHandler:
     wrmsr
 
 .1:
+    StuffRsb64
     rsm
 
 ASM_PFX(gcSmiHandlerSize)    DW      $ - _SmiEntryPoint
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 0b0c3f28e5..24357d5870 100644
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -18,6 +18,8 @@
 ;
 ;-------------------------------------------------------------------------------
 
+%include "StuffRsb.inc"
+
 extern ASM_PFX(SmmInitHandler)
 extern ASM_PFX(mRebasedFlag)
 extern ASM_PFX(mSmmRelocationOriginalAddress)
@@ -101,6 +103,7 @@ ASM_PFX(gPatchSmmInitStack):
     movdqa  xmm4, [rsp + 0x40]
     movdqa  xmm5, [rsp + 0x50]
 
+    StuffRsb64
     rsm
 
 BITS 16
diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/StuffRsb.inc b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/StuffRsb.inc
new file mode 100644
index 0000000000..14267c3fde
--- /dev/null
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/StuffRsb.inc
@@ -0,0 +1,55 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Abstract:
+;
+;   This file provides macro definitions for stuffing the Return Stack Buffer (RSB).
+;
+;------------------------------------------------------------------------------
+
+%define RSB_STUFF_ENTRIES 0x20
+
+;
+; parameters:
+; @param 1: register to use as counter (e.g. IA32:eax, X64:rax)
+; @param 2: stack pointer to restore   (IA32:esp, X64:rsp)
+; @param 3: the size of a stack frame  (IA32:4, X64:8)
+;
+%macro StuffRsb 3
+      mov     %1, RSB_STUFF_ENTRIES / 2
+  %%Unroll1:
+      call    %%Unroll2
+  %%SpecTrap1:
+      pause
+      lfence
+      jmp     %%SpecTrap1
+  %%Unroll2:
+      call    %%StuffLoop
+  %%SpecTrap2:
+      pause
+      lfence
+      jmp     %%SpecTrap2
+  %%StuffLoop:
+      dec     %1
+      jnz     %%Unroll1
+      add     %2, RSB_STUFF_ENTRIES * %3 ; Restore the stack pointer
+%endmacro
+
+;
+; RSB stuffing macros for IA32 and X64
+;
+%macro StuffRsb32 0
+      StuffRsb     eax, esp, 4
+%endmacro
+
+%macro StuffRsb64 0
+      StuffRsb     rax, rsp, 8
+%endmacro
-- 
2.12.0.windows.1

[PATCH v3 2/2] UefiCpuPkg/SmmCpuFeaturesLib: [CVE-2017-5715] Stuff RSB before RSM

[Hao Wu]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1093

Return Stack Buffer (RSB) is used to predict the target of RET
instructions. When the RSB underflows, some processors may fall back to
using branch predictors. This might impact software using the retpoline
mitigation strategy on those processors.

This commit will add RSB stuffing logic before returning from SMM (the RSM
instruction) to avoid interfering with non-SMM usage of the retpoline
technique.

After the stuffing, RSB entries will contain a trap like:

@SpecTrap:
    pause
    lfence
    jmp     @SpecTrap

A more detailed explanation of the purpose of commit is under the
'Branch target injection mitigation' section of the below link:
https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation

Please note that this commit requires further actions (BZ 1091) to remove
the duplicated 'StuffRsb.inc' files and merge them into one under a
UefiCpuPkg package-level directory (such as UefiCpuPkg/Include/).

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1091

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
---
 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm     |  3 ++
 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm | 10 ++--
 UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/StuffRsb.inc      | 55 ++++++++++++++++++++
 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm      |  3 ++
 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm  |  8 ++-
 UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/StuffRsb.inc       | 55 ++++++++++++++++++++
 6 files changed, 129 insertions(+), 5 deletions(-)

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
index 057ec6d105..31754734bc 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
@@ -18,6 +18,8 @@
 ;
 ;-------------------------------------------------------------------------------
 
+%include "StuffRsb.inc"
+
 %define MSR_IA32_MISC_ENABLE 0x1A0
 %define MSR_EFER      0xc0000080
 %define MSR_EFER_XD   0x800
@@ -206,6 +208,7 @@ CommonHandler:
     wrmsr
 
 .7:
+    StuffRsb32
     rsm
 
 
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm
index 93dc3005b7..bc8dbfe20b 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;
-; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
+; Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>
 ; This program and the accompanying materials
 ; are licensed and made available under the terms and conditions of the BSD License
 ; which accompanies this distribution.  The full text of the license may be found at
@@ -18,6 +18,8 @@
 ;
 ;-------------------------------------------------------------------------------
 
+%include "StuffRsb.inc"
+
 global  ASM_PFX(gcStmPsd)
 
 extern  ASM_PFX(SmmStmExceptionHandler)
@@ -130,7 +132,8 @@ ASM_PFX(OnStmSetup):
     wrmsr
 
 .71:
-  rsm
+    StuffRsb32
+    rsm
 
 global  ASM_PFX(OnStmTeardown)
 ASM_PFX(OnStmTeardown):
@@ -172,4 +175,5 @@ ASM_PFX(OnStmTeardown):
     wrmsr
 
 .72:
-  rsm
+    StuffRsb32
+    rsm
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/StuffRsb.inc b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/StuffRsb.inc
new file mode 100644
index 0000000000..14267c3fde
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/StuffRsb.inc
@@ -0,0 +1,55 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Abstract:
+;
+;   This file provides macro definitions for stuffing the Return Stack Buffer (RSB).
+;
+;------------------------------------------------------------------------------
+
+%define RSB_STUFF_ENTRIES 0x20
+
+;
+; parameters:
+; @param 1: register to use as counter (e.g. IA32:eax, X64:rax)
+; @param 2: stack pointer to restore   (IA32:esp, X64:rsp)
+; @param 3: the size of a stack frame  (IA32:4, X64:8)
+;
+%macro StuffRsb 3
+      mov     %1, RSB_STUFF_ENTRIES / 2
+  %%Unroll1:
+      call    %%Unroll2
+  %%SpecTrap1:
+      pause
+      lfence
+      jmp     %%SpecTrap1
+  %%Unroll2:
+      call    %%StuffLoop
+  %%SpecTrap2:
+      pause
+      lfence
+      jmp     %%SpecTrap2
+  %%StuffLoop:
+      dec     %1
+      jnz     %%Unroll1
+      add     %2, RSB_STUFF_ENTRIES * %3 ; Restore the stack pointer
+%endmacro
+
+;
+; RSB stuffing macros for IA32 and X64
+;
+%macro StuffRsb32 0
+      StuffRsb     eax, esp, 4
+%endmacro
+
+%macro StuffRsb64 0
+      StuffRsb     rax, rsp, 8
+%endmacro
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
index 90a9fd489b..c0a0f98f11 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
@@ -18,6 +18,8 @@
 ;
 ;-------------------------------------------------------------------------------
 
+%include "StuffRsb.inc"
+
 ;
 ; Variables referrenced by C code
 ;
@@ -221,6 +223,7 @@ CommonHandler:
     wrmsr
 
 .1:
+    StuffRsb64
     rsm
 
 _StmSmiHandler:
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm
index b0ab87b0d4..3e5295986b 100644
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm
@@ -18,6 +18,8 @@
 ;
 ;-------------------------------------------------------------------------------
 
+%include "StuffRsb.inc"
+
 global  ASM_PFX(gcStmPsd)
 
 extern  ASM_PFX(SmmStmExceptionHandler)
@@ -131,7 +133,8 @@ ASM_PFX(OnStmSetup):
     wrmsr
 
 .11:
-  rsm
+    StuffRsb64
+    rsm
 
 global ASM_PFX(OnStmTeardown)
 ASM_PFX(OnStmTeardown):
@@ -175,4 +178,5 @@ ASM_PFX(OnStmTeardown):
     wrmsr
 
 .12:
-  rsm
+    StuffRsb64
+    rsm
diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/StuffRsb.inc b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/StuffRsb.inc
new file mode 100644
index 0000000000..14267c3fde
--- /dev/null
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/StuffRsb.inc
@@ -0,0 +1,55 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
+; This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution.  The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php.
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Abstract:
+;
+;   This file provides macro definitions for stuffing the Return Stack Buffer (RSB).
+;
+;------------------------------------------------------------------------------
+
+%define RSB_STUFF_ENTRIES 0x20
+
+;
+; parameters:
+; @param 1: register to use as counter (e.g. IA32:eax, X64:rax)
+; @param 2: stack pointer to restore   (IA32:esp, X64:rsp)
+; @param 3: the size of a stack frame  (IA32:4, X64:8)
+;
+%macro StuffRsb 3
+      mov     %1, RSB_STUFF_ENTRIES / 2
+  %%Unroll1:
+      call    %%Unroll2
+  %%SpecTrap1:
+      pause
+      lfence
+      jmp     %%SpecTrap1
+  %%Unroll2:
+      call    %%StuffLoop
+  %%SpecTrap2:
+      pause
+      lfence
+      jmp     %%SpecTrap2
+  %%StuffLoop:
+      dec     %1
+      jnz     %%Unroll1
+      add     %2, RSB_STUFF_ENTRIES * %3 ; Restore the stack pointer
+%endmacro
+
+;
+; RSB stuffing macros for IA32 and X64
+;
+%macro StuffRsb32 0
+      StuffRsb     eax, esp, 4
+%endmacro
+
+%macro StuffRsb64 0
+      StuffRsb     rax, rsp, 8
+%endmacro
-- 
2.12.0.windows.1

Re: [PATCH v3 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: [CVE-2017-5715] Stuff RSB before RSM

[Laszlo Ersek]

On 08/17/18 04:35, Hao Wu wrote:
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1093
> 
> Return Stack Buffer (RSB) is used to predict the target of RET
> instructions. When the RSB underflows, some processors may fall back to
> using branch predictors. This might impact software using the retpoline
> mitigation strategy on those processors.
> 
> This commit will add RSB stuffing logic before returning from SMM (the RSM
> instruction) to avoid interfering with non-SMM usage of the retpoline
> technique.
> 
> After the stuffing, RSB entries will contain a trap like:
> 
> @SpecTrap:
>     pause
>     lfence
>     jmp     @SpecTrap
> 
> A more detailed explanation of the purpose of commit is under the
> 'Branch target injection mitigation' section of the below link:
> https://software.intel.com/security-software-guidance/insights/host-firmware-speculative-execution-side-channel-mitigation
> 
> Please note that this commit requires further actions (BZ 1091) to remove
> the duplicated 'StuffRsb.inc' files and merge them into one under a
> UefiCpuPkg package-level directory (such as UefiCpuPkg/Include/).
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1091
> 
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Hao Wu <hao.a.wu@intel.com>
> Acked-by: Laszlo Ersek <lersek@redhat.com>
> Regression-tested-by: Laszlo Ersek <lersek@redhat.com>
> ---
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm |  3 ++
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm  |  3 ++
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/StuffRsb.inc  | 55 ++++++++++++++++++++
>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm  |  3 ++
>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm   |  3 ++
>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/StuffRsb.inc   | 55 ++++++++++++++++++++
>  6 files changed, 122 insertions(+)
> 
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
> index 509e7a0a66..6bbc339c53 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm
> @@ -18,6 +18,8 @@
>  ;
>  ;-------------------------------------------------------------------------------
>  
> +%include "StuffRsb.inc"
> +
>  %define MSR_IA32_MISC_ENABLE 0x1A0
>  %define MSR_EFER      0xc0000080
>  %define MSR_EFER_XD   0x800
> @@ -204,6 +206,7 @@ ASM_PFX(SmiHandler):
>      wrmsr
>  
>  .7:
> +    StuffRsb32
>      rsm
>  
>  ASM_PFX(gcSmiHandlerSize): DW $ - _SmiEntryPoint
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
> index 5ff3cd2e73..322b1ab556 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
> @@ -18,6 +18,8 @@
>  ;
>  ;-------------------------------------------------------------------------------
>  
> +%include "StuffRsb.inc"
> +
>  extern ASM_PFX(SmmInitHandler)
>  extern ASM_PFX(mRebasedFlag)
>  extern ASM_PFX(mSmmRelocationOriginalAddress)
> @@ -75,6 +77,7 @@ BITS 32
>      mov     esp, strict dword 0         ; source operand will be patched
>  ASM_PFX(gPatchSmmInitStack):
>      call    ASM_PFX(SmmInitHandler)
> +    StuffRsb32
>      rsm
>  
>  BITS 16
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/StuffRsb.inc b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/StuffRsb.inc
> new file mode 100644
> index 0000000000..14267c3fde
> --- /dev/null
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/StuffRsb.inc
> @@ -0,0 +1,55 @@
> +;------------------------------------------------------------------------------
> +;
> +; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> +; This program and the accompanying materials
> +; are licensed and made available under the terms and conditions of the BSD License
> +; which accompanies this distribution.  The full text of the license may be found at
> +; http://opensource.org/licenses/bsd-license.php.
> +;
> +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +;
> +; Abstract:
> +;
> +;   This file provides macro definitions for stuffing the Return Stack Buffer (RSB).
> +;
> +;------------------------------------------------------------------------------
> +
> +%define RSB_STUFF_ENTRIES 0x20
> +
> +;
> +; parameters:
> +; @param 1: register to use as counter (e.g. IA32:eax, X64:rax)
> +; @param 2: stack pointer to restore   (IA32:esp, X64:rsp)
> +; @param 3: the size of a stack frame  (IA32:4, X64:8)
> +;
> +%macro StuffRsb 3
> +      mov     %1, RSB_STUFF_ENTRIES / 2
> +  %%Unroll1:
> +      call    %%Unroll2
> +  %%SpecTrap1:
> +      pause
> +      lfence
> +      jmp     %%SpecTrap1
> +  %%Unroll2:
> +      call    %%StuffLoop
> +  %%SpecTrap2:
> +      pause
> +      lfence
> +      jmp     %%SpecTrap2
> +  %%StuffLoop:
> +      dec     %1
> +      jnz     %%Unroll1
> +      add     %2, RSB_STUFF_ENTRIES * %3 ; Restore the stack pointer
> +%endmacro
> +
> +;
> +; RSB stuffing macros for IA32 and X64
> +;
> +%macro StuffRsb32 0
> +      StuffRsb     eax, esp, 4
> +%endmacro
> +
> +%macro StuffRsb64 0
> +      StuffRsb     rax, rsp, 8
> +%endmacro
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
> index 97c7b01d0d..315d0f8670 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm
> @@ -18,6 +18,8 @@
>  ;
>  ;-------------------------------------------------------------------------------
>  
> +%include "StuffRsb.inc"
> +
>  ;
>  ; Variables referrenced by C code
>  ;
> @@ -217,6 +219,7 @@ _SmiHandler:
>      wrmsr
>  
>  .1:
> +    StuffRsb64
>      rsm
>  
>  ASM_PFX(gcSmiHandlerSize)    DW      $ - _SmiEntryPoint
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
> index 0b0c3f28e5..24357d5870 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
> @@ -18,6 +18,8 @@
>  ;
>  ;-------------------------------------------------------------------------------
>  
> +%include "StuffRsb.inc"
> +
>  extern ASM_PFX(SmmInitHandler)
>  extern ASM_PFX(mRebasedFlag)
>  extern ASM_PFX(mSmmRelocationOriginalAddress)
> @@ -101,6 +103,7 @@ ASM_PFX(gPatchSmmInitStack):
>      movdqa  xmm4, [rsp + 0x40]
>      movdqa  xmm5, [rsp + 0x50]
>  
> +    StuffRsb64
>      rsm
>  
>  BITS 16
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/StuffRsb.inc b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/StuffRsb.inc
> new file mode 100644
> index 0000000000..14267c3fde
> --- /dev/null
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/StuffRsb.inc
> @@ -0,0 +1,55 @@
> +;------------------------------------------------------------------------------
> +;
> +; Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>
> +; This program and the accompanying materials
> +; are licensed and made available under the terms and conditions of the BSD License
> +; which accompanies this distribution.  The full text of the license may be found at
> +; http://opensource.org/licenses/bsd-license.php.
> +;
> +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
> +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
> +;
> +; Abstract:
> +;
> +;   This file provides macro definitions for stuffing the Return Stack Buffer (RSB).
> +;
> +;------------------------------------------------------------------------------
> +
> +%define RSB_STUFF_ENTRIES 0x20
> +
> +;
> +; parameters:
> +; @param 1: register to use as counter (e.g. IA32:eax, X64:rax)
> +; @param 2: stack pointer to restore   (IA32:esp, X64:rsp)
> +; @param 3: the size of a stack frame  (IA32:4, X64:8)
> +;
> +%macro StuffRsb 3
> +      mov     %1, RSB_STUFF_ENTRIES / 2
> +  %%Unroll1:
> +      call    %%Unroll2
> +  %%SpecTrap1:
> +      pause
> +      lfence
> +      jmp     %%SpecTrap1
> +  %%Unroll2:
> +      call    %%StuffLoop
> +  %%SpecTrap2:
> +      pause
> +      lfence
> +      jmp     %%SpecTrap2
> +  %%StuffLoop:
> +      dec     %1
> +      jnz     %%Unroll1
> +      add     %2, RSB_STUFF_ENTRIES * %3 ; Restore the stack pointer
> +%endmacro
> +
> +;
> +; RSB stuffing macros for IA32 and X64
> +;
> +%macro StuffRsb32 0
> +      StuffRsb     eax, esp, 4
> +%endmacro
> +
> +%macro StuffRsb64 0
> +      StuffRsb     rax, rsp, 8
> +%endmacro
> 

Thank you Hao, this looks great.
Laszlo

Re: [PATCH v3 0/2] UefiCpuPkg: [CVE-2017-5715] Stuff RSB before RSM

[Dong, Eric]

Reviewed-by: Eric Dong <eric.dong@intel.com>  for this serial.

> -----Original Message-----
> From: Wu, Hao A
> Sent: Friday, August 17, 2018 10:35 AM
> To: edk2-devel@lists.01.org
> Cc: Wu, Hao A <hao.a.wu@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>;
> Dong, Eric <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>; Kinney,
> Michael D <michael.d.kinney@intel.com>
> Subject: [PATCH v3 0/2] UefiCpuPkg: [CVE-2017-5715] Stuff RSB before RSM
> 
> V3 changes:
> A. Add relating CVE issue number to the commits' subject line.
> 
> B. Keep the URL links within log messages unwrapped.
> 
> C. Add TianoCore Bugzilla link reference to each commits.
> 
> D. Mention further actions should be taken after pushing the series in log
>    messages.
> 
> E. Refine file description comments for StuffRsb.inc files.
> 
> V2 changes:
> A. Refine commit log message to clarify the purpose of the series
> 
> B. Extract the RSB stuffing logic to INC files to avoid code duplication:
> When compiling .NASM source files, the current build rule does not support
> including files other than the .NASM file directory, this series will duplicate
> the StuffRsb.inc file together with the .NASM files at this moment.
> 
> Please consider this approach as the first stage, I have filed a Bugzilla for
> adding $(INC)-like support when compiling .NASM files:
> https://bugzilla.tianocore.org/show_bug.cgi?id=1085
> 
> After the above support is added, the next step will be taken to remove those
> duplicated StuffRsb.inc files and put it under a common include directory like:
> UefiCpuPkg/Include/
> 
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Michael D Kinney <michael.d.kinney@intel.com>
> 
> Hao Wu (2):
>   UefiCpuPkg/PiSmmCpuDxeSmm: [CVE-2017-5715] Stuff RSB before RSM
>   UefiCpuPkg/SmmCpuFeaturesLib: [CVE-2017-5715] Stuff RSB before RSM
> 
>  UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm     |  3 ++
>  UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm | 10 ++--
>  UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/StuffRsb.inc      | 55
> ++++++++++++++++++++
>  UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm      |  3 ++
>  UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm  |  8 ++-
>  UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/StuffRsb.inc       | 55
> ++++++++++++++++++++
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiEntry.nasm                |  3 ++
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm                 |  3 ++
>  UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/StuffRsb.inc                 | 55
> ++++++++++++++++++++
>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmiEntry.nasm                 |  3 ++
>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm                  |  3 ++
>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/StuffRsb.inc                  | 55
> ++++++++++++++++++++
>  12 files changed, 251 insertions(+), 5 deletions(-)  create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/StuffRsb.inc
>  create mode 100644
> UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/StuffRsb.inc
>  create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/StuffRsb.inc
>  create mode 100644 UefiCpuPkg/PiSmmCpuDxeSmm/X64/StuffRsb.inc
> 
> --
> 2.12.0.windows.1