From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=134.134.136.126; helo=mga18.intel.com; envelope-from=jian.j.wang@intel.com; receiver=edk2-devel@lists.01.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3AC1A210F622D for ; Sun, 19 Aug 2018 23:42:30 -0700 (PDT) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 19 Aug 2018 23:42:29 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.53,263,1531810800"; d="scan'208";a="66306063" Received: from jwang36-mobl2.ccr.corp.intel.com ([10.239.193.73]) by orsmga007.jf.intel.com with ESMTP; 19 Aug 2018 23:42:13 -0700 From: Jian J Wang To: edk2-devel@lists.01.org Date: Mon, 20 Aug 2018 14:41:57 +0800 Message-Id: <20180820064201.16592-1-jian.j.wang@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 Subject: [PATCH 0/4] Support non-stop mode in heap guard and null detection X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 Aug 2018 06:42:30 -0000 Background: Heap Guard and NULL Pointer Detection are very useful features to detect code flaw in EDK II. If an issue is detected, #PF exception will be triggered and the BIOS will enter into dead loop, which is the default behavior of exception handling. From QA perspective, this default behavior will block them to collect all tests result in reasonable time. Solution: This patch series update CpuDxe, PiSmmCpuDxeSmm and CpuExceptionHandlerLib to allow the code to continue execution after #PF. The mechanism behind it is the same as SMM Profile feature, in which a special #PF handler is registered to set the page causing #PF to be 'present' and setup single steop trap, then return the control back to the instruction accessing that page. Once the instruction is re-executed, a #DB is triggered and a special handler for it will be called to reset the page back to 'not-present'. Usage: The non-stop mode is enabled/disabled by BIT6 of following PCDs gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask The default setting is 'disable'. BZ Tracker: https://bugzilla.tianocore.org/show_bug.cgi?id=1095 Jian J Wang (4): MdeModulePkg/MdeModulePkg.dec: add new settings for PCDs UefiCpuPkg/CpuExceptionHandlerLib: Setup single step in #PF handler UefiCpuPkg/CpuDxe: implement non-stop mode for uefi UefiCpuPkg/PiSmmCpuDxeSmm: implement non-stop mode for SMM MdeModulePkg/MdeModulePkg.dec | 4 +- UefiCpuPkg/CpuDxe/CpuDxe.h | 39 +++ UefiCpuPkg/CpuDxe/CpuDxe.inf | 3 + UefiCpuPkg/CpuDxe/CpuMp.c | 34 ++- UefiCpuPkg/CpuDxe/CpuPageTable.c | 271 +++++++++++++++++++++ .../Ia32/ExceptionHandlerAsm.nasm | 7 + .../Ia32/ExceptionTssEntryAsm.nasm | 4 +- .../X64/ExceptionHandlerAsm.nasm | 4 + UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/PageTbl.c | 43 ++-- UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmiException.nasm | 3 +- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c | 60 ++++- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.h | 15 ++ UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfileInternal.h | 6 + UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 43 ++-- 14 files changed, 495 insertions(+), 41 deletions(-) -- 2.16.2.windows.1