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[2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id e137-v6sm3215074wma.20.2018.08.22.08.01.19 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 08:01:20 -0700 (PDT) Date: Wed, 22 Aug 2018 16:01:18 +0100 From: Leif Lindholm To: Ming Huang Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org, Sun Yuanchen Message-ID: <20180822150118.bl6t2ubahov44r5p@bivouac.eciton.net> References: <20180814080903.50466-1-ming.huang@linaro.org> <20180814080903.50466-32-ming.huang@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180814080903.50466-32-ming.huang@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v2 31/43] Hisilicon/D0x: Update SMBIOS type9 info X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Aug 2018 15:01:22 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Aug 14, 2018 at 04:08:51PM +0800, Ming Huang wrote: > From: Sun Yuanchen > > Move board level code to OemMiscLibD0x for unifying D0x. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Sun Yuanchen > --- > Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf | 1 + > Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf | 1 + > Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf | 4 + > Platform/Hisilicon/D06/Include/Library/CpldD06.h | 2 + > Silicon/Hisilicon/Include/Library/OemMiscLib.h | 1 + > Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c | 24 ++++++ > Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c | 27 +++++- > Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c | 90 ++++++++++++++++++++ > Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c | 14 +-- > 9 files changed, 151 insertions(+), 13 deletions(-) > > diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf > index 310bbaea84..0fa7fdf80f 100644 > --- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf > +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf > @@ -34,6 +34,7 @@ > Silicon/Hisilicon/HisiPkg.dec > > [LibraryClasses] > + BaseMemoryLib > PcdLib > TimerLib > > diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf > index bf44ff7440..022c3e940a 100644 > --- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf > +++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf > @@ -33,6 +33,7 @@ > Silicon/Hisilicon/HisiPkg.dec > > [LibraryClasses] > + BaseMemoryLib > PcdLib > TimerLib > > diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf > index 8f68f7cec5..bd984a6fe3 100644 > --- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf > +++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf > @@ -30,9 +30,13 @@ > ArmPkg/ArmPkg.dec > MdeModulePkg/MdeModulePkg.dec > MdePkg/MdePkg.dec > + Platform/Hisilicon/D06/D06.dec > Silicon/Hisilicon/HisiPkg.dec > > [LibraryClasses] > + BaseMemoryLib > + CpldIoLib > + IoLib > PcdLib > SerdesLib > TimerLib > diff --git a/Platform/Hisilicon/D06/Include/Library/CpldD06.h b/Platform/Hisilicon/D06/Include/Library/CpldD06.h > index be3548c8d1..ec9b49f4e7 100644 > --- a/Platform/Hisilicon/D06/Include/Library/CpldD06.h > +++ b/Platform/Hisilicon/D06/Include/Library/CpldD06.h > @@ -29,6 +29,8 @@ > #define CPLD_LOGIC_COMPILE_DAY (0x3) > > #define CPLD_RISER_PRSNT_FLAG 0x40 > +#define CPU1_RISER_PRESENT BIT6 > +#define CPU0_RISER_PRESENT BIT7 > #define CPLD_RISER2_BOARD_ID 0x44 > > #define CPLD_X8_X8_X8_BOARD_ID 0x92 > diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h > index efecb9aa77..86ea6a1b3d 100644 > --- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h > +++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h > @@ -34,6 +34,7 @@ typedef struct _REPORT_PCIEDIDVID2BMC{ > UINTN Slot; > }REPORT_PCIEDIDVID2BMC; > extern REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX]; > +extern VOID GetPciDidVid (REPORT_PCIEDIDVID2BMC *Report); > > BOOLEAN OemIsSocketPresent (UINTN Socket); > VOID CoreSelectBoot(VOID); > diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c > index fa1039bda1..c80500276f 100644 > --- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c > +++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c > @@ -15,6 +15,7 @@ > > #include > > +#include > #include > #include > #include > @@ -31,6 +32,29 @@ REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = { > {0xFFFF,0xFFFF,0xFFFF,0xFFFF} > }; > > +REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P[PCIEDEVICE_REPORT_MAX] = { Should really drop that _ from the variable name. > + {0x79,0,0,0}, > + {0xFF,0xFF,0xFF,1}, > + {0xC1,0,0,2}, > + {0xF9,0,0,3}, > + {0xFF,0xFF,0xFF,4}, > + {0x11,0,0,5}, > + {0x31,0,0,6}, > + {0x21,0,0,7} > +}; > + > +VOID > +GetPciDidVid ( > + REPORT_PCIEDIDVID2BMC *Report > + ) > +{ > + if (OemIsMpBoot ()) { > + (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P, sizeof (PcieDeviceToReport_2P)); > + } else { > + (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport, sizeof (PcieDeviceToReport)); I think these lines got longer from v1? Please wrap. With these changes: Reviewed-by: Leif Lindholm / Leif