From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 12389210F3D9D for ; Wed, 22 Aug 2018 08:04:57 -0700 (PDT) Received: by mail-wm0-x241.google.com with SMTP id c14-v6so2326479wmb.4 for ; Wed, 22 Aug 2018 08:04:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=4ySWSVudjrx4Wl4so2wJm8z4ANHPFbCPv+525D0DGiQ=; b=ImDR4W7U39uEzvLj4EljwusEr4Z5WL6no1Nl5QPyt5vyeVRBvlm3VZK9ZmRsX4/P43 8Xp13G1CWmaVqsC1uD3fbBteKQ+pkwnQj0VxlFRa34KltMafXONaQ58S8nYa4q4im1+Q zg/mXAIhCXFe0CxxeCX6FQcu0XDtZwn3bxpQQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=4ySWSVudjrx4Wl4so2wJm8z4ANHPFbCPv+525D0DGiQ=; b=CrcP35V7pcs6ivNaiZVyCbbIo11ye+d751Wu+rd5p1XhysK39XHdoFT6+KQcLOQtYa XdmdXOJ8/Pa5O2D8bLA7irRmg8ZFL5po5nmo1ACNf7mJLgNOBsBTDaJ/yl/wTfBiJDHq wtGNCuRCnnQFCjK+EhgxHz3wwkUdiKlMb8VLkib8QmARDmd2ymS06220dZ8ctKxqKHhi sQMSqxkE2HktSu2Et72MY8Mbe383h3Kvpo8hngYABqZl1gQvvQj7dmQFzt5VyZVCktuM 6iAhUAN3qlvzvYcs203+9J3CxZ7mmw9yqx635wYsHA9E8lYbzT2domhYSCVkX+UwAxaw JzOA== X-Gm-Message-State: APzg51AbCbKvbzdQz+EbWJmmtB7YCuQckpGUi8h/NVIk0YURY5US0flf IGjcBvA0pOUgC9g/lp+9mIfOOg== X-Google-Smtp-Source: ANB0VdZGCnHWOPSHCuqEL0hEWTWNa6GNF/jMG8f9Q7162dACW8rjnxAvTQF5GXRIKrWna6pVVYVe1Q== X-Received: by 2002:a1c:ca0f:: with SMTP id a15-v6mr2534255wmg.102.1534950296553; Wed, 22 Aug 2018 08:04:56 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id m8-v6sm1469008wrn.72.2018.08.22.08.04.54 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 08:04:55 -0700 (PDT) Date: Wed, 22 Aug 2018 16:04:53 +0100 From: Leif Lindholm To: Ming Huang Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org Message-ID: <20180822150453.rye5atlvc2wurxly@bivouac.eciton.net> References: <20180814080903.50466-1-ming.huang@linaro.org> <20180814080903.50466-33-ming.huang@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180814080903.50466-33-ming.huang@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v2 32/43] Platform/Hisilicon/D06: Add EarlyConfigPeim peim X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Aug 2018 15:04:58 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Aug 14, 2018 at 04:08:52PM +0800, Ming Huang wrote: > This peim configuare SMMU,BSP,MN(Miscellaneous Node). configuare still needs to change to configures With that change: Reviewed-by: Leif Lindholm > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ming Huang > --- > Platform/Hisilicon/D06/D06.dsc | 1 + > Platform/Hisilicon/D06/D06.fdf | 1 + > Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf | 50 +++++++++ > Silicon/Hisilicon/Include/Library/OemAddressMapLib.h | 2 + > Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c | 107 ++++++++++++++++++++ > 5 files changed, 161 insertions(+) > > diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc > index 5571028f42..3de09ea870 100644 > --- a/Platform/Hisilicon/D06/D06.dsc > +++ b/Platform/Hisilicon/D06/D06.dsc > @@ -263,6 +263,7 @@ > MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf > MdeModulePkg/Universal/Variable/Pei/VariablePei.inf > > + Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf > Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf > > MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { > diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf > index 184d5d4dcf..bd3ea47226 100644 > --- a/Platform/Hisilicon/D06/D06.fdf > +++ b/Platform/Hisilicon/D06/D06.fdf > @@ -359,6 +359,7 @@ READ_LOCK_STATUS = TRUE > INF ArmPkg/Drivers/CpuPei/CpuPei.inf > INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf > INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf > + INF Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf > > INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf > > diff --git a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf > new file mode 100644 > index 0000000000..8296ee02de > --- /dev/null > +++ b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf > @@ -0,0 +1,50 @@ > +#/** @file > +# > +# Copyright (c) 2018, Hisilicon Limited. All rights reserved. > +# Copyright (c) 2017, Linaro Limited. All rights reserved. > +# > +# This program and the accompanying materials > +# are licensed and made available under the terms and conditions of the BSD License > +# which accompanies this distribution. The full text of the license may be found at > +# http://opensource.org/licenses/bsd-license.php > +# > +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +# > +#**/ > + > + > +[Defines] > + INF_VERSION = 0x0001001A > + BASE_NAME = EarlyConfigPeimD06 > + FILE_GUID = FB8C65EB-0199-40C3-A82B-029921A9E9B3 > + MODULE_TYPE = PEIM > + VERSION_STRING = 1.0 > + ENTRY_POINT = EarlyConfigEntry > + > +[Sources.common] > + EarlyConfigPeimD06.c > + > +[Packages] > + ArmPkg/ArmPkg.dec > + MdeModulePkg/MdeModulePkg.dec > + MdePkg/MdePkg.dec > + Silicon/Hisilicon/HisiPkg.dec > + > +[LibraryClasses] > + ArmLib > + CacheMaintenanceLib > + DebugLib > + IoLib > + PcdLib > + PeimEntryPoint > + PlatformSysCtrlLib > + > +[Pcd] > + gHisiTokenSpaceGuid.PcdMailBoxAddress > + gHisiTokenSpaceGuid.PcdPeriSubctrlAddress > + gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable > + > +[Depex] > +## As we will clean mailbox in this module, need to wait memory init complete > + gEfiPeiMemoryDiscoveredPpiGuid > diff --git a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h > index 332a79343f..b330be09ba 100644 > --- a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h > +++ b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h > @@ -16,6 +16,8 @@ > #ifndef _OEM_ADDRESS_MAP_LIB_H_ > #define _OEM_ADDRESS_MAP_LIB_H_ > > +#include "PlatformArch.h" > + > typedef struct _DDRC_BASE_ID{ > UINTN Base; > UINTN Id; > diff --git a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c > new file mode 100644 > index 0000000000..0790f7941a > --- /dev/null > +++ b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c > @@ -0,0 +1,107 @@ > +/** @file > +* > +* Copyright (c) 2018, Hisilicon Limited. All rights reserved. > +* Copyright (c) 2018, Linaro Limited. All rights reserved. > +* > +* This program and the accompanying materials > +* are licensed and made available under the terms and conditions of the BSD License > +* which accompanies this distribution. The full text of the license may be found at > +* http://opensource.org/licenses/bsd-license.php > +* > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. > +* > +**/ > + > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define PERI_SUBCTRL_BASE (0x40000000) > +#define MDIO_SUBCTRL_BASE (0x60000000) > +#define PCIE2_SUBCTRL_BASE (0xA0000000) > +#define PCIE0_SUBCTRL_BASE (0xB0000000) > +#define ALG_BASE (0xD0000000) > + > +#define SC_BROADCAST_EN_REG (0x16220) > +#define SC_BROADCAST_SCL1_ADDR0_REG (0x16230) > +#define SC_BROADCAST_SCL1_ADDR1_REG (0x16234) > +#define SC_BROADCAST_SCL2_ADDR0_REG (0x16238) > +#define SC_BROADCAST_SCL2_ADDR1_REG (0x1623C) > +#define SC_BROADCAST_SCL3_ADDR0_REG (0x16240) > +#define SC_BROADCAST_SCL3_ADDR1_REG (0x16244) > +#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG (0x1000) > +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG (0x1010) > +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG (0x1014) > +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (0x1018) > +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (0x101C) > +#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG (0x1200) > +#define SC_ITS_M3_INT_MUX_SEL_REG (0x21F0) > +#define SC_TM_CLKEN0_REG (0x2050) > + > +#define SC_TM_CLKEN0_REG_VALUE (0x3) > +#define SC_BROADCAST_EN_REG_VALUE (0x7) > +#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE0 (0x0) > +#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE1 (0x40016260) > +#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE2 (0x60016260) > +#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE3 (0x400) > +#define SC_ITS_M3_INT_MUX_SEL_REG_VALUE (0x7) > +#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0 (0x0) > +#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0 (0x27) > +#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1 (0x2F) > +#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2 (0x77) > +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0 (0x178033) > +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0 (0x17003c) > +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0 (0x15003d) > +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1 (0x170035) > +#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0 (0x16003e) > + > +STATIC > +VOID > +QResetAp ( > + VOID > + ) > +{ > + MmioWrite64 (FixedPcdGet64 (PcdMailBoxAddress), 0x0); > + (VOID)WriteBackInvalidateDataCacheRange ( > + (VOID *)FixedPcdGet64 (PcdMailBoxAddress), > + sizeof (UINT64) > + ); > + > + //SCCL A > + if (!PcdGet64 (PcdTrustedFirmwareEnable)) { > + StartupAp (); > + } > +} > + > + > +EFI_STATUS > +EFIAPI > +EarlyConfigEntry ( > + IN EFI_PEI_FILE_HANDLE FileHandle, > + IN CONST EFI_PEI_SERVICES **PeiServices > + ) > +{ > + DEBUG ((DEBUG_INFO,"SMMU CONFIG.........")); > + (VOID)SmmuConfigForBios (); > + DEBUG ((DEBUG_INFO,"Done\n")); > + > + DEBUG ((DEBUG_INFO,"AP CONFIG.........")); > + (VOID)QResetAp (); > + DEBUG ((DEBUG_INFO,"Done\n")); > + > + DEBUG ((DEBUG_INFO,"MN CONFIG.........")); > + (VOID)MN_CONFIG (); > + DEBUG ((DEBUG_INFO,"Done\n")); > + > + return EFI_SUCCESS; > +} > + > -- > 2.17.0 >