From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::244; helo=mail-wm0-x244.google.com; envelope-from=leif.lindholm@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 31F74211F887B for ; Wed, 22 Aug 2018 08:33:40 -0700 (PDT) Received: by mail-wm0-x244.google.com with SMTP id l2-v6so12376188wme.1 for ; Wed, 22 Aug 2018 08:33:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=vZNscybhGlbFbAh9vb794e7O+dkzB80tBqP7OjvgDuY=; b=G1Ihr8t0iHSNqZ5WtpWu+jHRVbBEbNfzblJGoCg8FsplCLV7TogCx6ur5OiKLwqZ/Z wO72eSZ37hQvBJiR1DiPzk1BqWkoiYD7N0mMt4eTTRnt1TZNyp9aBxxl8ke/HqNb45nE swfKXQE1TbVs1l/3cMfS48PjU9r0l2+Tjzr6Q= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=vZNscybhGlbFbAh9vb794e7O+dkzB80tBqP7OjvgDuY=; b=TTVEW9XEqRWyZvgBYBbMXPOXRb1Wqgf4M6MFuBpWbVmuQPWQfaGKUEokWBg0pMsaek pGUq49xZZwb780T52L0XEr+U97bjtMHIZYoaUBIWCEe7nYDVgX5tA3Oy3ClkH6wXfR1j NwP3dslguXE0znalZem6rIJa0LoYQf1+CtEvFLz2v2/ml3xrYB23UXPWb8yoFXxNCTgp QkZmUqijBBaQrLUP9NtdOS4cnxNaRBmNtzjMMgDKtx6jr7eW2f7+6lMKogJQs/IUPMKV Z0Nwu8cOXYDbz2+M0EZ5D/SrU9tgxVuPnzltP6JRQkYmN7gGxZXxDZldjQHW9Mex8smC LXxQ== X-Gm-Message-State: APzg51A6ubblHv/61ldB7IWQQ9tfkFfOmeDLTtmxBUVfeGp1Y07V3dOW DiFZr06B7osLQBDuwBdfeAySig== X-Google-Smtp-Source: ANB0VdYFFbBzSGBFCZ7ZMMGDT+eikN1baNskqVTrGJu/hw9fh6isfJhdkmGpmAnalT7kYdHbNbzOXw== X-Received: by 2002:a1c:7dc7:: with SMTP id y190-v6mr1719934wmc.62.1534952018740; Wed, 22 Aug 2018 08:33:38 -0700 (PDT) Received: from bivouac.eciton.net (bivouac.eciton.net. [2a00:1098:0:86:1000:23:0:2]) by smtp.gmail.com with ESMTPSA id a184-v6sm1827540wmh.41.2018.08.22.08.33.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 22 Aug 2018 08:33:37 -0700 (PDT) Date: Wed, 22 Aug 2018 16:33:36 +0100 From: Leif Lindholm To: Ming Huang Cc: linaro-uefi@lists.linaro.org, edk2-devel@lists.01.org, graeme.gregory@linaro.org, ard.biesheuvel@linaro.org, michael.d.kinney@intel.com, lersek@redhat.com, guoheyi@huawei.com, wanghuiqiang@huawei.com, huangming23@huawei.com, zhangjinsong2@huawei.com, huangdaode@hisilicon.com, john.garry@huawei.com, xinliang.liu@linaro.org Message-ID: <20180822153336.mllu5y6fr72surxn@bivouac.eciton.net> References: <20180814080903.50466-1-ming.huang@linaro.org> <20180814080903.50466-36-ming.huang@linaro.org> MIME-Version: 1.0 In-Reply-To: <20180814080903.50466-36-ming.huang@linaro.org> User-Agent: NeoMutt/20170113 (1.7.2) Subject: Re: [PATCH edk2-platforms v2 35/43] Silicon/Hisilicon/D06: Add some Lpc macro to LpcLib.h X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Aug 2018 15:33:40 -0000 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Tue, Aug 14, 2018 at 04:08:55PM +0800, Ming Huang wrote: > Add some Lpc macro to LpcLib.h for D06. > Unaddressed feedback from v1: I have no issue with this patch, but can you explain when these macros are intended to be used? And if in this set, move this patch immediately before the patch than needs it? Again, this patch is not D06 specific, and the subject should reflect that. / Leif > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Ming Huang > --- > Silicon/Hisilicon/Include/Library/LpcLib.h | 51 +++++++++++++++++++- > 1 file changed, 49 insertions(+), 2 deletions(-) > > diff --git a/Silicon/Hisilicon/Include/Library/LpcLib.h b/Silicon/Hisilicon/Include/Library/LpcLib.h > index 236a52ba45..5cf08ccde1 100755 > --- a/Silicon/Hisilicon/Include/Library/LpcLib.h > +++ b/Silicon/Hisilicon/Include/Library/LpcLib.h > @@ -1,7 +1,7 @@ > /** @file > * > -* Copyright (c) 2016, Hisilicon Limited. All rights reserved. > -* Copyright (c) 2016, Linaro Limited. All rights reserved. > +* Copyright (c) 2016-2018, Hisilicon Limited. All rights reserved. > +* Copyright (c) 2016-2018, Linaro Limited. All rights reserved. > * > * This program and the accompanying materials > * are licensed and made available under the terms and conditions of the BSD License > @@ -18,6 +18,53 @@ > > #include > > +#define PCIE_SUBSYS_IOMUX 0x201100000 > +#define PCIE_SUBSYS_IOMG019 (PCIE_SUBSYS_IOMUX + 0x48) > +#define PCIE_SUBSYS_IOMG020 (PCIE_SUBSYS_IOMUX + 0x4C) > +#define PCIE_SUBSYS_IOMG021 (PCIE_SUBSYS_IOMUX + 0x50) > +#define PCIE_SUBSYS_IOMG022 (PCIE_SUBSYS_IOMUX + 0x54) > +#define PCIE_SUBSYS_IOMG023 (PCIE_SUBSYS_IOMUX + 0x58) > +#define PCIE_SUBSYS_IOMG024 (PCIE_SUBSYS_IOMUX + 0x5C) > +#define PCIE_SUBSYS_IOMG025 (PCIE_SUBSYS_IOMUX + 0x60) > +#define PCIE_SUBSYS_IOMG028 (PCIE_SUBSYS_IOMUX + 0x6C) > + > +#define IO_MGMT_SUBCTRL_BASE 0x201070000 > +#define SC_LPC_RESET_REQ_REG (IO_MGMT_SUBCTRL_BASE + 0x0a58) > +#define SC_LPC_RESET_DREQ_REG (IO_MGMT_SUBCTRL_BASE + 0x0a5c) > +#define SC_LPC_SEL (IO_MGMT_SUBCTRL_BASE + 0x2400) > + > + > +#define LPCD06_BASE 0x201190000 > +#define LPC_FIRM_SPACE0_CFG (LPCD06_BASE + 0x100) > +#define LPC_FIRM_SPACE1_CFG (LPCD06_BASE + 0x104) > +#define LPC_FIRM_SPACE2_CFG (LPCD06_BASE + 0x108) > +#define LPC_FIRM_SPACE3_CFG (LPCD06_BASE + 0x10C) > +#define LPC_FIRM_SPACE4_CFG (LPCD06_BASE + 0x110) > +#define LPC_FIRM_SPACE5_CFG (LPCD06_BASE + 0x114) > +#define LPC_FIRM_SPACE6_CFG (LPCD06_BASE + 0x118) > +#define LPC_FIRM_SPACE7_CFG (LPCD06_BASE + 0x11C) > +#define LPC_MEM_SPACE0_CFG (LPCD06_BASE + 0x120) > +#define LPC_MEM_SPACE1_CFG (LPCD06_BASE + 0x124) > +#define LPC_MEM_SPACE2_CFG (LPCD06_BASE + 0x128) > +#define LPC_MEM_SPACE3_CFG (LPCD06_BASE + 0x12C) > +#define LPC_MEM_SPACE4_CFG (LPCD06_BASE + 0x130) > +#define LPC_MEM_SPACE5_CFG (LPCD06_BASE + 0x134) > +#define LPC_MEM_SPACE6_CFG (LPCD06_BASE + 0x138) > + > +#define LPCD06_START_REG (LPCD06_BASE + 0x00) > +#define LPCD06_OP_STATUS_REG (LPCD06_BASE + 0x04) > +#define LPCD06_IRQ_ST_REG (LPCD06_BASE + 0x08) > +#define LPCD06_OP_LEN_REG (LPCD06_BASE + 0x10) > +#define LPCD06_CMD_REG (LPCD06_BASE + 0x14) > +#define LPCD06_ADDR_REG (LPCD06_BASE + 0x20) > +#define LPCD06_WDATA_REG (LPCD06_BASE + 0x24) > +#define LPCD06_RDATA_REG (LPCD06_BASE + 0x28) > + > +#define LPC_SIRQ_CTR0 (LPCD06_BASE + 0x80) > +#define LPC_SIRQ_CTR1 (LPCD06_BASE + 0x84) > +#define LPC_SIRQ_INT_MASK (LPCD06_BASE + 0x94) > + > + > #define PCIE_SUBSYS_IO_MUX 0xA0170000 > #define PCIE_SUBSYS_IOMG033 (PCIE_SUBSYS_IO_MUX + 0x84) > #define PCIE_SUBSYS_IOMG035 (PCIE_SUBSYS_IO_MUX + 0x8C) > -- > 2.17.0 >